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DM8127 ISS parallel并行接口 接收的PCLK是否有限制?

DM8127 ISS parallel并行接口直接连接FPGA输出的并行数据,这个帧频有限制吗?是多少?有人说是165MHZ,但是我查文档,这个是HDVPSS的。ISS文档上说使用外部时钟,上限是多少?烦请各位大牛赐教,谢谢!