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omapl138 dsp cache 影响arm核

大家好:

omapl138 ddr 0xc0000000~0xc1ffffff,该地址arm核、dsp核、fpga(通过HPI)共用。

在dsp中将该地址进行cache,命令如下:

CacheEnableMAR((unsigned int)0xC0000000, (unsigned int)0x2000000);

CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K | L2CFG_L2MODE_256K);

1、首先dsp将该地址初始化为0

2、fpga写数据

3、arm读数据,发现fpga重新写的数据无效

这是为什么,总感觉dsp的cache功能影响到arm了?