当我将epwm的计数模式从上升下降沿改为下降沿或者上升沿之后模块无PWM输出信号，通过JTAG在线调试发现CMPA或者CMPB寄存器都有值，可为什么没有输出呢？
EPwm2Regs.TBPRD = (Uint16)(TLBDC_PER); //PWM period
EPwm2Regs.TBPHS.bit.TBPHS = 0;//TLBDC_PHASE(120.0f);//0; //No phase shift
EPwm2Regs.TBCTL.bit.FREE_SOFT = 2; //Free run
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;//TB_SYNC_IN;//TB_CTR_ZERO; //Send synchronization signal when counter = 0
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; //Using shadow register for PWM period
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;//TB_DISABLE; //Master, don't need load phase register
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;//TB_COUNT_UPDOWN; //TB_COUNT_UP;//Up-down mode
/* Counter compare register initialization */
EPwm2Regs.CMPA.bit.CMPA = TLBDC_CMPA(0);//TLBDC_CMPA(0.3);//cmpa=zkb*prd(s1),zkb=pi_out
EPwm2Regs.CMPB.bit.CMPB = TLBDC_CMPB(0);//TLBDC_CMPB(0.3);//phase=180; zkb'=pi_out,cmpb=(1-zkb')*prd=(1-pi_out)*prd (s2,pass a not logic->s3)
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;//Load new compare value when counter = period
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;//CC_CTR_ZERO;//Load new compare value when counter = zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;//Set PWM to low when counter increase and = compare A
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;//Set PWM to high when counter decrease and = compare A
EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;//Set PWM to low when counter increase and = compare A
EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR;//Set PWM to high when counter decrease and = compare A
EPwm2Regs.DBCTL.bit.IN_MODE = DBB_RED_DBA_FED;//DBA_RED_DBB_FED;//s5=1,s4=0
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//DBB_ENABLE;//DB_DISABLE;//DBB_ENABLE;// s1=0,s0=1(Q3)->0(Q2)
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;//DB_ACTV_LO;//0x00;//DB_ACTV_HIC;// s3=1,s2=0->1, Active Hi complementary
EPwm2Regs.DBFED = 0x00;//INV_DEAD_CYCLE;// FED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBRED = 0;//INV_DEAD_CYCLE;// RED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBCTL.bit.OUTSWAP = 0x03;
//add soca
EPwm2Regs.ETSEL.bit.SOCAEN=ET_ENABLE;//enable
EPwm2Regs.ETSEL.bit.SOCASEL=ET_CTR_PRDZERO;//ET_CTR_PRDZERO;
EPwm2Regs.ETPS.bit.SOCAPRD=ET_1ST;//divide frequency, page69/117.
//1 1 2 3-Generate the EPWMxSOCA pulse on the first second third event:
//2 Once the SOCA pulse is generated, the ETPS[SOCACNT] bits will automatically be cleared.
EPwm2Regs.ETSEL.bit.SOCBEN=ET_ENABLE;//enable
EPwm2Regs.ETSEL.bit.SOCBSEL=ET_CTR_PRDZERO;//ET_CTR_ZERO;
EPwm2Regs.ETPS.bit.SOCBPRD=ET_1ST;//divide frequency
//3 Generate the EPWMxSOCA pulse on the first event: ETPS[SOCACNT] = 0,1
EPwm2Regs.ETSEL.bit.INTEN=ET_DISABLE;
EPwm2Regs.ETPS.bit.INTPRD=ET_DISABLE;
