如何将28377D的ADC采样率达到最高

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e2e.ti.com/.../584025

The ADC conversion time is given in table Table 5-51. "ADC Timings in 12-Bit Mode (SYSCLK Cycles)". From this table, the conversion time when the ADC is operating /4 of the SYSCLK (typical when the CPU is running at 200MHz) would be 44 cycles. The minimum S+H is 75ns @ 200MHz = 15 cycles. Total ADC time between samples therefore needs to be at least 59 cycles. If you want 10MSPS then a sample has to occur every 20 cycles. With 4 ADCs each ADC samples once every 80 cycles, which is > than 59, so possible.

To generate the triggers, you will probably want to use 2 synchronized ePWMs, each with a period of 80 cycles. Each ePWM can generate triggers for two of the ADCs.

As far as memory, 10MSPS * 0.25 seconds = 2.5M samples. Each sample is 12-bit, so they take up a full 16-bit word. There is as much as 106K x 16 on-chip RAM, so you are definitely going to need an external memory connected to the EMIF peripheral. It should be possible for the DMA to move ADC samples to the EMIF, and for the EMIF to write to external memory without CPU intervention.

As far as performance, take a look at the ENOB section in the datasheet table "ADC Characteristics (12-Bit Single-Ended Mode)". In this interleaved cases, the ADCs are not operating in lock-step, so we have to consider the "Asynchronous ADCs" performance specification. For the ZWT package (BGA) this is 10.9 bits and for the PTP pacakge (QFP) this is 9.7 bits. Both should be OK, but note that the single-core F28377x launchpad uses the PZP package, which has bad enough performance in this case that it is "not supported". The PZP package also only has 2 ADCs pinned-out, so you probably would want to get the F283779D dual-core launchpad if you want to use a launchpad as your development platform for this.

In addition to the non-lockstep performance penalty, interleaving ADCs will give you some very significant tones due to ADC-to-ADC gain, offset, and linearity mismatch. We specify the ADC-to-ADC gain and offset error in the datasheet as +/-4 LSBs and +/-2 LSBs (both typical), so I think you should probably be OK to meet 8-bits of performance.