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如何用DSP配置实现电感电流零界CRM发波

Other Parts Discussed in Thread: C2000WARE

你好,

如何用DSP实现电感电流零界CRM发波

1、是否有配置/方案? 或者用模拟芯片实现方案推荐?

2、CMPSSx+DCxEVTx+TBsysnc

同样程序+信号发生器分别给三角波和脉冲波测试结果以下:

三角波测试异常:50~270k三角波,PWM丢波/没波/高电平时间变化不对, 270k=高时间600ns,<---------------------为什么丢波/没波/高电平时间变化不对比下方脉冲波效果差?怎样修改实现?
三角波测试正常:50~270k三角波,PWM一直高电平,关三角波PWM默认20K高3.5us

脉冲波测试异常:50~250脉冲波,PWM跟随过零发波正常,但高时间不对:40k=990ns 80k=2us 100k=2.2us 150k=2.8 200k=2.8us 250k=3us 300k=直高,关=默认20k3.2us<---------------------跟随电流过零发波没问题,就是不同频率下高电平时间不是3.5us为什么?
脉冲波测试正常:300k脉冲波,pwm一直高电平,关三角波PWM默认20K高3.5us

  • 你好,请问你使用的是哪款芯片?
  • TI官方有提供一个参考设计“基于 GaN 的高效率 1.6kW 高密度 1MHz CrM 图腾柱 PFC 转换器参考设计”你可以参考一下:
    www.ti.com.cn/.../TIDA-00961
    但是关于这个参考设计我没有使用经验,相关技术问题建议你去E2E上咨询,E2E上有专业的工程师或者产线BU为你提供支持。
  • 感谢您回复,“建议你去E2E上咨询”从哪里进去?现在这个平台不是吗
  • 抱歉,忘了贴上网址了。这里是中文E2E论坛,建议你去英文E2E论坛上咨询,因为英文E2E论坛有更多专业工程师和产品线BU,能给到你更全面的技术支持:e2e.ti.com/.../171
  • 参考已阅读不错就是比较泛,假如要知道软件细节应该如何进入或如何申请?谢谢
  • 软件信息你可以参考这篇文档:www.ti.com.cn/.../tidudu4c.pdf
    具体软件包根据文档上提到的,可以在以下路径找到软件例程(需要安装C2000WARE及附带的DigitalPower SDK):
    C:\ti\c2000\C2000Ware_DigitalPower_SDK_3_00_01_00\solutions\tida_00961
  • 大家好

      相关配置代码和波形如下,请问是什么原因,尝试了找不到原因,怎样实现,请提供相关技术支持分析(转发给有相关经验也行),感谢支持。

    我们采用方式:CMPSSx+DCxEVTx+TBsysnc

    同样程序+信号发生器分别给三角波和脉冲波测试结果以下:

    三角波测试异常:50~270k三角波,PWM丢波/没波/高电平时间变化不对, 270k=高时间600ns,<---------------------为什么丢波/没波/高电平时间变化不对?比下方脉冲波效果差?怎样修改实现?
    三角波测试正常:50~270k三角波,PWM一直高电平,关三角波PWM默认20K高3.5us

    脉冲波测试异常:50~250脉冲波,PWM跟随过零发波正常,但高时间不对:40k=990ns 80k=2us 100k=2.2us 150k=2.8 200k=2.8us 250k=3us 300k=直高,关=默认20k3.2us<---------------------为什么输入脉冲波可以跟随过零发波没问题? 不同频率下默认高电平时间不是3.5us为什么?
    脉冲波测试正常:300k脉冲波,pwm一直高电平,关三角波PWM默认20K高3.5us

    -------------------cmpss configuration code------------------------------------

    EALLOW;
    //  signal generator--->ADC_A3(pin10)--->CMP1HP  
    AnalogSubsysRegs.CMPHPMXSEL.bit.CMP1HPMXSEL = 3;

    // Disable CMPSS1
    Cmpss1Regs.COMPCTL.bit.COMPDACE = 0;

    // NEG signal comes from DAC
    Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;

    #if 0
    // Configure CTRIPOUT path
    Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_FILTER; // 输入方波and outpwm 50~300k ok, 输入三角波outpwm没波?
    Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_FILTER;
    //Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_LATCH; // 输入方波没波? 输入三角波没波?
    //Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_LATCH;

    /* Maximum CLKPRESCALE value provides the most time between samples */
    Cmpss1Regs.CTRIPHFILCLKCTL.bit.CLKPRESCALE = 0x1;
    /* Set SAMPWIN and THRESH */
    // Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 6;
    // Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = 6;
    Cmpss1Regs.CTRIPHFILCTL.bit.SAMPWIN = 1;
    Cmpss1Regs.CTRIPHFILCTL.bit.THRESH = 1;
    /* Reset filter logic & start filtering */
    Cmpss1Regs.CTRIPHFILCTL.bit.FILINIT = 1;
    #else
    // Configure CTRIPOUT path
    Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH; 
    Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_ASYNCH;
    // Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_SYNCH;
    // Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_SYNCH;
    #endif

    // Use VDDA as the reference for DAC
    Cmpss1Regs.COMPDACCTL.bit.DACSOURCE = 0; // DACVALS
    Cmpss1Regs.COMPDACCTL.bit.SWLOADSEL = 0; // SYSCLK
    Cmpss1Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
    Cmpss1Regs.DACHVALS.bit.DACVAL = 500; // 1--->0 trip
    //Cmpss1Regs.DACHVALS.bit.DACVAL = 10;
    //Cmpss1Regs.DACHVALS.bit.DACVAL = 2048;

    // Enable CMPSS1
    Cmpss1Regs.COMPCTL.bit.COMPDACE = 1; // ADC_A3(pin10)<----PWM/DG4062

    EDIS;

    -------------------pwm configuration code------------------------------------

    EALLOW;

    EPwm1Regs.TBCTR = 0; // Clear counter
    EPwm1Regs.TBPHS.bit.TBPHS = 0; // Set as master, phase =0
    EPwm1Regs.TBPRD = DC_DC_FREQUENCY_Khz(20); // 5000

    EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; // Phase Direction Down

    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Timebase clock pre-scale
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // High speed time pre-scale

    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
    EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;

    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_RED_DBB_FED; // IN_mode selection, A->rising B->falling
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // PWMxB inverted
    EPwm1Regs.DBCTL.bit.OUT_MODE = 0x3;

    EPwm1Regs.DBRED.bit.DBRED = DB_NS_300;//DEAD_TIME;
    EPwm1Regs.DBFED.bit.DBFED = DB_NS_300;//DEAD_TIME;

    ----------------------xbar and DCEVT configuration code------------------------------------------------------------------

    // ADC_A3(pin10)--->CMPSS1.CTRIPH--->TRIP4
    EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0;
    EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0 = 1;

    // TRIP4-->DCAH
    EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TRIPIN4; // single
    EPwm1Regs.DCAHTRIPSEL.bit.TRIPINPUT4 = 1; // multiply

    // DCAH-->DCAEVT2
    EPwm1Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI; // DCAH = low, DCAL = don't care // 0---->1 

    EPwm1Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT2; // DCAEVT2 = DCAEVT2 (not filtered)
    EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; // Take async path
    // EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_SYNC;
    EPwm1Regs.DCACTL.bit.EVT1SYNCE = 1;


  • 波形说明:CH1:ePWM发波, CH2:信号发生器输入模拟电感电流
  • 波形说明:CH1:ePWM发波, CH2:信号发生器输入模拟电感电流
  • 你好,如上所述,目前这款套件国内没有工程师支持,相关技术问题建议你去英文E2E上咨询,E2E上有专业的工程师或者产线BU为你提供支持:e2e.ti.com/.../171
    或者去英文E2E你这边有什么顾虑吗?