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TMS570LC4357开发需要的头文件

Other Parts Discussed in Thread: TMS570LC4357, HALCOGEN

TMS570LC4357开发,找不到芯片的头文件,还有就是找不到相关的例程,哪位可以给一下相关链接,谢谢了!

  • http://www.ti.com/lsds/ti/microcontrollers_16-bit_32-bit/c2000_performance/safety/tools_software.page

  • TI技术,您好,我最近在使用TMS570LS1227ZWT这款芯片,在使用SPI(不是Mibspi)时,用逻辑分析仪抓时序,发现能发,也能收,但是在操作外部SPI FLASH器件的时候,器件的ID居然读不出来,查看手册什么的配置感觉也没有错误,但是就是不知道为什么这样,我是用HALCogen这个UI软件生成的库代码,然后开发的,一下是我的代码,请您看下哪里设置是否有错误。

    /** @b initialize @b SPI3 */

        /** bring SPI out of reset */
        spiREG3->GCR0 = 0U;
        spiREG3->GCR0 = 1U;

        /** SPI3 master mode and clock configuration */
        spiREG3->GCR1 = (spiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U)  /* CLOKMOD */
                      | 1U);  /* MASTER */

        /** SPI3 enable pin configuration */
        spiREG3->INT0 = (spiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U);  /* ENABLE HIGHZ */

        /** - Delays */
        spiREG3->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
                       | (uint32)((uint32)1U << 16U)  /* T2CDELAY */
                       | (uint32)((uint32)0U << 8U)   /* T2EDELAY */
                       | (uint32)((uint32)0U << 0U);  /* C2EDELAY */

        /** - Data Format 0 */
        spiREG3->FMT0 = (uint32)((uint32)0U << 24U)  /* wdelay */
                      | (uint32)((uint32)0U << 23U)  /* parity Polarity */
                      | (uint32)((uint32)0U << 22U)  /* parity enable */
                      | (uint32)((uint32)0U << 21U)  /* wait on enable */
                      | (uint32)((uint32)0U << 20U)  /* shift direction */
                      | (uint32)((uint32)0U << 17U)  /* clock polarity */
                      | (uint32)((uint32)0U << 16U)  /* clock phase */
                      | (uint32)((uint32)89U << 8U) /* baudrate prescale */
                      | (uint32)((uint32)8U << 0U);  /* data word length */

        /** - Data Format 1 */
        spiREG3->FMT1 = (uint32)((uint32)0U << 24U)  /* wdelay */
                      | (uint32)((uint32)0U << 23U)  /* parity Polarity */
                      | (uint32)((uint32)0U << 22U)  /* parity enable */
                      | (uint32)((uint32)0U << 21U)  /* wait on enable */
                      | (uint32)((uint32)0U << 20U)  /* shift direction */
                      | (uint32)((uint32)0U << 17U)  /* clock polarity */
                      | (uint32)((uint32)0U << 16U)  /* clock phase */
                      | (uint32)((uint32)89U << 8U) /* baudrate prescale */
                      | (uint32)((uint32)8U << 0U);  /* data word length */

        /** - Data Format 2 */
        spiREG3->FMT2 = (uint32)((uint32)0U << 24U)  /* wdelay */
                      | (uint32)((uint32)0U << 23U)  /* parity Polarity */
                      | (uint32)((uint32)0U << 22U)  /* parity enable */
                      | (uint32)((uint32)0U << 21U)  /* wait on enable */
                      | (uint32)((uint32)0U << 20U)  /* shift direction */
                      | (uint32)((uint32)0U << 17U)  /* clock polarity */
                      | (uint32)((uint32)0U << 16U)  /* clock phase */
                      | (uint32)((uint32)89U << 8U) /* baudrate prescale */
                      | (uint32)((uint32)8U << 0U);  /* data word length */

        /** - Data Format 3 */
        spiREG3->FMT3 = (uint32)((uint32)0U << 24U)  /* wdelay */
                      | (uint32)((uint32)0U << 23U)  /* parity Polarity */
                      | (uint32)((uint32)0U << 22U)  /* parity enable */
                      | (uint32)((uint32)0U << 21U)  /* wait on enable */
                      | (uint32)((uint32)0U << 20U)  /* shift direction */
                      | (uint32)((uint32)0U << 17U)  /* clock polarity */
                      | (uint32)((uint32)0U << 16U)  /* clock phase */
                      | (uint32)((uint32)89U << 8U) /* baudrate prescale */
                      | (uint32)((uint32)8U << 0U);  /* data word length */

        /** - set interrupt levels */
        spiREG3->LVL = (uint32)((uint32)0U << 9U)  /* TXINT */
                     | (uint32)((uint32)0U << 8U)  /* RXINT */
                     | (uint32)((uint32)0U << 6U)  /* OVRNINT */
                     | (uint32)((uint32)0U << 4U)  /* BITERR */
                     | (uint32)((uint32)0U << 3U)  /* DESYNC */
                     | (uint32)((uint32)0U << 2U)  /* PARERR */
                     | (uint32)((uint32)0U << 1U) /* TIMEOUT */
                     | (uint32)((uint32)0U << 0U);  /* DLENERR */

        /** - clear any pending interrupts */
        spiREG3->FLG |= 0xFFFFU;

        /** - enable interrupts */
        spiREG3->INT0 = (spiREG3->INT0 & 0xFFFF0000U)
                      | (uint32)((uint32)0U << 9U)  /* TXINT */
                      | (uint32)((uint32)0U << 8U)  /* RXINT */
                      | (uint32)((uint32)0U << 6U)  /* OVRNINT */
                      | (uint32)((uint32)0U << 4U)  /* BITERR */
                      | (uint32)((uint32)0U << 3U)  /* DESYNC */
                      | (uint32)((uint32)0U << 2U)  /* PARERR */
                      | (uint32)((uint32)0U << 1U) /* TIMEOUT */
                      | (uint32)((uint32)0U << 0U);  /* DLENERR */

        /** @b initialize @b SPI3 @b Port */

        /** - SPI3 Port output values */
        spiREG3->PC3 =    (uint32)((uint32)1U << 0U)  /* SCS[0] */
                        | (uint32)((uint32)1U << 1U)  /* SCS[1] */
                        | (uint32)((uint32)1U << 2U)  /* SCS[2] */
                        | (uint32)((uint32)1U << 3U)  /* SCS[3] */
                        | (uint32)((uint32)1U << 4U)  /* SCS[4] */
                        | (uint32)((uint32)1U << 5U)  /* SCS[5] */
                        | (uint32)((uint32)0U << 8U)  /* ENA */
                        | (uint32)((uint32)0U << 9U)  /* CLK */
                        | (uint32)((uint32)0U << 10U)  /* SIMO */
                        | (uint32)((uint32)0U << 11U); /* SOMI */

        /** - SPI3 Port direction */
        spiREG3->PC1  =   (uint32)((uint32)1U << 0U)  /* SCS[0] */
                        | (uint32)((uint32)1U << 1U)  /* SCS[1] */
                        | (uint32)((uint32)1U << 2U)  /* SCS[2] */
                        | (uint32)((uint32)1U << 3U)  /* SCS[3] */
                        | (uint32)((uint32)1U << 4U)  /* SCS[4] */
                        | (uint32)((uint32)1U << 5U)  /* SCS[5] */
                        | (uint32)((uint32)0U << 8U)  /* ENA */
                        | (uint32)((uint32)1U << 9U)  /* CLK */
                        | (uint32)((uint32)1U << 10U)  /* SIMO */
                        | (uint32)((uint32)0U << 11U); /* SOMI */

        /** - SPI3 Port open drain enable */
        spiREG3->PC6  =   (uint32)((uint32)0U << 0U)  /* SCS[0] */
                        | (uint32)((uint32)0U << 1U)  /* SCS[1] */
                        | (uint32)((uint32)0U << 2U)  /* SCS[2] */
                        | (uint32)((uint32)0U << 3U)  /* SCS[3] */
                        | (uint32)((uint32)0U << 4U)  /* SCS[4] */
                        | (uint32)((uint32)0U << 5U)  /* SCS[5] */
                        | (uint32)((uint32)0U << 8U)  /* ENA */
                        | (uint32)((uint32)0U << 9U)  /* CLK */
                        | (uint32)((uint32)0U << 10U)  /* SIMO */
                        | (uint32)((uint32)0U << 11U); /* SOMI */

        /** - SPI3 Port pullup / pulldown selection */
        spiREG3->PC8  =   (uint32)((uint32)1U << 0U)  /* SCS[0] */
                        | (uint32)((uint32)1U << 1U)  /* SCS[1] */
                        | (uint32)((uint32)1U << 2U)  /* SCS[2] */
                        | (uint32)((uint32)1U << 3U)  /* SCS[3] */
                        | (uint32)((uint32)1U << 4U)  /* SCS[4] */
                        | (uint32)((uint32)1U << 5U)  /* SCS[5] */
                        | (uint32)((uint32)1U << 8U)  /* ENA *

    我用的SPI轮训方式,没有使用中断