This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430f5529 的DCO频率设置

最近在测试DCO频率时  对于设置有一些疑问,请各位大神帮忙解释一下

我外部晶振XT2是8M的, 在测试产生 4M 8M 16M 32M MCLK时 发现产生8M的不正确,请问该如何配置呢?

UCSCTL1  和  UCSCTL0  关系不是很清楚啊

以下是代码

void main(void)
{


WDTCTL = WDTPW + WDTHOLD; //关闭看门狗
P7SEL |= BIT7;
P7DIR |= BIT7;//测量MCLK用

P5SEL |= BIT2+BIT3;
UCSCTL6 &= ~XT2OFF; //打开XT2

/*********************寄存器配置部分********************8M晶振**********/

/*16.47
__bis_SR_register(SCG0);
UCSCTL0 = 0x0000;
UCSCTL1 = DCORSEL_4;   //DCO频率范围在28.2MHZ以下
UCSCTL2 = FLLD_0 + 1;   //D=1,N=1
UCSCTL3 = SELREF_5 + FLLREFDIV_0; //n=1,FLLREFCLK时钟源为XT2CLK  8M;DCOCLK=D*(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELM__DCOCLK; //MCLK的时钟源为DCOCLK
__bic_SR_register(SCG0);   //Enable the FLL control loop
*/

__bis_SR_register(SCG0);
UCSCTL0 = 0x0000;
UCSCTL1 = DCORSEL_4; //DCO频率范围在28.2MHZ以下
UCSCTL2 = FLLD_0 + 1; //D=1,N=1
UCSCTL3 = SELREF_5 + FLLREFDIV_1; //n=2,FLLREFCLK时钟源为XT2CLK;DCOCLK=D*(N+1)*(FLLREFCLK/n);
UCSCTL4 = SELM__DCOCLK; //MCLK的时钟源为DCOCLK
__bic_SR_register(SCG0); //Enable the FLL control loop

while(1);

}

  • 您可以看一下下面的代码:

    /* --COPYRIGHT--,BSD_EX
     * Copyright (c) 2012, Texas Instruments Incorporated
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     *
     *******************************************************************************
     * 
     *                       MSP430 CODE EXAMPLE DISCLAIMER
     *
     * MSP430 code examples are self-contained low-level programs that typically
     * demonstrate a single peripheral function or device feature in a highly
     * concise manner. For this the code may rely on the device's power-on default
     * register values and settings such as the clock configuration and care must
     * be taken when combining code from several examples to avoid potential side
     * effects. Also see www.ti.com/grace for a GUI- and www.ti.com/msp430ware
     * for an API functional library-approach to peripheral configuration.
     *
     * --/COPYRIGHT--*/
    //******************************************************************************
    //  MSP430F552x Demo - XT2 sources MCLK & SMCLK
    //
    //  Description: This program demonstrates using XT2 to source MCLK. XT1 is not
    //  connected in this case.
    //
    //  By default, LFXT1 is requested by the following modules:
    //     - FLL
    //     - ACLK
    //  If LFXT1 is NOT used and if the user does not change the source modules,
    //  it causes the XT1xxOFIFG flag to be set because it is constantly looking
    //  for LFXT1. OFIFG, global oscillator fault flag, will always be set if LFXT1
    //  is set. Hence, it is important to ensure LFXT1 is no longer being sourced
    //  if LFXT1 is NOT used.
    //  MCLK = XT2
    //
    //               MSP430F552x
    //             -----------------
    //        /|\ |                 |
    //         |  |                 |
    //         ---|RST              |
    //            |            XT2IN|-
    //            |                 | HF XTAL (455kHz - 16MHz)
    //            |           XT2OUT|-
    //            |                 |
    //            |             P7.7|--> MCLK = XT2
    //            |             P2.2|--> SMCLK = XT2
    //
    //   Bhargavi Nisarga
    //   Texas Instruments Inc.
    //   April 2009
    //   Built with CCSv4 and IAR Embedded Workbench Version: 4.21
    //******************************************************************************
    
    #include <msp430.h>
    
    int main(void)
    {
      WDTCTL = WDTPW + WDTHOLD;                 // Stop watchdog timer
    
      P2DIR |= BIT2;                            // SMCLK set out to pins
      P2SEL |= BIT2;                            
      P7DIR |= BIT7;                            // MCLK set out to pins
      P7SEL |= BIT7;
      
      P5SEL |= BIT2+BIT3;                       // Port select XT2
    
      UCSCTL6 &= ~XT2OFF;                       // Enable XT2 
      UCSCTL3 |= SELREF_2;                      // FLLref = REFO
                                                // Since LFXT1 is not used,
                                                // sourcing FLL with LFXT1 can cause
                                                // XT1OFFG flag to set
      UCSCTL4 |= SELA_2;                        // ACLK=REFO,SMCLK=DCO,MCLK=DCO
    
      // Loop until XT1,XT2 & DCO stabilizes - in this case loop until XT2 settles
      do
      {
        UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                                // Clear XT2,XT1,DCO fault flags
        SFRIFG1 &= ~OFIFG;                      // Clear fault flags
      }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
    
      UCSCTL6 &= ~XT2DRIVE0;                    // Decrease XT2 Drive according to
                                                // expected frequency
      UCSCTL4 |= SELS_5 + SELM_5;               // SMCLK=MCLK=XT2
    
      while(1);                                 // Loop in place
    }
    
    

  • UCSCTL0寄存器设置为0x0000,因为这些位在运行期间由FLL自动修改。您可以在用户指南的统一时钟系统(UCS)部分中阅读更多相关信息。当设备开始运行时,它们不会保持在0x0000。

    更多信息您可以看一下

    e2echina.ti.com/.../16107
  • 感谢,是因为我没有检测晶振是否起振!太感谢了
  • 很高兴您能解决问题!
  • 再问您个问题,用XT2做为FLL的时钟源,应该如何设置呢?
  • 应该是

    UCSCTL3 |= SELREF_5; //设置FLL参考时钟源为XT2CLK
  • 我也是这样设置的,但是计算出来的DCO总是有问题,比如我用XT2 8M的晶振,想产生一个分频的4M mclk 配置的为
    __bis_SR_register(SCG0);
    UCSCTL0 = 0x0000;
    UCSCTL1 = DCORSEL_3; //
    UCSCTL2 = FLLD_0 + 1; //D=1,N=1
    UCSCTL3 = SELREF_5 + FLLREFDIV_2; //n=2,FLLREFCLK时钟源为XT2CLK;DCOCLK=D*(N+1)*(FLLREFCLK/n);
    UCSCTL4 = SELM__DCOCLK; //MCLK的时钟源为DCOCLK
    __bic_SR_register(SCG0); //Enable the FLL control loop


    得到的竟然是7.2M左右。
  • 程序的注释里写的很明白啊

    DCOCLK=D*(N+1)*(FLLREFCLK/n);