MSP430F5529计时器中断问题

想用timerA_0的比较模式实现pwm，从而实现单周期的短脉冲。首先设定MCLK与SMCLK时钟均为DCO频率25MHz。其次，利用TA0CCR0=25000，TA0CCR1=24999，以及TA0CCTL1 = OUTMOD_3实现set/reset输出。于此同时，程序让LED灯闪烁。另外设置了TAIE中断使能，测试起见，中断处理函数没写内容，但程序跑了结果LED灯并没有闪烁，而且调试发现程序在中断处理函数中死循环，请问是何原因，多谢！！！

#include <msp430.h>				


/**
 * blink.c
 */


void main(void)
{
	WDTCTL = WDTPW | WDTHOLD;		// stop watchdog timer
	P1SEL |= BIT2;
	P1DIR |= BIT2;                  // P1.2 -> TA0.1
	P1DIR |= BIT0;					// P1.0 as output (LED)

	setupDCO();

	P1OUT = 0x0000;

	// set timer A
	TA0CCTL1 = OUTMOD_3;                      // CCR1 set/reset
	TA0CCR1 = 24999;
	TA0CCR0 = 25000;
	TA0CTL = TAIE | TASSEL_2 | MC_2 | TACLR;         // SMCLK, continue mode, clear TAR
	__delay_cycles(100);

	__enable_interrupt();
	_BIS_SR(GIE);          // Enter LPM0 w/ interrupt

	while(1)
	{
	    P1OUT = 0x0001;
	    __delay_cycles(2500000);
	    P1OUT = 0x0000;
	    __delay_cycles(12500000);
	    //TA0CTL = TAIE | TASSEL_2 | MC_2 | TACLR;
	}
}

// Timer A0 interrupt service routine
#pragma vector=TIMER0_A0_VECTOR
__interrupt void TIMER0_A0_ISR(void)
{

}


void SetVCoreUp (unsigned int level)
{
    // Open PMM registers for write access
    PMMCTL0_H = 0xA5;
    // Set SVS/SVM high side new level
    SVSMHCTL = SVSHE + SVSHRVL0 * level + SVMHE + SVSMHRRL0 * level;
    // Set SVM low side to new level
    SVSMLCTL = SVSLE + SVMLE + SVSMLRRL0 * level;
    // Wait till SVM is settled
    while ((PMMIFG & SVSMLDLYIFG) == 0);
    // Clear already set flags
    PMMIFG &= ~(SVMLVLRIFG + SVMLIFG);
    // Set VCore to new level
    PMMCTL0_L = PMMCOREV0 * level;
    // Wait till new level reached
    if ((PMMIFG & SVMLIFG))
    while ((PMMIFG & SVMLVLRIFG) == 0);
    // Set SVS/SVM low side to new level
    SVSMLCTL = SVSLE + SVSLRVL0 * level + SVMLE + SVSMLRRL0 * level;
    // Lock PMM registers for write access
    PMMCTL0_H = 0x00;
}

void setupDCO(void)
{

      /* Power settings */
      SetVCoreUp(1u);
      SetVCoreUp(2u);
      SetVCoreUp(3u);


      UCSCTL3 = SELREF__REFOCLK;    // select REFO as FLL source
      UCSCTL6 = XT1OFF | XT2OFF;    // turn off XT1 and XT2

      /* Initialize DCO to 25.00MHz */
      __bis_SR_register(SCG0);                  // Disable the FLL control loop
      UCSCTL0 = 0x0000u;                        // Set lowest possible DCOx, MODx
      UCSCTL1 = DCORSEL_6;                      // Set RSELx for DCO = 50 MHz
      UCSCTL2 = 762u;                            // Set DCO Multiplier for 25MHz
                                                // (N + 1) * FLLRef = Fdco
                                                // (762 + 1) * 32768 = 25.00MHz
      UCSCTL4 = SELA__REFOCLK | SELS__DCOCLK | SELM__DCOCLK;
      __bic_SR_register(SCG0);                  // Enable the FLL control loop

      // Worst-case settling time for the DCO when the DCO range bits have been
      // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
      // UG for optimization.
      // 32*32*25MHz/32768Hz = 781250 = MCLK cycles for DCO to settle
      __delay_cycles(781250u);


      /* Loop until XT1,XT2 & DCO fault flag is cleared */
      do
      {
        UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG  + DCOFFG);
                                                // Clear XT2,XT1,DCO fault flags
        SFRIFG1 &= ~OFIFG;                      // Clear fault flags
      }
      while (SFRIFG1&OFIFG);                    // Test oscillator fault flag


}