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MSP432P4001R SPI

Other Parts Discussed in Thread: ADS1299EEGFE-PDK

我想要利用MSP432P401R(MASTER)寫一個可以透過spi發送命令並且接收slave回傳的數據的程式碼,我的想法是指令可以透過main迴圈裡面的SPI_transmitData(EUSCI_B0_BASE, TXData);發送,假設我有5個指令,那我可以在main透過連續5行此指令,只需更換TXData變數,然後發送給slave,並在中斷處,透過RXData = SPI_receiveData(EUSCI_B0_BASE);來接收從slave回傳的資料,但根據以下的程式碼,我的clock在示波器上顯示為'3.3V的一條直線,完全沒有嬰出現的波行,我不懂發生了什麼事?麻煩給予指教謝謝!

/* --COPYRIGHT--,BSD
 * Copyright (c) 2017, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * --/COPYRIGHT--*/
/******************************************************************************
 * MSP432 SPI - 3-wire Master Incremented Data
 *
 * This example shows how SPI master talks to SPI slave using 3-wire mode.
 * Incrementing data is sent by the master starting at 0x01. Received data is
 * expected to be same as the previous transmission.  eUSCI RX ISR is used to
 * handle communication with the CPU, normally in LPM0. Because all execution 
 * after LPM0 is in ISRs, initialization waits for DCO to stabilize against 
 * ACLK.
 *
 * Note that in this example, EUSCIB0 is used for the SPI port. If the user
 * wants to use EUSCIA for SPI operation, they are able to with the same APIs
 * with the EUSCI_AX parameters.
 *
 * ACLK = ~32.768kHz, MCLK = SMCLK = DCO 3MHz
 *
 * Use with SPI Slave Data Echo code example.
 *
 *                MSP432P401
 *              -----------------
 *             |                 |
 *             |                 |
 *             |                 |
 *             |             P1.6|-> Data Out (UCB0SIMO)
 *             |                 |
 *             |             P1.7|<- Data In (UCB0SOMI)
 *             |                 |
 *             |             P1.5|-> Serial Clock Out (UCB0CLK)
 *******************************************************************************/
/* DriverLib Includes */
#include <ti/devices/msp432p4xx/driverlib/driverlib.h>

/* Standard Includes */
#include <stdint.h>
#include <stdbool.h>

/* Statics */
static volatile uint8_t RXData = 0;
static uint8_t TXData = 0;

//![Simple SPI Config]
/* SPI Master Configuration Parameter */
const eUSCI_SPI_MasterConfig spiMasterConfig =
{
        EUSCI_B_SPI_CLOCKSOURCE_SMCLK,             // SMCLK Clock Source
        3000000,                                   // SMCLK = DCO = 3MHZ
        500000,                                    // *** = 500khz
        EUSCI_B_SPI_MSB_FIRST,                     // MSB First
        EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT,    // Phase
        EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH, // High polarity
        EUSCI_B_SPI_3PIN                           // 3Wire SPI Mode
};
//![Simple SPI Config]

int main(void)
{
    /* Halting WDT  */
    WDT_A_holdTimer();

    //![Simple SPI Example]
    /* Selecting P1.5 P1.6 and P1.7 in SPI mode */
    GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P1,
            GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7, GPIO_PRIMARY_MODULE_FUNCTION);

    /* Configuring SPI in 3wire master mode */
    SPI_initMaster(EUSCI_B0_BASE, &spiMasterConfig);

    /* Enable SPI module */
    SPI_enableModule(EUSCI_B0_BASE);

    /* Enabling interrupts */
    SPI_enableInterrupt(EUSCI_B0_BASE, EUSCI_B_SPI_RECEIVE_INTERRUPT);
    Interrupt_enableInterrupt(INT_EUSCIB0);
    Interrupt_enableSleepOnIsrExit();
    //![Simple SPI Example]
    TXData = 0x01;

    /* Polling to see if the TX buffer is ready */
    while (!(SPI_getInterruptStatus(EUSCI_B0_BASE,EUSCI_B_SPI_TRANSMIT_INTERRUPT)));

    /* Transmitting data to slave */
    SPI_transmitData(EUSCI_B0_BASE, TXData);



    PCM_gotoLPM0();
    __no_operation();
}

//******************************************************************************
//
//This is the EUSCI_B0 interrupt vector service routine.
//
//******************************************************************************
void EUSCIB0_IRQHandler(void)
{
    uint32_t status = SPI_getEnabledInterruptStatus(EUSCI_B0_BASE);
    uint32_t jj;

    SPI_clearInterruptFlag(EUSCI_B0_BASE, status);

    if(status & EUSCI_B_SPI_RECEIVE_INTERRUPT)
    {
        /* USCI_B0 TX buffer ready? */
        while (!(SPI_getInterruptStatus(EUSCI_B0_BASE, EUSCI_B_SPI_TRANSMIT_INTERRUPT)));

        RXData = SPI_receiveData(EUSCI_B0_BASE);

        /* Send the next data packet */
        //SPI_transmitData(EUSCI_B0_BASE, ++TXData);

        /* Delay between transmissions for slave to process information */
        //for(jj=50;jj<50;jj++);
    }

}

  • 您现在是想实现3线SPI通信?

    那您可以参考下 C:\ti\simplelink_msp432p4_sdk_3_10_00_08\examples\nortos\MSP_EXP432P401R\registerLevel 内的

    msp432p401x_euscib0_spi_09 (master)和 msp432p401x_euscib0_spi_10(slave)

    能描述下您现在使用的硬件吗?
  • 3線通信沒錯!
    硬件的部分目前是利用兩塊MSP432進行溝通,完成後,未來會改成MSP432P401R(主) ADS1299EEGFE-PDK(從)
    那個範例我也有參考過,但是有些地方我不知道該如何撰寫,以下code是我利用msp432p401x_euscib0_spi_09(主)撰寫修改的,但我不知道如果我要用這個範例發送多個指令,該如何撰寫,我對於中斷函式不太了解該如何運用,




    /* --COPYRIGHT--,BSD_EX
    * Copyright (c) 2014, Texas Instruments Incorporated
    * All rights reserved.
    *
    * Redistribution and use in source and binary forms, with or without
    * modification, are permitted provided that the following conditions
    * are met:
    *
    * * Redistributions of source code must retain the above copyright
    * notice, this list of conditions and the following disclaimer.
    *
    * * Redistributions in binary form must reproduce the above copyright
    * notice, this list of conditions and the following disclaimer in the
    * documentation and/or other materials provided with the distribution.
    *
    * * Neither the name of Texas Instruments Incorporated nor the names of
    * its contributors may be used to endorse or promote products derived
    * from this software without specific prior written permission.
    *
    * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    *
    *******************************************************************************
    *
    * MSP432 CODE EXAMPLE DISCLAIMER
    *
    * MSP432 code examples are self-contained low-level programs that typically
    * demonstrate a single peripheral function or device feature in a highly
    * concise manner. For this the code may rely on the device's power-on default
    * register values and settings such as the clock configuration and care must
    * be taken when combining code from several examples to avoid potential side
    * effects. Also see www.ti.com/.../mspdriverlib for an API functional
    * library & https://dev.ti.com/pinmux/ for a GUI approach to peripheral configuration.
    *
    * --/COPYRIGHT--*/
    //******************************************************************************
    // MSP432P401 Demo - eUSCI_B0, SPI 3-Wire Master with clock polarity high
    //
    // This example can be used with msp432p401x_euscib0_spi_10.c 3-wire Slave.
    //
    // Description: SPI master talks to SPI slave using 3-wire mode. This example
    // increments data sent by the master starting at 0x01. Received data is
    // expected to be same as the previous transmission RXData = TXData - 1 if
    // this example is used with msp432p401x_euscib0_spi_10.c.
    //
    // USCI RX ISR is used to handle communication with the CPU, normally in LPM0.
    //
    // MSP432P401x Master MSP432P401x Slaves
    // ----------------- -----------------
    // /|\| | /|\| |
    // | | | | | |
    // --|RST | --|RST |
    // | | | |
    // | | Data In (UCB0SIMO) | |
    // | P1.6|------------------->|P1.6 |
    // | | | |
    // | | Data OUT (UCB0SOMI)| |
    // | P1.7|<-------------------|P1.7 |
    // | | | |
    // | | S Clock (UCB0CLK) | |
    // | P1.5|------------------->|P1.5 |
    // | | | |
    //
    // William Goh
    // Texas Instruments Inc.
    // June 2016 (updated) | June 2014 (created)
    // Built with CCSv6.1, IAR, Keil, GCC
    //******************************************************************************
    #include "ti/devices/msp432p4xx/inc/msp.h"
    #include <stdint.h>

    static uint8_t RXData = 0;
    static uint8_t TXData;

    int main(void)
    {
    volatile uint32_t i;
    uint8_t previousData;

    WDT_A->CTL = WDT_A_CTL_PW | // Stop watchdog timer
    WDT_A_CTL_HOLD;

    P1->OUT &= ~BIT0;
    P1->DIR |= BIT0; // Set P1.0 LED

    P1->SEL0 |= BIT5 | BIT6 | BIT7; // Set P1.5, P1.6, and P1.7 as
    // SPI pins functionality

    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SWRST; // Put eUSCI state machine in reset
    EUSCI_B0->CTLW0 = EUSCI_B_CTLW0_SWRST | // Remain eUSCI state machine in reset
    EUSCI_B_CTLW0_MST | // Set as SPI master
    EUSCI_B_CTLW0_SYNC | // Set as synchronous mode
    EUSCI_B_CTLW0_CKPL | // Set clock polarity high
    EUSCI_B_CTLW0_MSB; // MSB first

    EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SSEL__ACLK; // ACLK
    EUSCI_B0->BRW = 0x01; // /2,fBitClock = fBRCLK/(UCBRx+1).
    EUSCI_B0->CTLW0 &= ~EUSCI_B_CTLW0_SWRST;// Initialize USCI state machine

    TXData = 0x01; // Initialize TX data to 0x01

    // Enable global interrupt
    __enable_irq();

    // Enable eUSCI_B0 interrupt in NVIC module
    NVIC->ISER[0] = 1 << ((EUSCIB0_IRQn) & 31);

    // Wake up on exit from ISR
    SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;

    // Ensures SLEEPONEXIT takes effect immediately
    __DSB();

    while(1)
    {

    EUSCI_B0->IFG |= EUSCI_B_IFG_TXIFG;// Clear TXIFG flag
    EUSCI_B0->IE |= EUSCI_B_IE_TXIE; // Enable TX interrupt
    EUSCI_B0->IFG |= EUSCI_B_IFG_RXIFG;// Clear TXIFG flag
    EUSCI_B0->IE |= EUSCI_B_IE_RXIE; // Enable TX interrupt

    __sleep();
    __no_operation(); // For debug,Remain in LPM0

    // Check the received data
    /*previousData = TXData - 1;
    if (RXData != (previousData))
    {
    // If the Received data is not equal to TXData-1, then
    // Set P1.0 LED
    P1->OUT |= BIT0;
    }
    else
    {
    P1->OUT &= ~BIT0;
    }*/

    for (i = 2000; i > 0; i--); // Delay before next transmission
    //TXData++; // Increment transmit data
    }
    }

    // SPI interrupt service routine
    void EUSCIB0_IRQHandler(void)
    {
    if (EUSCI_B0->IFG & EUSCI_B_IFG_TXIFG)
    {

    EUSCI_B0->TXBUF = TXData; // Transmit characters
    EUSCI_B0->IE &= ~EUSCI_B__TXIE;

    // Wait till a character is received
    //while (!(EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG));
    //RXData = EUSCI_B0->RXBUF;

    // Clear the receive interrupt flag
    //EUSCI_B0->IFG &= ~EUSCI_B_IFG_RXIFG;
    }
    if (EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG)
    {
    //EUSCI_B0->IE &= ~EUSCI_B__RXIE;
    // USCI_B0 TX buffer ready?
    //while (!(EUSCI_B0->IFG & EUSCI_B_IFG_TXIFG));
    RXData = EUSCI_B0->RXBUF;
    EUSCI_B0->IE &= ~EUSCI_B__RXIE;
    // Echo received data
    //EUSCI_B0->TXBUF = EUSCI_B0->RXBUF;
    }
    }
  • 先完成独立的发送和接收调试,然后再实现联合调试。先确认基本的配置没有问题,硬件没有问题。