uint8 HalUARTOpen(uint8 port, halUARTCfg_t *config)
{
#if HAL_UART_USB
(void)port;
HalUARTOpenUSB(config);
return HAL_UART_SUCCESS;
#else
return(HalUARTOpenIsr(port, config));
#endif
}
uint8 HalUARTOpenIsr(uint8 port, halUARTCfg_t *config)
{
if (uartRecord.configured)
{
HalUARTClose(port);
}
if (config->baudRate > HAL_UART_BR_115200)
{
return HAL_UART_BAUDRATE_ERROR;
}
if (((uartRecord.rx.pBuffer = osal_mem_alloc(config->rx.maxBufSize)) == NULL) ||
((uartRecord.tx.pBuffer = osal_mem_alloc(config->tx.maxBufSize)) == NULL))
{
if (uartRecord.rx.pBuffer != NULL)
{
osal_mem_free(uartRecord.rx.pBuffer);
uartRecord.rx.pBuffer = NULL;
}
return HAL_UART_MEM_FAIL;
}
if(config->flowControl)
{
IOCPinConfigPeriphOutput(GPIO_D_BASE, GPIO_PIN_3, IOC_MUX_OUT_SEL_UART1_RTS);
GPIOPinTypeUARTOutput(GPIO_D_BASE, GPIO_PIN_3);
IOCPinConfigPeriphInput(GPIO_B_BASE, GPIO_PIN_0, IOC_UARTCTS_UART1);
GPIOPinTypeUARTInput(GPIO_B_BASE, GPIO_PIN_0);
}
IntEnable(HAL_UART_INT_CTRL);
uartRecord.configured = TRUE;
uartRecord.baudRate = config->baudRate;
uartRecord.flowControl = config->flowControl;
uartRecord.flowControlThreshold = (config->flowControlThreshold > config->rx.maxBufSize) ? 0 :
config->flowControlThreshold;
uartRecord.idleTimeout = config->idleTimeout;
uartRecord.rx.maxBufSize = config->rx.maxBufSize;
uartRecord.tx.maxBufSize = config->tx.maxBufSize;
uartRecord.intEnable = config->intEnable;
uartRecord.callBackFunc = config->callBackFunc;
UARTConfigSetExpClk(HAL_UART_PORT, SysCtrlClockGet(), UBRRTable[uartRecord.baudRate],
(UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE));
/* FIFO level set to 1/8th for both RX and TX which is 2 bytes */
UARTFIFOLevelSet(HAL_UART_PORT, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
UARTFIFOEnable(HAL_UART_PORT);
/* Clear and enable UART TX, RX, CTS and Recieve Timeout interrupt */
UARTIntClear(HAL_UART_PORT, (UART_INT_RX | UART_INT_TX | UART_INT_CTS | UART_INT_RT ));
UARTIntEnable(HAL_UART_PORT, (UART_INT_RX | UART_INT_TX | UART_INT_CTS | UART_INT_RT ));
if(config->flowControl)
{
/* Enable hardware flow control by enabling CTS and RTS */
HWREG(HAL_UART_PORT + UART_O_CTL) |= (UART_CTL_CTSEN | UART_CTL_RTSEN );
}
UARTEnable(HAL_UART_PORT);
return HAL_UART_SUCCESS;
}