放大器论坛 - 最近的话题

DRV632: DRV632PWR，该物料的类别是

Xiaoqiong HONG — Fri, 30 Oct 2026 01:38:26 GMT

Part Number: DRV632

DRV632PWR

您好，该物料我们需要安排进口报关，目前对该物料的归属类目有点争议，麻烦帮忙确认：该物料功能属于放大功能还是驱动功能？同时提供对应的申报品名、功能描述以及海关 HS 编码，谢谢

OPA2192: OPA2192IDR封装表面外观问题

DARK NIE — Tue, 27 Oct 2026 02:08:11 GMT

Part Number: OPA2192

你好:
请教一下同一个型号，同一卷里的物料有的塑封表面光亮一些，这种正常吗？

TLV9022: BQ25713RSN/INA300AIDSQR/SN74LVC1G74DCTR/TLV9022DGKR/CSD25402Q3A技术支持

huiqing huang — Mon, 26 Oct 2026 07:42:45 GMT

Part Number: TLV9022
Other Parts Discussed in Thread: BQ25713, BQ25713B, INA300, SN74LVC1G74, CSD25402Q3A

一 BQ25713RSNR 充电控制器 U601

当前条件：1S 配置；输入采样电阻 R604=20 mΩ，充电采样电阻 R605=10 mΩ；OTG/VAP 引脚经 10 kΩ 下拉。ILIM_HIZ 的许可路径含 R1254 0 Ω 链路，当前标为 DNP 未装；后级为 7.50 kΩ/100 kΩ 分压及默认下拉，见附图1。拟议初始化方案是在硬件保持禁止时设置 CHRG_INHIBIT（0x00[0]）=1、ChargeCurrent（0x03/02）=0、AUTO_WAKEUP_EN（0x30[0]）=0，完成配置及回读后才允许运行；不把 HIZ 视为电池放电隔离。

1 启动及重新配置边界

请确认电池单独供电、适配器先上电、慢爬升/欠压恢复时，在保持 ILIM_HIZ 为低的条件下，I2C 可可靠访问所需的电源条件及就绪判据。《BQ25713/BQ25713B 充电控制器数据手册》（SLUSD83C，Rev C）第24页描述的 50 ms、150 ms 和重新判定间隔 2 s，是否有适用于上述条件的保证上下界？若没有，请说明建议的外部监督和超时处理方法。另请明确 AUTO_WAKEUP_EN 与 CHRG_INHIBIT、ChargeCurrent=0 的优先关系，以及适配器重新插入或局部复位时可能重新加载的相关设置，避免初始化前出现非预期充电。

2 20 mΩ 输入采样电阻的换算

拟按《BQ25713/BQ25713B 充电控制器数据手册》（SLUSD83C，Rev C）第40页设置 RSNS_RAC，即字节 0x31[3]=1，RSNS_RSR 即 0x31[2]=0。请明确此设置对 IIN_HOST、IIN_DPM、输入电流 ADC、输入过流/PROCHOT 门限及 PSYS 的影响：哪些量自动补偿电阻值，哪些仍需软件按实际 20 mΩ 换算？请给出适用于本料号的公式或算例，包含零代码和量化规则；不沿用 10 mΩ 示例的物理电流值。

3 两处寄存器文档差异

• 《BQ25713/BQ25713B 充电控制器数据手册》（SLUSD83C，Rev C）第25页表9-1给出 1S 的 REG0x05/04 默认值为 4.192 V，而《BQ25713/BQ25713B 充电控制器数据手册》（SLUSD83C，Rev C）第58页 §9.6.4 及寄存器摘要给出 4.200 V。请确认实际 POR、CELL 检测及 RESET_REG 后的值与采样时点。我方最终充电电压设置仍待确认。

• 《BQ25713/BQ25713B 充电控制器数据手册》（SLUSD83C，Rev C）第35页 §9.5.1.8 将 IIN_DPM 列入双字节写命令，但《BQ25713/BQ25713B 充电控制器数据手册》（SLUSD83C，Rev C）第63页 0x25/24 为只读；《BQ25713/BQ25713B 充电控制器数据手册》（SLUSD83C，Rev C）第61–62页实际主机设置为 IIN_HOST 0x0F/0E。请确认应使用的连续 LSB→MSB 事务及低字节处理要求，并提供勘误或正确示例。

二 INA300AIDSQR 电流比较器 U2010 U2011

当前两只均以 IN+=CHG_BAT_PRE_RSR、IN−=CHG_COMMON 监测 R605 的充电方向；VS/ENABLE 接 AON，LATCH/DELAY 接地，ALERT 经上拉进入硬件故障链。我们拟另设放电方向检测通道，不将现有两只误认作双向检测，也不把 ALERT 释放为高等同于监测器已就绪。

4 响应上界与失电输出

依据《INA300 电流检测比较器数据手册》（SBOS613C，Rev C）第5页及第7.3.4、7.4.2节，请提供或明确没有保证的上电、ENABLE 恢复，以及 DELAY=GND 在规定过驱动、温度和电源条件下的最大报警延迟；我们不会把典型响应时间直接用作整条故障能量预算。对于 VS 缓降/局部断电而 ALERT 上拉仍可能存在的情况，ALERT 状态、泄漏及重新有效的边界是否有保证？《INA300 电流检测比较器数据手册》（SBOS613C，Rev C）第28页的失电输入耐受已知，并不等同于故障输出有效。若需外部电源有效门控或自检，请建议实现原则及必须验证的条件。

三 SN74LVC1G74DCTR 异步清零与时钟配合

重点实例为 U1206、U2037：D、nPRE、VCC 均接 AON；nCLR 分别为 LATCH_CLEAR_N、CHG_MAIN_SEEN_CLEAR_N。U1206 时钟由施密特缓冲器输出 ARM_CLOCK_DELAYED 驱动；U2037 时钟由逻辑门推挽输出 MAIN_RAW 驱动，并非直接接慢 RC 节点。

5 请确认电源有效之前的复位覆盖及释放方法

设计须满足《SN74LVC1G74 D 型触发器数据手册》（SCES794G，Rev G）第6–7、9页在相应 VCC/温度/负载条件下的 nCLR 脉宽、释放至 CLK 的建立时间、数据建立/保持及输入边沿要求，不把 Ioff 或异步清零功能外推到未规定的欠压区间。对于 nPRE/D 随 VCC 爬升、nCLR 持续为低的启动，以及运行中 VCC 缓降，是否存在可保证 Q/nQ 状态的额外电压或保持条件？若没有，请明确推荐的复位监督、时钟屏蔽和重新释放顺序，以及审查复位释放靠近 CLK 或电源恢复时所需的引脚波形。违反规定时序后的输出不得视为确定状态。

四 TLV9022DGKR 温度窗口比较器 U1212

当前由 3.3 V AON 供电，两路开漏输出分别经 10 kΩ 上拉至同一电源；NTC_SENSE 和门限来自 1.25 V 参考及分压，参考电容在掉电时可能比 AON 下降慢。输入由现有偏置、暖温分压和 ADC 支路共同加载。

6 Rev H 输出就绪与高阻节点误差边界

《TLV902x 和 TLV903x 精密比较器系列数据手册》（SNOSDA3H，Rev H）第36页修订记录删除了原 POR 特性，但《TLV902x 和 TLV903x 精密比较器系列数据手册》（SNOSDA3H，Rev H）第22页 §6.4.2.2 仍明确输入在 VS=0 或爬升/下降期间的容错条件。请说明当前 TLV9022DGKR 是否仍有可保证的上电/欠压输出状态和就绪时间，或需外部监督与输出门控。《TLV902x 和 TLV903x 精密比较器系列数据手册》（SNOSDA3H，Rev H）第11页 IB、IOS 及《TLV902x 和 TLV903x 精密比较器系列数据手册》（SNOSDA3H，Rev H）第12页响应/上电时间为特定条件下的典型值：请提供或明确没有保证的全温输入偏置/泄漏上界，以及在本板 3.3 V、10 kΩ 上拉、缓变输入、给定最小过驱动和总输出电容下的最大响应时间。若只能提供表征数据，请建议误差预算、迟滞及验证方法。我们不将输入容错解释为输出始终安全，也不直接套用 5 V、2.5 kΩ 上拉的典型延迟。

五 CSD25402Q3A 功率 MOSFET

当前 Q605 为 BQ25713 的 BATFET；Q606/Q607、Q2001/Q2002 各为并联的单方向阻断级。我们已识别其体二极管方向，不将并联器件视为冗余或双向隔离。

7 线性及重复体二极管瞬态的适用数据

针对 Q605 在 BQ 低电压充电阶段可能进入线性区，以及关断过渡中上述器件可能承受的体二极管电流，请说明《CSD25402Q3A P 沟道 MOSFET 数据手册》（SLPS454B，Rev B）第4页热阻曲线、《CSD25402Q3A P 沟道 MOSFET 数据手册》（SLPS454B，Rev B）第6页单脉冲 SOA 如何用于高起始结温和重复脉冲工况；是否有补充的线性区/体二极管限制或推荐验证方法？我们不会直接以典型 RDS(on)、绝对最大电流或单脉冲图作为本板允许值。请列出进行器件适用性确认所需的 VGS/VDS/ID 波形、重复周期、起始温度及 PCB 散热资料。

请按编号回复，并区分数据手册保证值、典型或表征数据及尚未明确的条件。如需补充工况或实测波形，请列明所需字段。

LMH13000: 我需要该器件的评估板的原理图和PCB图工程文件

zhang answer — Fri, 23 Oct 2026 05:51:00 GMT

Part Number: LMH13000

我需要该器件的评估板的原理图和PCB图工程文件

LMH6882: 关于LMH6882增益控制测试不准问题请教

Xianbin Huang — Thu, 22 Oct 2026 06:33:14 GMT

Part Number: LMH6882

您好：

我在使用LMH6882作为VGA增益控制，当前测试6db（2倍）和12db（4倍）下，发现在VGA输入前后的波形幅度峰峰值比值，不等于6db（2倍）和12db（4倍），我核对D0~D7的数字控制是对的。请帮忙分析会是什么问题？如下截图是LMH6882的原理图：

1）在LMH6882 最靠近的输入端，测试的单端波形如下，1M正弦波259.123mvpp；

2）在LMH6882 最靠近的直接输出端。测试波形如下图，差分峰峰值是670mvpp左右；

3）按照测试增益是670/259.123=2.58；

4）测试12db方法一样，VGA输入端单端幅度峰峰值是244.979mvpp，VGA输出差分波形，单端测试分别是659.406，差分波形峰峰值就是1318.812mvpp；按照计算1318.812/244.979=5.38，偏离4倍。

测试有对比断开VGA后级的电路，结果一样。

5）已经确认FPGA设置后，核对D0~D7是对的，分别是规格书说明的，如下图。其他请帮忙分析是啥原因？

SN10501: SN1710047DRCR

ZHAOFA SU — Wed, 21 Oct 2026 11:14:38 GMT

Part Number: SN10501

Subject: Datasheet Request – SN1710047DRCR

Dear Texas Instruments Support Team,

We currently have inventory of the TI part number **SN1710047DRCR**.

We are looking for the original datasheet and technical documentation for this exact part number.

Could you please help us confirm:

1. Whether SN1710047DRCR is an official TI part number.
2. Whether the original datasheet is available, including any non-public documentation that can be shared.
3. The product function, package, pin configuration, and electrical specifications.
4. Whether this device is a production part, engineering prototype, or custom device.

Thank you for your assistance.

Best regards,

Shenzhen Tehaowei Semiconductor Co., Ltd.

suzhaofa2576@gmail.com

TL061: TL061ID芯片发烫

david chu — Wed, 21 Oct 2026 01:40:05 GMT

Part Number: TL061

我们有个显示屏，在测试时出现了1PCS TL061ID 这个IC 发烫的异常。更换一个IC后，模组功能正常。

想了解下，出现TL061ID功能异常，是什么原因？与电路的搭配是否相关？

如下是我司与这个IC相关的电路。

LMH13000: LMH13000相关问题

mingLiang — Tue, 20 Oct 2026 09:44:16 GMT

Part Number: LMH13000
Other Parts Discussed in Thread: TINA-TI

工程师您好:

打算使用LMH13000这颗芯片，但是有几个问题想要确认一下.

第一，Vset引脚处的调制带宽是从这里看吗？也就是约f-3dB带宽为600K。VSET处正弦波频率600K的时候，IOUT电流衰减到了0.707倍？

第二，恒定电流ICC为0的时候，我在TINA-TI上仿真会有问题。必须有一个ICC（比如4mA）才行。请问实际使用的时候是这样吗？

第三，有一篇用LMH13000搭建LD恒功率的电路，请问功率稳定性如何呢？

第四，EP/EN LVDS驱动问题。我看了论坛里面一篇帖子里提到，

1、如果是TTL驱动，那么不需要TTL转LVDS转换芯片，直接TTL驱动导EP，EN设置到1.65V即可。这样高电平为1.65V，低电平为-1.65V；

2、电阻分压器连接到EN引脚设置1.65V即可，因为它是高阻输入。请问这么理解对吗？

——非常感谢！！！

AMC1300B-Q1: AMC1300&AMC1300B&AMC1400&AMC0300D&AMC0300R: Failure criteria for CMTI

Levi Zhu — Tue, 20 Oct 2026 08:02:10 GMT

Part Number: AMC1300B-Q1
Other Parts Discussed in Thread: AMC0300D

Following up on CS3523717.
Sorry, I can’t see the example on the left, and there don’t seem to be any attached files, so I’m having trouble understanding the chip’s performance. Could you please resend it?

Also, does what you said mean that the same CMTI evaluation criteria apply to different isolated amplifier models, as long as they all have differential outputs?

There’s also another version of the model you mentioned, the AMC0300D. I checked its datasheet, and it has an adjustable gain and a single-ended output. Could you explain a bit about this version as well?

Are the CMTI evaluation criteria the same for single-ended and differential outputs?

JFE2140: JFE2140 – Request for Definitive Suitability Assessment: Forward-Biased Gate PN Junctions in a 100 pA to 12 µA Logarithmic Current Amplifier

haha li — Sun, 18 Oct 2026 14:58:28 GMT

Part Number: JFE2140
Other Parts Discussed in Thread: LMC6082

JFE2140 – Request for Definitive Suitability Assessment: Forward-Biased Gate PN Junctions in a 100 pA to 12 µA Logarithmic Current Amplifier

Hello TI Applications Engineering Team,

I am designing a precision logarithmic current detection circuit using the JFE2140 matched dual N-channel JFET and the LMC6082 dual CMOS operational amplifier.

Before finalizing the circuit, I need to determine whether the JFE2140 can safely and reliably operate as a pair of forward-biased gate PN-junction logarithmic feedback elements, rather than as conventional JFET amplifiers.

I have reviewed the JFE2140 datasheet (SLPS730, Revision B), but several critical aspects of this unconventional application are not specified.

I would appreciate a detailed technical assessment. In particular, I need to know whether the device is suitable for continuous use, and whether its forward-junction behavior is sufficiently characterized for precision low-current measurement.

1. Circuit Configuration

My circuit uses the JFE2140 as follows:

Reference channel (JFET 1):

G1 (pin 4) is connected to the inverting input of LMC6082 channel 1.
D1 (pin 2) and S1 (pin 1) are shorted together and connected to the op-amp output.
The non-inverting input is connected to analog ground.
A 2.5 V precision reference and a total resistance of 2.5 MΩ provide approximately 1 µA to the inverting-input node.

Measurement channel (JFET 2):

G2 (pin 8) is connected to the inverting input of LMC6082 channel 2.
D2 (pin 6) and S2 (pin 5) are shorted together and connected to the second op-amp output.
The non-inverting input is connected to analog ground.
The input current is intended to range from 100 pA to 12 µA.

Other conditions:

LMC6082 supply: +5 V / −5 V.
JFE2140 VCH (pin 3) and VCL (pin 7) are left floating.
Each logarithmic feedback branch has a 100 pF capacitor in parallel.
Both channels operate with the gate junction forward-biased during normal operation.
Because D and S are shorted, VDS is approximately 0 V.
The two op-amp outputs are subtracted to obtain a logarithmic response proportional to the ratio between measurement current and reference current.

The intended use is continuous DC and low-frequency microcurrent measurement, not a short-duration transient or ESD protection function.

A schematic screenshot of the relevant front-end circuit is attached.

2. Absolute Maximum Ratings and Continuous Forward Conduction

Section 6.1 of the JFE2140 datasheet specifies:

Gate-to-source and gate-to-drain voltage: −40 V to +0.1 V.
Gate-to-source and gate-to-drain current: −20 mA to +20 mA.

Section 6.3 specifies a recommended gate-to-source voltage range of −1.2 V to 0 V.

Q1. Does the +0.1 V absolute maximum for VGS and VGD apply without exception when the drain and source are shorted and the gate PN junction is deliberately operated in forward conduction?

Q2. If the forward gate current is strictly limited to 12 µA or less during steady-state operation, is continuous positive VGS/VGD exceeding +0.1 V permitted? Please provide a clear YES or NO, rather than only referring to the current rating.

Q3. The datasheet separately specifies a ±20 mA gate-current absolute maximum. What operating or stress conditions is this current rating intended to cover? Is there any current-limited forward-conduction exception to the +0.1 V voltage rating?

Q4. If a typical forward-junction voltage of approximately +0.3 V to +0.6 V were required at these microampere currents, would this be considered an absolute-maximum-rating violation and an unacceptable continuous operating condition? These voltage values are hypothetical, not measured values for the JFE2140.

Q5. Is there any known risk of long-term degradation, leakage-current increase, matching drift, or permanent damage from continuous forward gate current in the 100 pA to 12 µA range, even when the resulting junction power dissipation is very low?

Q6. Is the configuration with each drain shorted to its corresponding source electrically and structurally acceptable? Could this cause any undesired internal current paths or interactions with the integrated protection diodes?

3. Forward Gate-Junction Characteristics

For the logarithmic conversion to work accurately, I need the relationship between forward gate current and junction voltage.

Q7. Does TI have any measured or simulated forward gate-junction I–V curves for JFE2140, particularly over 100 pA, 1 nA, 10 nA, 100 nA, 1 µA, and 12 µA, with D and S shorted?

If available, could you provide the typical VGS/VGD values, voltage ranges, or measurement data at these current levels?

Q8. Is the forward gate-junction characteristic sufficiently close to the standard diode exponential equation over this current range?

If characterized, could TI provide the ideality factor (n), saturation-current parameter (IS), and their variation with current and temperature?

Q9. At very low forward current, especially around 100 pA, are there additional leakage, recombination, parasitic-device, or nonideal effects that would make the gate-junction current-voltage relationship unsuitable for precision logarithmic conversion?

4. Matching Between the Two JFET Gate Junctions

The two junction voltages are subtracted in my circuit. Therefore, their forward characteristics must track each other closely.

The datasheet specifies a differential VGS mismatch of up to approximately 4 mV under conventional JFET bias conditions, including IDS = 2 mA.

Q10. Does the published VGS matching specification have any relevance to the matching of the two forward-biased gate PN junctions when VDS = 0 V?

Q11. Has TI characterized the forward-junction voltage difference between channel 1 and channel 2 at the same gate current, especially between 100 pA and 12 µA?

If available, please provide typical and maximum forward-voltage mismatch, or the distribution across devices and production lots.

Q12. Are the forward-junction ideality factors and logarithmic slopes matched between the two internal JFETs, or is the matching specification limited to conventional drain-source operation?

Q13. Can the two gate junctions be reasonably expected to track one another over temperature in this configuration? Is any forward-junction mismatch drift or logarithmic-slope drift data available?

My application requires reproducible readings over the full input-current range. I understand that calibration may be necessary, but I need to distinguish errors that can be calibrated from unpredictable device-to-device or temperature-dependent behavior.

5. Noise, Leakage, and Stability at 100 pA

Q14. Are the JFE2140's published low gate-current and noise specifications applicable when the gate PN junction is deliberately forward-biased and carrying picoampere-to-microampere current?

If not, does TI have any relevant noise, leakage, or stability characterization in this mode?

Q15. Could the integrated protection-diode structures connected to VCH and VCL affect the forward gate-junction current, leakage, matching, or long-term stability when these pins are floating?

6. SPICE Model Validity

TI provides a PSpice model for the JFE2140/JFEx140 family.

Q16. Does the official SPICE model accurately support the following operating conditions?

Positive gate-to-source and gate-to-drain voltage.
Forward gate current from 100 pA to 12 µA.
Shorted drain and source.
Operation down to 100 pA with realistic gate leakage and nonideal behavior.

Q17. Does the model represent the matching errors, forward-junction ideality factors, temperature dependence, and device-to-device variation between the two internal JFETs?

If not, which simulated results should not be relied upon when evaluating this application?

7. Final Device Suitability Decision

These are the most important questions for my design decision.

Q18. Based on the internal device structure, absolute maximum ratings, and available reliability characterization, does TI officially consider the JFE2140 suitable for continuous use as a pair of forward-biased PN-junction logarithmic feedback elements over 100 pA to 12 µA?

Please explicitly state one of the following:

YES — This application is permitted under specified conditions.
NO — This application violates device ratings or is unsuitable.
NOT CHARACTERIZED / NOT SUPPORTED — TI cannot guarantee this application, even if the device may function experimentally.

Q19. If the answer is YES, what precise voltage, current, temperature, startup/transient, or other operating limits must be followed to keep this design within the device's guaranteed operating conditions?

Q20. If the application is not permitted or not supported, could TI recommend a specific matched dual JFET, matched PN-junction device, or other semiconductor component with documented continuous forward-junction operation that would be more appropriate for this logarithmic current-measurement circuit?

If the requested forward-junction characterization data is unavailable, please state that explicitly rather than assuming the published conventional JFET parameters apply.

I am trying to make a clear engineering decision before PCB fabrication, and your answers will determine whether I retain or replace the JFE2140.

Thank you very much for your technical assistance.

Best regards.

LOG114: LOG114参数升级

user4645094 — Thu, 15 Oct 2026 08:59:05 GMT

Part Number: LOG114

log114规格书新.pdf log114旧版.pdf

Dears,

请帮忙看下log114参数是否有更改，客户在新的一个批次产品贴片测试时发现了电源轨异常，经过对比发现老板手册和新版手册有更改，请帮忙确认下，多谢！

LMH6629SDEVAL: LMH6629SD/NOPB 3D有问题

Xiumin Zhou — Thu, 15 Oct 2026 02:29:06 GMT

Part Number: LMH6629SDEVAL

LMH6629SD/NOPB，此料在官网上下载3D模型，STEP格式，有问题，请帮忙确认并提供最新版本，谢谢

TAS5805M: TAS5805M EQ调整问题

Vincent Suen — Tue, 13 Oct 2026 05:02:03 GMT

Part Number: TAS5805M

您好, 我遇到了一个问题, 就是我在计算机的PPC3软件, 调整了EQ 以及 DRC后, 在计算机软件生成了.H 档案, 然后, 我把这个.H档案内的参数经由我主板的主控芯片去发送,

会发现跟计算机调整的声音, 会有些微不同

但我在计算机, 以及自己主控初始化时 (即没有EQ调整), 出来的声音是一样的, 理论上这个初始化, EQ应该是平的(Flat).

即EQ参数有在生效后, 声音才会有所差异. (计算机跟主控发送EQ参数是有变化的, 只是主控发送后, 声音跟我在计算机调整的, 有些微不同)

想问一下, 应该从那个方向解决?

OPA544: 正弦电流输入方案（器件）咨询

cooper kuo — Mon, 12 Oct 2026 07:52:09 GMT

Part Number: OPA544
Other Parts Discussed in Thread: OPA561, OPA551

你好，TI是否有输出正弦电流的方案或器件，输出正弦电流最大值约200mA, 频率约1MHZ ;

感谢

TLC2272-Q1: What's the difference between TLC2272QPWRQ1 and TLC2272AQPWRQ1

bxh hdh — Sun, 11 Oct 2026 08:51:51 GMT

Part Number: TLC2272-Q1
Other Parts Discussed in Thread: TLC2272A-Q1

Hello

What's the difference between TLC2272QPWRQ1 and TLC2272AQPWRQ1

A means

OPA569: OPA569运放输出到电源轨后恢复出现滞回

user6350480 — Sat, 10 Oct 2026 09:58:48 GMT

Part Number: OPA569
Other Parts Discussed in Thread: TINA-TI,

您好，

我在设计TEC驱动电路，使用如上电路，VIN在1V降至0.3V过程中，输出正常，到达0.3V，此时U1输出3.8V，U2输出0.3V，而在回到0.4V，U1,U2输出值不变，直到VIN从0.3V上升到0.7V后，U1,U2输出才会改变。而在1V升至1.7V时，U2输出3.8V，U1输出0.3V，在1.7V降至1.6V，U1,U2输出随之改变。检测过流标志引脚和热保护标志引脚，都是正常状态，未触发。

请问这是什么原因触发以及该如何在硬件上解决

TAS6684-Q1: TAS6684E-Q1静态电流

gebing Duan — Wed, 07 Oct 2026 05:49:16 GMT

Part Number: TAS6684-Q1
Other Parts Discussed in Thread: TAS6684Q1EVM

设计为汽车功放，测试步骤如下

1.板上所有PA芯片不初始化，PVDD&STBY供电，读取电源表显电流（除PA外其余芯片正常工作的电流）为0.09A
2.TAS6684E-Q1正常输出，其余芯片仍不初始化。读取电源表显电流，为TAS6684E-Q1的静态电流，多次测试读取值为 0.441-0.446A左右。

根据实际设计,

Test conditions (unless otherwise noted): Tc= 25°C, PVDD = 35 V, VBAT = 14.4 V, DVDD = 3.3 V,R,= 4Ω, L= 10 uH, Fsw= 480 kHz, Hybrid Mode, 200 kHz bandwidth, BTL, AES17 Filter
读取规格书中该PA芯片静态电流值为，I_DVDD+I_PVDD+I_VBAT=40+80+32=162mA

数据来源，EXCEL 5.5 Electrical Characteristics、Figure 5-45 PVDD IDLE Current vs Voltage

实测静态电流值与规格书中参数相差过大。

LM393: 请问LM393可以支持±12V的电源电压吗？

Abner Ma — Wed, 30 Sep 2026 09:16:39 GMT

Part Number: LM393

工程师你好，

我们最近有一个需求是：

MCU输出0-3.3V、占空比为50%的PWM信号（频率为100HZ），现在想将这个信号转换成±12V的PWM信号。我们计划将这个PWM输入到比较器的正，比较器的负输入一个1.65V的稳定电压（3.3V的一半），然后比较器的电源是±12V，希望输出±12V的PWM波。

1.请问这样使用比较器可以吗？

2.有没有合适的比较器推荐？LM393可以吗？

感谢。

TPA3112D1: Speaker AMP TPA3112D1

Joyce Wu — Tue, 29 Sep 2026 06:48:39 GMT

Part Number: TPA3112D1

Our new product uses the TPA3112D1 IC, and the circuit design is shown in the diagram below.

After trial production of 10 boards, we found short circuits in components at positions

TS11 and TS12 on every board.

What could be causing this?

Please also help us confirm whether the circuit design is appropriate. Thank you.

OPA690: 用OPA690搭的电压跟随器存在明显震荡现象，请问是PCB哪里设计的有问题

HaoXuan huang — Sat, 26 Sep 2026 04:37:31 GMT

Part Number: OPA690

根据数据手册推荐，挖空了反馈引脚的铜皮，同时加了几个隔离电阻，但是实际使用时发现仍然存在自激振荡现象，在无信号输入情况下依然存在1Vpp以上的正弦输出信号，以下是我的旧版PCB

我怀疑是铜皮与走线的间隔不够导致，所以提升了走线与铜皮的间距，以下是新版的PCB：

请问以上设计中是否存在问题

BUF802RGTEVM: 如何在BUF802前端加入多个衰减电路，同时保证带内平坦度和1M的输入阻抗呢？

chunyu Lang — Thu, 24 Sep 2026 07:36:15 GMT

Part Number: BUF802RGTEVM
Other Parts Discussed in Thread: BUF802

如何在BUF802前端加入多个衰减电路，同时保证带内平坦度和1M的输入阻抗呢？

LMC6482: LMC6482IMX/NOPB 产品为什么不同批次之间外观及性能上存在差异

Dieya Lu — Wed, 23 Sep 2026 02:35:45 GMT

Part Number: LMC6482

不同批次之间产品外观存在差异。Marking为543Y LMC6482IM 的产品本体上的标记点为一个大圆点，而Marking 为64RJ LMC6482IM 的产品本体上的标记点为两个小圆圈。如下图
测量Pin2 和Pin3 之间阻值， Marking 543Y 产品Pin 2 和Pin3 之间阻值为0.7MΩ左右，Marking 为64RJ的产品Pin2 和Pin3 之间阻值为20MΩ左右。

TLV6002-Q1: TLV6002QDRQ1 售后质保期

Shengle Lv — Wed, 23 Sep 2026 00:43:23 GMT

Part Number: TLV6002-Q1

烦请确认TLV6002QDRQ1 售后质保期

TLV6002-Q1: TLV6002QDRQ1 售后质保期

Shengle Lv — Wed, 23 Sep 2026 00:20:41 GMT

Part Number: TLV6002-Q1

烦请确认TLV6002QDRQ1 售后质保期

INA333: INA333采集电阻性桥式传感器力信号

user1993031 — Tue, 22 Sep 2026 09:50:45 GMT

Part Number: INA333

在采用INA333放大桥式力传感器信号时，触摸传感器外壳，上传采集数据跳变；

电路结构为：采用隔离DCDC给采集板供电，INA333采集传感器信号放大，进单片机AD口模数转换，再通过隔离RS485总线上报；传感器与采集板密封在同一个金属盒中，都与金属盒电气绝缘；测试过程中，用手触摸金属盒，上报值跳变（传感器外部受力为0）

更换设计后，同样工况没有出线这个问题；

我的疑惑在于INA333的内部结构中有 RFI Filter,替换的型号中没这个功能。可否讲下内部的 RFI Filter是干什么的？是否会在输出转换为直流电压？