其他DSP文档

2014 TI 处理器研讨会资料

deyisupport — Wed, 27 Aug 2014 02:02:05 GMT

TMS320C6000 EABI 迁移指南

user 21ic — Mon, 16 Jun 2014 01:41:05 GMT

The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI.

KeyStone 的DDR3设计要求

user 21ic — Mon, 16 Jun 2014 01:40:19 GMT

This document provides implementation instructions for the DDR3 interface incorporated in the Texas Instruments (TI) Keystone series of DSP devices. It supports 1333 MT/s and higher memory speeds in a variety of topologies (see to the Data Manual for supported speeds). This document assumes the user has a familiarization with DRAM implementation concepts and constraints. When searching for a particular configuration see the appendix, which will alleviate the need for searching the entire document which contains all possible variations.

调整VCP2和TCP2位错误率

user 21ic — Mon, 16 Jun 2014 01:38:37 GMT

This application note presents the strategies and programming methodology to optimize VCP2 and TCP2 BER performance on TI DSPs. It is assumed the reader is familiar with Convolutional and Turbo coding theory.

TMS320C66x DSP系列

user 21ic — Thu, 12 Jun 2014 02:25:11 GMT

Based on TI’s innovative KeyStone architecture, the new TMS320C66x DSP core and generation of C66x multicore devices include the industry’s first 10-GHz DSP with 320 GMACs and 160 GFLOPs of combined fixed- and floating-point performance on a single device. These devices are designed to maximize the throughput of on-chip data flows and eliminate the possibility of bottlenecks. This enables developers to fully utilize the vast processing power of the DSP cores to design applications in markets such as test and measurement, mission critical, industrial automation, medical and high-end imaging equipment, and high-performance computing.

KeyStone 的PCIe 应用案例

user 21ic — Thu, 12 Jun 2014 02:24:00 GMT

This document gives examples of PCIe usage in KeyStone devices including address translation, multi-device connection, and programming examples. It also contains detailed descriptions of PCIe features that supplement the information in the PCIe user's guide. See the KeyStone Architecture PCI Express User's Guide (SPRUGS6) for information about the PCIe registers and functions.

C66x KeyStone 吞吐量性能指南

user 21ic — Fri, 30 May 2014 03:57:59 GMT

This document analyzes various performance measurements of the KeyStone Architecture C66x device. It provides a throughput analysis of the various DSP support peripherals as well as EDMA transfer times to different end-points and memory access.

多核编程指南

user 21ic — Fri, 30 May 2014 03:57:04 GMT

As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore devices.We also describe the features of Texas Instruments DSPs that enable efficient implementation, execution, synchronization, and analysis of multicore applications.

Keystone DDR3初始化

user 21ic — Fri, 30 May 2014 03:55:41 GMT

The initialization of the DDR3 DRAM controller on KeyStone DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.

KeyStone I串行器/解串器实施指南

user 21ic — Fri, 30 May 2014 02:14:22 GMT

This document is intended to aid in the hardware design and implementation of a KeyStone I-based system. The document should be used along with the device-specific data manual and relevant user guides, application reports, standards, and specifications

KeyStone I硬件设计指南

user 21ic — Fri, 30 May 2014 02:12:36 GMT

This document describes hardware system design considerations for the KeyStone I family of processors. This design guide is intended to be used as an aid during the development of application hardware. Other aids including, but not limited to, device data manuals and explicit collateral should also be used.

HyperLink 编程和性能考量

user 21ic — Fri, 30 May 2014 02:11:37 GMT

HyperLink 为两个 KeyStone 架构 DSP 之间提供了一种高速，低延迟，引脚数量少的通信接口。HyperLink 的用户手册已经详细的对其进行了描述。本文主要是为 HyperLink 的编程提供了一些额外的补充信息。同时本文还讨论了 HyperLink 的性能，提供了在各种操作条件下的性能测试数据。对影响 HyperLink 性能的一些参数进行了讨论。

OpenEM简介和基于OpenEM的大矩阵乘实现

user 21ic — Thu, 29 May 2014 08:02:09 GMT

OpenEM 的全称是Open Event Machine。是TI 针对嵌入式应用开发的multicore runtime system library 。OpenEM 可以在多核上有效的调度，分发任务。它把任务调度给负载轻的核，进而实现动态的负载平衡。OpenEM 是基于TI Keystone 系列芯片的multicore Navigator 构建的，具有开销小，效率高的特点。本文首先对OpenEM 的原理做了简单的介绍。然后结合一个大矩阵乘的演示用例详细介绍了OpenEM 的使用。最后通过量化分析这个演示用例的执行cycle 数，总结了OpenEM 的效率和局限。希望本文能成为学习OpenEM 的读者的一个有用的参考。

TMS320C6678 存储器访问性能

user 21ic — Thu, 29 May 2014 08:00:32 GMT

TMS320C6678 有8 个 C66x 核，典型速度是1GHz，每个核有 32KB L1D SRAM，32KB L1P SRAM 和 512KB LL2 SRAM ；所有 DSP 核共享 4MB SL2 SRAM 。一个 64-bit 1333MTS DDR3 SDRAM 接口可以支持8GB 外部扩展存储器。

TMS320C6670 多核定点和浮点的片上系统

user 21ic — Thu, 29 May 2014 07:53:47 GMT

The TMS320C6670 Communications Infrastructure KeyStone SoC is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance wireless infrastructure applications. The C6670 provides a very high performance macro basestation platform for developing all wireless standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX. Even with aggregate data rates for 20-MHz LTE systems above 400 Mbps per sector, the C6670 can support two sectors running at full rate. The C6670 also sets a new standard for clock speed with operating frequencies up to 1.2 GHz.