This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How to design a PLL clock circuit that can receive a WordClock input and output BCLK

Other Parts Discussed in Thread: SRC4192EVM, LMK61E2, SRC4192, CDCM7005

I am designing an audio circuit, the circuit needs to synchronize the external clock, the clock is a professional audio commonly used WordClock (sampling rate is typically 44.1kHz to 192kHz TTL).
For example, WC48kHz, multiplier 256 times to 12.288MHz
What chip or circuit should I choose?

https://noisegate.com.au/word-clock/