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TLV320AIC3007: 如何配置寄存器才能MIC输入经ADC和数字滤波后直通DAC然后输出到耳机?

Part Number: TLV320AIC3007

我们想将从MIC输入采集的声音经过AIC3007数字滤波和EQ后得到20Hz~1000Hz之间的音频数据,MCU不采集数字音频信号,数字信号滤波后直接经DAC到耳机输出。在芯片参考手册上Page0 / Register 107的D3位可以将ADC数字转出到滤波器部分,但是要求在关闭DAC,这样就不能实现我们想要的功能。请问还有别的方式实现ADC到DAC的路径吗吗?如果有,麻烦给一下寄存器配置示例。

  • 您好,

    我稍后看下您的问题,给您带来不便很抱歉

  • 在这里数字滤波器您是什么功能?看寄存器 Page0 / Register 107的D3=0的话,只能使用HPF

    使用DAC播放音频的话,数字音频的处理可以看 datasheet 中 31页 DIGITAL AUDIO PROCESSING FOR PLAYBACK部分的功能。

  • 我们想用到的功能是在Figure 24. Record Only Mode With Digital Processing Path Enabled中,SW_D1闭合、SW_D2状态不重要、DAC Powered Up,然后通过HPOUT能在耳机中听到Analog Input的声音,请问这能否实现?

    我试过如下配置,但是没能从耳机中听到声音输出,请看一下是否有哪里设置的不正确:

    MIC3L is connected to the left ADC PGA :  R17 = 0x0F

    MIC3R is connected to the right ADC PGA :  R18 = 0xF0

    The left ADC PGA is not muted and left ADC PGA Gain 0dB: R15 = 0x00;

    The rigth ADC PGA is not muted and right ADC PGA Gain 0dB: R16 = 0x00;

    Left AGC is disabled: R26 = 0x00

    Right AGC is disabled: R29 = 0x00

    Left ADC channel is powered up: R19 = 0x7C

    Rigth ADC channel is powered up: R22 = 0x7C

    DC dither disabled:  R76 = 0x00

    Left and right ADC highpass filters disabled, left and right DAC digital effects filters disabled (bypassed), left and right DAC de-emphasis filters disabled (bypassed): R12 = 0x00

    The Programmable Filter is connected to ADC output, if both DACs are powered down:  R107 = 0x08

    The left DAC channel is not muted and gain is 0dB: R43 = 0x00

    The right DAC channel is not muted and right is 0dB: R44 = 0x00

    Left DAC is powered up, rightDAC is powered up : R37 = 0xD0

    DAC Output Switching Control(Left DAC output selects DAC_L1 path, Right DAC output selects DAC_R1 path): R41 = 0x00

    DAC_L1 is routed to HPLOUT and volume 0: R47=0x80

    DAC_R1 is routed to HPROUT and volume 0: R64=0x80

    HPLOUT is not muted and output level control = 0 dB: R51 = 0x0F

    HPROUT is not muted and output level control = 0 dB: R65 = 0x0F

  • 可以实现,但是Effects那个block 在 Record-Only路径和 Playback 路径可以实现的功能是不一样的,虽然它们共用相同的配置寄存器地址。

    将 R107 D3 配置0输出现象是怎样的?

  • 我输入的是正弦波,将 R107 D3 配置0与配置为1,在耳机输出端都没有检测到波形。你说可以实现,那么能详细地说一下寄存器的配置吗?

  • 很抱歉,我这边没有EVM没办法生成相应的配置。

    上述寄存器配置没看出异常,您可以附上全部的寄存器配置吗?以查看下ADC和DAC的采样频率信号是否正常配置

    您可以做如下配置吗?即旁路掉ADC和DAC,直接PGA输出到驱动端,以查看是否有输出?

  • 旁路掉ADC和DAC,直接PGA输出到驱动端是有输出的,这个之前我们已经多次验证过了。

    我的全部寄存器配置如下(用I2C接口从3007里读出来的):

    0-3:00 00 00 81
    4-7:1c 52 40 8a
    8-11:e0 07 00 01
    12-15:00 00 00 00
    16-19:00 0f f0 7c
    20-23:78 78 7c 78
    24-27:78 02 00 fe
    28-31:00 00 fe 00
    32-35:00 00 00 00
    36-39:cc d0 00 00
    40-43:00 00 00 00
    44-47:00 2f 2f 80
    48-51:2f 2f 2f 9f
    52-55:2f 2f 2f 2f
    56-59:2f 2f 07 2f
    60-63:2f 2f 2f 2f
    64-67:80 9f 00 00
    68-71:00 00 00 00
    72-75:06 00 00 00
    76-79:00 00 00 00
    80-83:00 00 00 00
    84-87:00 00 00 00
    88-91:00 00 00 00
    92-95:00 00 c6 0c
    96-99:00 00 00 00
    100-103:00 00 02 00
    104-107:00 00 00 00
    p1 0-3:01 7e b6 81
    p1 4-7:4a 7e b6 02
    p1 8-11:27 02 27 02
    p1 12-15:27 7e b4 82
    p1 16-19:8f 66 76 aa
    p1 20-23:75 3a f3 f4
    p1 24-27:c3 50 4b 7e
    p1 28-31:b6 81 4a 7e
    p1 32-35:b6 02 27 02
    p1 36-39:27 02 27 7e
    p1 40-43:b4 82 8f 66
    p1 48-51:f3 f4 c3 50
    p1 52-55:4b 7f ff 00
    p1 56-59:00 00 00 00
    p1 60-63:00 00 00 00
    p1 64-67:00 77 78 88
    p1 68-71:88 6e f2 77
    p1 72-75:78 88 88 6e
    p1 76-79:f2 00 00 00

  • 好的,感谢您的反馈,我需要花些时间细看下您的寄存器配置