ADC32RF42EVM: ADC32RFXX EVM GUI

补充：

Can the AD terminal enter the test mode and send K codes in this configuration mode？

Register 038= 0x0001_0000

Register 03C= 0x0000_0000

Register 004= 0x0001_0000

 I check with the following method：

1. I checked the configurations of AD and FPGA
2. I checked the clock
3. I checked the three reset signals and the QPLL LOCK signal
4. Constraints are checked

No problem. I was really confused for a long time. I would appreciate it if you could give me some advice

I have posted your question to the English E2E forum and our senior engineer would reply you as soon as possible, you could refer to it directly and any other questions, you could follow it here.

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1114243/adc32rf42evm-adc32rfxx-evm-gui

Hello， as to your questions , I need to confirm with you some detailed information.

• Can you resend the images that were posted to the E2E thread? I cannot read anything in these images because the quality is low.
• What is the input clock level? 
• Are you trying to use subclass 1 mode?
• What is the JESD K value?
• The issue is you are  unable to get into CGS, is the SYNC request working? Are there any /K28.5/ characters in the ILA?
• Are there any modifications at all to the configuration file for the ADC?

1.This is my clock configuration screen

2.My chip only supports subclass 1 mode, which seems to be the default

3.JESD and AD both have K values of 16

4.SYNC kept the level low and GTX did not receive K code from AD

5.AD I used the example configuration file, the first time without any changes. The second time I changed to test mode, but the result was the same

Thank you very much for your reply. I still don't know what the problem is. The AD register cannot be checked

您好，抱歉图片打开后， 波形还是看不清，建议放大后再截图附上呢。 

Can you see it this way?

I have another question about the configuration order of ADC. In the ADC manual, AD configuration is divided into 8 steps, but the configuration file of ADCEVMGUI is a whole, does it contain its sequence requirements?

LMK04828
0x13A 0x04 // set SYSREF to 1024
0x13B 0x00
0x10F 0x16 // Enable SYSREF, LVDS
0x10E 0xF0 // Enable SYSREF
ADC32RFxx_LOWLEVEL
0x0000 0x81 // software reset
0x0012 0x04 // write 4 to address 12 page select
0x0000 0x81 // software reset
0x0012 0x00
0x0011 0xFF // write to address 0x0011 ADC page select
0x0022 0xC0 // Stg1 incm
0x0032 0x80 // Dither clk mux : 1 : FLOP CLK
0x0033 0x08 // DAC Prog_vreg_1p5[2:0] : 4 :
0x0042 0x03
0x0043 0x03 // Prog_out_diff_reg1/reg_new : 3 : 1.231
0x0045 0x58 // Clk settings
0x0046 0xC4 // Clk settings
0x0047 0x01 // Clk settings
0x0053 0x01 // Dither_clk_mux : 1 : DITHER_CLK_NEW
0x0054 0x08 // Prog_ftrim_1/2x_hirange
0x0064 0x05 // Adither_msb_force[1:0] : 2 : force 0
0x0072 0x84 // Offset_interleaving_sample_change : Asserted
0x008C 0x80 // Prog_trim_cdac_force : Asserted
0x0097 0x80 // Prog_trim_fdac_force : Asserted
0x00F0 0x38 // Fuse enable
0x00F1 0xBF //
0x0011 0xCC // --v Power down of unused cores and all cores of channel B
0x0020 0x10
0x0020 0x50
0x0020 0xD0
0x0031 0x20
0x0031 0x60
0x0031 0xE0
0x0043 0x83
0x0062 0x80
0x0063 0x01
0x004D 0x01
0x0011 0x00 // Set 0x0011 with 0x00 to enable only master page later
0x0011 0x00 // Set 0x0011 with 0x00 to enable only master page later
0x0012 0x04 // write 4 to address 12 page select
ADC32RFxx_ANALOG
0x0058 0x20 // SYNC polarity inverted as the hsdcpro.ini inverts the sync
ADC32RFxx_LOWLEVEL
0x0025 0x01 //CHB Sha settings ( Vref_1p6_profg[2:0] : 4 : -100m Incm_prog[2:0] : 4 : +80m
0x0026 0x40
0x0027 0x80
0x0029 0x40
0x002A 0x80
0x002C 0x40
0x002D 0x80
0x002F 0x40
0x0034 0x01 // CHB CAP NL DISABLE
0x003F 0x01 // CHA CAP NL DISABLE
0x0039 0x50 // //Iref_50u_inbuf_trim_reg[2:0] : 0x5
0x003B 0x2C //0xEC(Non Fuse 0x2C(Fuse
0x0040 0x80 ////CHA Sha settings ( Vref_1p6_profg[2:0] : 4 : -100m Incm_prog[2:0] : 4 : +80m
0x0042 0x40
0x0043 0x80
0x0045 0x40
0x0046 0x80
0x0048 0x40
0x0049 0x80
0x004B 0x40
0x0053 0x60 // Clk buf Prog_outcm[1:0] : 2 : -50m Prog_n_incm[1:0] : 1 : -60m
0x0059 0x02 // No clock disable
0x005B 0x08 // Sp reg Outcm_prog[2:0] : 4 : -100m
0x0062 0xE0 // Sha current -60u
0x0065 0x81 // Incm -> m200m
0x006B 0x04 //
0x006C 0x08 // CSET disable
0x006E 0x80 // Iref_10u_comp_trim : 2 : 20u
0x006F 0xC0 // Intr_coarse_ref_trim : 3 : 60u
0x0070 0xC0 // CSET disable
0x0071 0x03 // CSET disable
0x0076 0xA0 // Prog_stg1_idac_large : 1 : 880u
0x0077 0x0A // Prog_stg1_idac_large : 1 : 880u
0x007D 0x40 // Clamp dis and Prog_sha_load_cap[1:0] : 1 : 0f 0x41
0x0081 0x1F // In_clk_delay_prog[2:0] : 7 : 240f
0x0084 0x55 // Prog_stg1_idac_large : 1 : 880u
0x008E 0x1F // In_clk_delay_prog[2:0] : 7 : 240f
0x005c 0x07 // No fuse blown val = 0x00 //Refsys fuse en =0x07 - NEW PG
0x0012 0x00 //master select 0x00
0x0011 0xFF
0x0083 0x07 // flash convergence
0x005C 0x00 // flash convergence
0x005C 0x01 // flash convergence
0x0011 0x00
0x4001 0x00 //--v IL corr_regs "Mode" made 2 for stream arrangement
0x4002 0x00
0x4003 0x01
0x4004 0x61
0x6000 0x02
0x4003 0x00
0x6000 0x02
ADC32RFxx_MAIN_DIG
0x680100A2 0x08 //Progam nyquist zone 1 for chB, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A
0x680000A2 0x08 //Progam nyquist zone 1 for chA, nyquist zone = 1 : 0x08, nyquist zone = 2 : 0x09, nyquist zone = 3 : 0x0A
ADC32RFxx_LOWLEVEL
0x4001 0x00
0x4002 0x00
0x4003 0x01
0x4004 0x68
0x604a 0x02 //--v sets mode to ILby2 streams 2 (0 and 180 3(90 and 270
0x6042 0x04 //validity
0x6068 0x40 //analog delay correction enable
0x6044 0x20 //validity
0x4003 0x00
0x604a 0x02
0x6042 0x04
0x6068 0x40
0x6044 0x20
0x4003 0x00
0x4004 0x68
0x6000 0x00 //clear reset
0x7000 0x00
0x6000 0x01 //reset digital
0x7000 0x01
0x6000 0x00 //clear reset
0x7000 0x00
0x4001 0x00 //--v prog_clk[4] and tm_clk_mux_dig enabled
0x4002 0x00
0x4003 0x00
0x4004 0x6a
0x6012 0x44
0x601F 0x00 //0x80
0x4001 0x00
0x4002 0x00
0x4003 0x01
0x4004 0x6a
0x6013 0x01
0x6014 0x80
0x601F 0x00 //0x80
0x4003 0x00
0x0012 0x04
0x0011 0x00
0x003E 0xCC //--v Unused ADC SHA and sp_clk of channel Bpowerdown
0x0033 0xCC //--v Unused ADC SHA and sp_clk of channel B powerdown
0x0052 0xC0
0x0034 0x01
0x0036 0xC0
0x0012 0x00
0x4001 0x00
0x4002 0x00
0x4003 0x00 //channel A
0x4004 0x68
0x6044 0x20 // TN validity for analog correction loop
0x6068 0x40 // TN enable for analog correction 0x40
0x60A2 0x18 // nyquist zone = 1
0x4003 0x01 // channelB
0x4004 0x68
0x6044 0x20 // TN validity for analog correction loop
0x6068 0x40 // TN enable for analog correction 0x40
0x60A2 0x08 // nyquist zone = 1
0x608D 0x50 // Firmware writes for NL correction
0x608B 0x05 // Firmware writes for NL correction
0x6000 0x00 //clear reset
0x7000 0x00
0x6000 0x01 //reset digital
0x7000 0x01
0x6000 0x00 //clear reset
0x7000 0x00
0x4003 0x00
0x6003 0x00 // No Bypass IL bypass 0x80
ADC32RFxx_DIGITAL
0x0690002 0x01 // 14b mode and JESDMODE0 = 1
0x1690002 0x01
0x0690037 0x00 // PLL DIV mode to 20
0x1690037 0x00
0x0690032 0x3C // set -6.2dB TX de-emphasis Lane 0, chA
0x1690032 0x3C // set -6.2dB TX de-emphasis Lane 0, chB
0x0690033 0x3C // set -6.2dB TX de-emphasis Lane 1, chA
0x1690033 0x3C // set -6.2dB TX de-emphasis Lane 1, chB
0x0690034 0x3C // set -6.2dB TX de-emphasis Lane 2, chA
0x1690034 0x3C // set -6.2dB TX de-emphasis Lane 2, chB
0x0690035 0x3C // set -6.2dB TX de-emphasis Lane 3, chA
0x1690035 0x3C // set -6.2dB TX de-emphasis Lane 3, chB
0x0690001 0x80 //EN CTRL K
0x1690001 0x80
0x0690007 0x0F //set K to 15
0x1690007 0x0F
ADC32RFxx_LOWLEVEL
0x6003 0x00 // Ramp mode -0x01
0x7003 0x00
0x6006 0x00 //scr en 0x80
0x7006 0x00
0x4001 0x00
0x4002 0x00
0x4003 0x00
0x4004 0x68
0x60AA 0x03 //Firmware_NL_Corr_disable 0x03
0x4003 0x01
0x60AA 0x03 //Firmware_NL_Corr_disable 0x03
0x4001 0x00
0x4002 0x00
0x4003 0x00
0x4004 0x68
0x6068 0x00 //Firmware freeze enable 0x04
0x6044 0x01 //Firmware freeze validity
0x6069 0x00 //Watch Dog timer Disable
0x6045 0x10 //Watch Dog timer Validity
0x608D 0x64 //Firmware sensor read periodicity set to 100
0x608B 0x20 //Firmware sensor read periodicity validity
0x4001 0x00
0x4002 0x00
0x4003 0x00
0x4004 0x68
0x6000 0x00 //clear reset
0x4003 0x01
0x6000 0x00 //clear reset
0x4003 0x00
0x6000 0x01 //reset_digital
0x4003 0x01
0x6000 0x01 //reset_digital
0x4003 0x00
0x6000 0x00 //clear reset
0x4003 0x01
0x6000 0x00 //clear reset
0x4003 0x00
0x4004 0x00
0x0012 0x00
0x0011 0xFF
0x00F0 0x00 // Fuse enable
0x00F1 0x00 //
0x0083 0x07 // flash convergence
0x005C 0x00 // flash convergence
0x005C 0x01 // flash convergence
0x0011 0x00
LMK04828
0x10F 0x06 //Disable SYSREF from LMK to ADC
0x10E 0xF1 //Disable SYSREF from LMK to ADC
0x100 0x04 // 

This is the ADC's ByPASS4222 schema,This is the default configuration mode of ADC ByPASS4222. I have changed the front and back clock configurations according to my own

I will confirm this question with the senior engineer again, once I received his reply, I would reply you.

Hi. I think I found the reason. As for the use of ADC32RFXX EVM GUI software, when I observed the clock chip register through oscilloscope, the SPI timing sequence was normal, but when AD was written, the SCLK of SPI timing sequence only had 10 pulses, which was not enough to write the 24-bit register. But how should this be modified

Do you mean that the LMK04828  has output only 10 pulses?  Does the PLL lock normally?

Except  only have 10 pulses, what about the amplitude and frequency, do they output correct? 

The clock register write and read are correct, but the TIMING SPI pin SCLK of the AD register write is not correct, so the register write is not correct

Hello, about your questions.

A few comments:

• The clocking level should be fine since it is coming from the LMK04828.
• SYNC pulling and staying low but no K28.5 characters indicates ADC configuration issue.
• The ADC configuration file covers the required programming sequence. It should work using the ADC EVM configuration without having to look into the ADC32RF42 datasheet.
• The EVM SPI is controlled through an FTDI chip. The GUI backend may be calling the FTDI chip API in a strange way which breaks up the clock pulses in a non-logical manner

Do you  test with a TSW14J56/57 EVM by chance to verify the configuration is functional? Alternatively, you can forward me the ADC GUI .cfg file and I can try this out in the lab.