Hello, I designed a test version of the ADC12DJ3200 chip. I collected the digital signal converted from analog signal through FPGA and *** the analog signal through digital signal. Our FPGA engineers used the JMODE1 mode and set the chip according to the recommended configuration of the register. But now I find that the digital signal collected is very abnormal. See the figure for relevant pictures, In addition, correct data can be collected in the relevant RAMP test mode and SHORT test mode. In view of this phenomenon, I would like to ask whether it is a hardware design problem or an FPGA program error.