数据转换器论坛 - 最近的话题

DAC37J82EVM: DAC37J82: Unexpectedly Long Trigger-to-Analog-Output Latency in JESD204B Subclass 1 Mode

ShiHao wang — Wed, 22 Jul 2026 06:57:34 GMT

Part Number: DAC37J82EVM
Other Parts Discussed in Thread: DAC37J82

Hello,

We are evaluating the deterministic latency of a DAC37J82 operating with
a JESD204B Subclass 1 interface. We measure approximately 250 to 260 ns
from an FPGA waveform-change trigger to the observable change at the DAC
analog output. This is significantly longer than we expected from the
known FPGA, GTY, RBD and documented DAC pipeline contributions.

Our current JESD204B configuration is:

- Device: DAC37J82
- Subclass: 1
- L = 4
- M = 2
- F = 1
- S = 1
- K = 32
- N = N' = 16
- DAC sample clock / DACCLK: 983.04 MHz
- JESD lane rate: approximately 9.8304 Gbps
- RBD = 22 frame cycles
- Interpolation disabled
- PAP disabled
- Mixer, QMC and inverse-sinc functions disabled

The FPGA continuously transmits valid JESD204B sample data. The trigger
only changes the generated sample waveform; it does not reset or
reinitialize the JESD link. SYNC remains asserted during the normal
latency measurement.

Our measured latency breakdown is approximately:

1. Trigger to waveform-generator data change:
4.1 ns

2. Trigger to the GTY TX parallel-data interface:
28.5 ns

3. Trigger through a GTY near-end PMA loopback to the GTY RX parallel
interface:
82 to 90 ns

4. Trigger to the DAC analog-output waveform change:
approximately 250 to 260 ns

Changing RBD from 22 to 26 increases the total analog-output latency by
approximately 4 ns. This agrees with four frame periods at 983.04 MHz:

4 / 983.04 MHz = approximately 4.07 ns

Therefore, the RBD setting appears to be active and behaves as expected.
However, the overall trigger-to-analog-output latency remains around
250 ns.

As an additional diagnostic, we tested the SIFDAC path by changing the
SIFDAC data through the serial interface. The approximate response times
were:

- DACCLK = 983.04 MHz: approximately 151 to 153 ns
- DACCLK = 491.52 MHz: approximately 300 ns

The response time approximately doubles when DACCLK is halved, suggesting
that a large portion of this response is determined by a DACCLK-cycle-
based synchronization or digital pipeline.

We also tested the PAP function at 491.52 MHz:

- PAP disabled: approximately 300 ns
- PAP enabled: approximately 440 ns
- Increment: approximately 140 ns

This increment corresponds to approximately 69 DACCLK cycles and is close
to the documented PAP latency of 68 DACCLK cycles. This gives us
confidence that our measurement can identify DACCLK-cycle-based latency
changes.

We understand that the SIFDAC path may include serial-register update and
clock-domain synchronization latency, and that it may not follow exactly
the same path as normal JESD204B sample data. We therefore do not assume
that the measured SIFDAC latency directly represents the JESD receive
latency. We are using it only as a diagnostic indication that a relatively
long clocked path may exist inside the DAC.

Could you please clarify the following points?

1. What is the expected latency from the DAC37J82 JESD serial input to the
analog output for the configuration listed above?

2. Which internal blocks contribute to this latency, and how many DACCLK
or frame-clock cycles does each block contribute?

3. Is there an elastic buffer, JESD receive FIFO, synchronization stage or
common digital pipeline after the SerDes/8b10b block that contributes
significant latency?

4. Can this FIFO or digital pipeline be bypassed or configured for minimum
latency while retaining JESD204B Subclass 1 deterministic latency?

5. Does the documented 11-DACCLK-cycle latency apply to this exact
configuration with interpolation, PAP, mixer, QMC and inverse-sinc
disabled? If so, from which internal reference point to which output
point are those 11 cycles defined?

6. Which internal blocks are shared by the SIFDAC path and the normal
JESD204B sample-data path?

7. Does a SIFDAC response of approximately 150 DACCLK cycles indicate a
normal register-update synchronization delay, or does it indicate the
latency of a shared DAC digital-output pipeline?

8. Is there a recommended register configuration or test method for
measuring the minimum deterministic JESD-input-to-analog-output latency
of the DAC37J82?

Our primary concern is the approximately 250 to 260 ns total
trigger-to-analog-output latency. The SIFDAC measurement is only an
additional observation that may help identify where the unexpected delay
is introduced.

K32.txt

Thank you.

AFE4404: 是否可以提供额头部位的血氧算法

yb bai — Tue, 21 Jul 2026 06:01:20 GMT

Part Number: AFE4404

我用贵司的血氧模拟前端AFE4404+SFH7050做血氧模块,用于测试人体额头部位的脉率和血氧,用的参考代码是TI官网下载的:AFE4404EVM_FW_SRC_v1.5_Release,该参考代码中的hrm.c 心率算法测试额头部位的心率比较准确,贵司是否可以提供对应的血氧算法？多谢支持

AFE4404: 是否可以提供额头部位的血氧算法

yb bai — Tue, 21 Jul 2026 06:00:01 GMT

Part Number: AFE4404

DAC39RF10: dac需要直流输出，看手册碰到一些问题

xiao weihua — Fri, 17 Jul 2026 08:09:06 GMT

Part Number: DAC39RF10

我打算使用TRF1305放大器接到DAC的输出，实现差分转单端输出。

数据手册给出了DAC core里的Ibias、Ifs等电流的表达式，后面又给了一个静态电流的表达式，要求静态电流为满幅电流的0.235倍，这是需要我们配置完满幅电流后，再修改寄存器配置Ibias电流为静态电流吗？0.235的关系是从哪里来的，必须要满足吗？

TX7364: 哪可以提供TX7364和AFE5832的数据手册？

Yuan CL — Fri, 17 Jul 2026 06:26:58 GMT

Part Number: TX7364
Other Parts Discussed in Thread: AFE5832

您好！

我们设计新产品，使用TX7364+AFE5832器件,哪里可以提供数据手册？

谢谢

CL Yuan

TSW14J57EVM: Alternative Recommendation for TSW14J57EVM

國文陳 — Fri, 17 Jul 2026 01:34:04 GMT

Part Number: TSW14J57EVM
Other Parts Discussed in Thread: ADC12DJ5200SEEVM, , TSW14J59EVM, TSW14J58EVM

Hi TI Team,

I reviewed the ADC12DJ5200SEEVM user guide and noticed that the evaluation module requires the TSW14J57EVM for data capture and evaluation.

However, it appears that the TSW14J57EVM has been discontinued, and we are currently unable to procure this product.We also find the product TSW14J58EVM TSW14J59EVM seems also been discontinued

Could you please recommend an alternative evaluation or data capture platform that is compatible with the ADC12DJ5200SEEVM?

We would appreciate any suggestions regarding:

Direct replacement products for TSW14J57EVM
Newer TI evaluation platforms

TX73H32: Questions about the datasheet

sifeng lian — Thu, 16 Jul 2026 11:02:18 GMT

Part Number: TX73H32

P116.Section 9.4, item 7 of the technical manual（sbasb47a_TX73H32_Datasheet） says the wake-up time is 200us, but Figure 9-3 below says 200ms. Which one is correct?

TX73H32: Questions about the datasheet，TX73H32

sifeng lian — Thu, 16 Jul 2026 10:51:22 GMT

Part Number: TX73H32

P116.Section 9.4, item 7 of the technical manual（sbasb47a_TX73H32_Datasheet） says the wake-up time is 200us, but Figure 9-3 below says 200ms. Which one is correct?

AFE882H1: VREFIO输出

xu xia — Wed, 15 Jul 2026 02:10:38 GMT

Part Number: AFE882H1

我在测试时发现，当IOVDD未通电时，VREFIO无输出，VDD电压1.7V。IOVDD上电，reset引脚拉高后，VREFIO正常输出，VDD电压1.8V。

数字引脚reset会影响VREFIO的输出，这种情况是正常的吗？

ADC3648: ADC3648 CHB采样的底噪异常

liang wang — Tue, 14 Jul 2026 10:42:51 GMT

Part Number: ADC3648

ADC3648测量时，发现CHB采样的的底噪异常偏大且呈现一定的周期性，CHA正常，有排查方向吗

ADS1299EEGFE-PDK: ADS1299 共模抑制比无法满足手册要求110dB，且工频噪声有200uV.

? ? — Tue, 14 Jul 2026 10:13:29 GMT

Part Number: ADS1299EEGFE-PDK
Other Parts Discussed in Thread: ADS1299

最近也在调试ADS1299 这款芯片，（测试环境如下：ADS1299能够正常工作，根据手册和开发板参考设计进行设计，并且启用了BIAS功能。所有通道的差分负输入都连接到了SRB1，SRB1作为统一参考位点连接到右侧耳垂。BIAS输出电极连接到左侧耳垂。PGA增益都为1。正电源为2.5V，负电源为-2.5V。其余硬件电路按照

ADS1299EEG-FE EEG Front-End Performance Demonstration Kit (Rev. B)

手册进行设计的50-51页）

问题1：在测试过程中，仅开启IN1P通道，（其他通道设置为001=输入短路）配置寄存器将IN1P和SRB1内部短接，测得短接噪声约为5uV，但当外部短接测试，噪声将达到20uV~100uV左右，同时通道2、3、4、5、6、7、8 测试过程中用手触摸，也会影响测试波形；

问题2：在测试过程中，仅开启IN1P通道（其他通道设置为001=输入短路），工频噪声很大，且共模抑制比仅有85dB，

原理图参考

ADS1299EEG-FE EEG Front-End Performance Demonstration Kit (Rev. B)

文件进行设计和布局。请协助解决，谢谢，

ADS125H02: 有的ADS125H02芯片，在0.25倍增益时，输入9992mV就满量程了，那咋测量10000mv输入信号呢？

GE BAOSHAN — Tue, 14 Jul 2026 08:50:05 GMT

Part Number: ADS125H02

我在调试基于ADS125h02的数据采集仪过程中，发现有些ADS125h02芯片，输入信号9992mV，输出就达到满量程9999.21mV了，输入高于9992mv，输出都一样是9999.21mv，看来是过荷了，那怎样解决这个问题呢？使得我还能正确测量9992~10000mv之间的输入。采用的内部参考电压，参考电压也无法调大，如果调大也能解决这个问题。

TSW14J57EVM: ADC12DJ5200SEEVM 搭配之數據擷取卡(TSW14J57EVM)停產替代型號詢問

國文陳 — Tue, 14 Jul 2026 07:48:35 GMT

Part Number: TSW14J57EVM
Other Parts Discussed in Thread: ADC12DJ5200SEEVM, , TSW14J59EVM

Hi,TI
我們團隊近期購買了 TI 的 ADC12DJ5200SEEVM 評估板。查閱說明書（User's Guide）後得知，若要進行數據輸出與擷取，需要搭配 TSW14J57EVM 擷取卡。

經確認，發現 TSW14J57EVM 這一型號目前已經停產。請問 TI 官方是否有推薦、規格相容（支援 JESD204C 協定且接頭匹配），且目前尚未停產/正常供應的替代板子型號？

TSW14J57EVM: ADC12DJ5200SEEVM 搭配之數據擷取卡(TSW14J57EVM)停產替代型號詢問

國文陳 — Tue, 14 Jul 2026 07:38:03 GMT

Part Number: TSW14J57EVM
Other Parts Discussed in Thread: ADC12DJ5200SEEVM,

Hi,TI

我們團隊近期購買了 TI 的 ADC12DJ5200SEEVM 評估板。查閱說明書（User's Guide）後得知，若要進行數據輸出與擷取，需要搭配 TSW14J57EVM 擷取卡。

謝謝

ADS8665: ADS8665：AVDD关闭（0V）且DVDD为3.3V时AIN_P是否带电

Jacob — Mon, 13 Jul 2026 06:02:10 GMT

Part Number: ADS8665

TI专家您好，

我在使用ADS8665检测连接至AIN_P引脚的外设模拟信号。系统中：

DVDD = 3.3V（常开）
AVDD = 5V（可独立关闭）

我观察到，当 AIN_P 引脚处于悬空状态（没有外部外围设备连接时），该引脚上会存在约 1V的电压。根据数据手册以及相关的 E2E 讨论，这是由于器件内部的偏置电压所致。

我的问题是：如果关闭AVDD（置为0V），同时DVDD保持3.3V，能否保证AIN_P引脚上不带电（即0V）？

期待您的解答，谢谢！

ADS1299: ADS1299采样饱和和信噪比下降

SHEN Rui — Fri, 10 Jul 2026 12:43:47 GMT

Part Number: ADS1299

基本背景：ADS1299能够正常工作，根据手册和开发板参考设计进行设计，并且启用了BIAS功能。所有通道的差分负输入都连接到了SRB1，SRB1作为统一参考位点连接到右侧耳垂。BIAS输出电极连接到左侧耳垂。PGA增益都为24。正电源为2.5V负电源为-2.5V

问题1：所有通道正常连接并且和皮肤良好接触，由于ADS1299是直流耦合，观察采样原始数据可以发现，所有通道会在20min-30min逐渐饱和，饱和趋势一致最后接近-0.1875V（也有时候一起接近+0.1875），这种发生推着时间变化饱和的原因是什么，需要怎样修改？

问题2：假设一块ADS1299开启了BIAS_PD使能，并且选择了通道123作为BIASSENS+和-。当我只是连接通道1，2，3时候，其余45678悬空。此时4，5，6，7，8通道映入大量工频，1，2，3通道正常采样。对于1-8通道全部连接额情况，发现只连接良好的1，2，3通道采样信号的信噪比不如1-8通道全连接的情况，理论上每一个通道都有独立的滤波，放大和adc电路，请问原因是什么？如何解决

TPL0102-100: 3Dmodel unavailable

Yanni Chou — Fri, 10 Jul 2026 08:02:11 GMT

Part Number: TPL0102-100

I cannot press the submit button

TPL0102-100: 3Dmodel unavailable

Yanni Chou — Fri, 10 Jul 2026 08:01:03 GMT

Part Number: TPL0102-100

I cannot press the submit button

ADS9324: ADS9324 的SPI配置口，与数据并口的冲突

long ye — Thu, 09 Jul 2026 06:53:21 GMT

Part Number: ADS9324

我们板子采用MCU STM32H563VIT6，搭配TI ADC芯片的ADS9324，ADC芯片的配置端口和数据端口共用CLK、CS，但Data线是分开的（如下图）：

我们打算将ADS9324的SPI Data连接到MCU的PSSI接口，但ADS9324无clk输出，所以想把SPI_CLK回接到MCU PSSI_CLK上，请帮忙确认下是否可以，谢谢！另外，SPI配置和PSSI数据传输能够同时进行吗？

AFE5832: 32 通道便携式工业超声探伤仪硬件选型咨询，AFE5832 搭建可行性、参考设计

ky s — Wed, 08 Jul 2026 10:57:24 GMT

Part Number: AFE5832

您好，TI技术支持团队：

本人目前正在进行一款便携式多通道超声波相控阵探伤仪的研发工作，主要应用于工业无损检测领域。目前正在进行系统架构设计和硬件选型，基础机型 32 通道，预留扩展能力升级至 128 通道阵列探伤，探头工作频率 2~10MHz，后端采用 FPGA 完成信号采集与算法处理，设备小型化便携设计。，用于金属焊缝、材料内部缺陷无损检测，希望获得TI工程师关于整体方案设计、器件选型以及AFE5832应用方面的指导。设计咨询如下：

一、关于32通道超声探伤仪硬件方案咨询

接收端方面，想确认适配该设备的器件，核心咨询AFE5832是否可作为32通道超声接收核心，同时希望获取TI其他备选解决方案。发射端方面，本项目采用“FPGA波形生成-DAC转换-高压脉冲驱动-超声探头”的架构，现咨询TI适配的DAC芯片、超声发射脉冲器、高压驱动电路以及收发隔离T/R开关的相关选型方案。

二、关于AFE5832应用的问题

想向您确认 AFE5832 能否适配工业无损检测、相控阵探伤等多通道超声回波采集场景，TI 是否有相关落地应用方案，比如AFE5832的实际应用案例或参考设计，是否提供相关设计资料作为硬件设计参考以及外围电路连接方案，并咨询官方资料的获取渠道。另外在电路仿真验证，但目前未能检索到 AFE5832 配套 PSpice、IBIS 仿真模型，想咨询芯片仿真模型的获取途径与系统仿真相关建议。

三、关于128通道扩展方案咨询

本项目后续计划将系统扩展至 128 通道，特此咨询 TI 相关扩展方案：是否推荐多颗 AFE5832 级联方案，多 AFE 之间如何进行时钟同步、Zynq FPGA 处理多路 LVDS 高速数据流的设计思路，同时是否有 64 通道 / 128 通道超声设备官方参考架构。

麻烦工程师提供对应技术资料与方案建议，感谢支持！

DAC8551: DAC8551 bipolar offset output increases system noise when connected to a difference amplifier

Maoliang Jian — Wed, 08 Jul 2026 08:12:28 GMT

Part Number: DAC8551
Other Parts Discussed in Thread: OPA189, OPA828,

Hello everyone,

I am designing a high-precision analog front-end for measuring small voltage variations. The system includes an instrumentation amplifier, a DAC-based dynamic offset cancellation stage, a fixed-gain difference amplifier, a programmable gain stage, and a high-speed SAR ADC.

The issue I am seeing is that once the DAC offset path is connected to the fixed-gain difference amplifier, the input-referred RMS noise increases from a few µV to about 30–40 µV RMS. More interestingly, even when the inputs of the DAC offset amplifier are both tied to AGND, so that its output should ideally be 0 V, the noise is still almost the same as when the full DAC offset circuit is connected.

1. System structure

The measured signal first goes through an instrumentation amplifier and is converted to a single-ended signal. It then enters a fixed-gain difference amplifier, which implements:

Vout = 5 × (Vsignal - VDAC_bias)

The fixed difference amplifier currently uses a high-speed, low-noise op amp. The resistor values are:

Input resistors: 300 Ω Feedback / reference-side resistors: 1.5 kΩ Gain: 5 V/V

After this stage, there is a non-inverting PGA with gain settings:

1 / 2 / 4 / 8

Therefore, the total analog gains are:

5 / 10 / 20 / 40

All noise data below is input-referred RMS noise, calculated after dividing by the corresponding total analog gain.

2. DAC offset circuit

The DAC offset path is used to generate a bipolar offset voltage, so that the DC component of the measured signal can be subtracted before further amplification.

The offset circuit is:

2.048 V precision reference → DAC8551 reference

DAC8551 output → 34 kΩ + 470 nF RC low-pass filter → non-inverting input of offset op amp

2.048 V precision reference → 5 kΩ → inverting input of offset op amp

offset op amp output → 5 kΩ → inverting input of offset op amp

Therefore, the low-frequency transfer function is:

VDAC_bias = 2 × VDAC - 2.048 V

When the DAC output is 1.024 V, the offset amplifier output should be approximately 0 V.

I have tried both OPA189 and OPA828 as the offset amplifier, but the noise level did not change significantly. I also tried different capacitors in parallel with the 5 kΩ feedback resistor, such as 10 nF and 330 pF, but there was no fundamental improvement.

3. Test data

The following data is input-referred RMS noise in volts. Each row corresponds to PGA gain settings:

1 / 2 / 4 / 8

3.1 Full circuit connected

The DAC offset output is connected normally to the fixed 5× difference amplifier.

1 MSPS:
3.95E-05   3.71E-05   3.39E-05   3.18E-05

2 MSPS, average every 2 samples:
3.28E-05   3.20E-05   3.08E-05   2.90E-05

The input-referred noise is around 30–40 µV RMS.

3.2 DAC offset path disconnected

In this test, the DAC offset output is disconnected from the fixed difference amplifier. The original DAC offset input of the difference amplifier is tied directly to AGND. The main signal path is still connected normally.

1 MSPS:
6.46E-06   6.15E-06   4.76E-06   3.92E-06

2 MSPS, average every 2 samples:
4.77E-07   1.46E-06   2.13E-06   2.17E-06

In this condition, the main signal chain can reach a few µV RMS input-referred noise.

3.3 Offset amplifier inputs tied to AGND, but output still connected

In this test:

The non-inverting input of the offset amplifier is tied to AGND.

The 5 kΩ resistor that normally connects the 2.048 V reference to the inverting input is also tied to AGND instead of 2.048 V.

The 5 kΩ feedback resistor remains connected.

The offset amplifier output is still connected to the fixed 5× difference amplifier.

In this condition, the offset amplifier should ideally output 0 V.

However, the measured noise is:

1 MSPS:
3.88E-05   3.94E-05   3.52E-05   3.47E-05

2 MSPS, average every 2 samples:
3.41E-05   3.38E-05   3.31E-05   3.08E-05

This result is almost the same as when the full DAC offset circuit is connected.

Therefore, the noise does not seem to come mainly from the DAC8551 output code itself, nor only from the 2.048 V reference. Even when the offset amplifier inputs are both grounded and the expected output is 0 V, connecting this active 0 V output to the difference amplifier still brings the noise back to the 30–40 µV RMS level.

4. Other tests already performed

To rule out cable effects, I used a shielded cable. The shield is connected to AGND only at the acquisition board side, while the far end of the shield is left floating. The far-end Sense+ and Sense− wires are shorted together.

I also tried removing the cable and shorting Sense+ and Sense− directly at the input connector of the board. As long as the DAC offset amplifier output is connected to the fixed difference amplifier, the noise remains much higher than when the DAC offset path is disconnected.

I also tried splitting the original 300 Ω DAC-bias input resistor of the fixed difference amplifier into:

DAC offset op amp output → 100 Ω → middle node → 200 Ω → difference amplifier input

Then I added a capacitor from the middle node to AGND. However, the noise increased by about 10–20 µV. After removing this capacitor, the noise returned to the original 30–40 µV RMS level.

So this middle-node capacitor did not help. It may have introduced AGND noise or parasitic effects from the temporary wiring.

5. Current thoughts

At this point, I suspect the issue may be related to one or more of the following:

The DAC offset amplifier output, used as an “active 0 V” or active bias source, is not as quiet as a direct AGND connection.
The offset amplifier is driving a relatively low input resistance of 300 Ω into the difference amplifier, which may make its output noise, power-supply noise, or stability issues more visible.
When the active DAC offset source is connected to the difference amplifier, the input network or layout parasitics of the difference amplifier may cause noise peaking.
The 5 kΩ / 5 kΩ feedback network of the offset amplifier may have too high an impedance, making the inverting node sensitive to parasitic coupling and noise.

6. Planned modification

I am planning to reduce the two 5 kΩ resistors in the DAC offset amplifier to 2.2 kΩ:

Feedback resistor = 2.2 kΩ
Reference input resistor = 2.2 kΩ
Feedback capacitor ≈ 10 nF

This should still keep the same transfer function:

VDAC_bias = 2 × VDAC - 2.048 V

but with a lower impedance at the inverting node, which may reduce thermal noise and sensitivity to parasitic coupling.

7. Questions

In this type of circuit, can the noise increase from a few µV RMS to 30–40 µV RMS simply because an active DAC offset source is connected to the difference amplifier?
Could the 300 Ω DAC-bias input resistor of the difference amplifier be too low for the DAC offset amplifier, causing output noise, supply noise, or stability issues to be injected into the following stage?
For this kind of structure:

Vout = 5 × (Vsignal - VDAC_bias)

should the DAC offset source be designed as a lower-output-impedance and lower-bandwidth precision bias source?

Is reducing the offset amplifier resistor pair from 5 kΩ / 5 kΩ to 2.2 kΩ / 2.2 kΩ a reasonable direction for reducing noise and parasitic sensitivity?

8. Summary

The main point that confuses me is:

When the DAC offset amplifier inputs are both tied to AGND, its output should ideally be 0 V. However, as soon as this output is connected to the fixed 5× difference amplifier, the system noise becomes almost the same as when the full DAC offset circuit is connected.

Does this behavior look more like a noise / stability problem of the active offset source itself, or more like an issue with the input network / layout of the following difference amplifier?

Thank you.

AFE4404: 关于AFE4404使用单通道LED的问题

?? ? — Tue, 07 Jul 2026 12:36:59 GMT

Part Number: AFE4404

TI工程你们好：

我们现在有个新项目，使用的是AFE4404这个芯片，我们的需要只需要测心率信号即可，用于在耳机上做心率检测空间非常有限，所以只使用了一路led。现在根据之前多路的代码器修改，关闭其他多余的LED现在的结果显示采样的数据很不正常。经过多次尝试没有解决。

现在的问题是：

1.使用一路LED的时候应该如何去配置LED寄存器。

2.关于环境光的测量这个能配置吗，理论上环境光应该是LED没有启动的时候测试的数据。但是这个数据的读取流程应该是怎么实现的。

ADS42LB69: ADS42LB69支持的204B接口模式

zheng nan — Tue, 07 Jul 2026 04:23:45 GMT

Part Number: ADS42LB69
Other Parts Discussed in Thread: ADS42JB69

你们好，我们目前在开发设计ADS42LB69这款芯片，但我们想要使用JESD204B模式，但是通过技术手册获取到的接口pin只有LVDS和QDR LVDS 的接口，也没有找到相关的参考设计，请给予相关的支持，和相关资料，谢谢

AFE4404: AFE4404 AGC自动校准算法优化及测试额头部位低概率出现无法收敛的问题

yb bai — Mon, 06 Jul 2026 11:42:46 GMT

Part Number: AFE4404

我用AFE4404+SFH7050A做血氧项目,用于测试人体额头部位心率和血氧,AFE4404 驱动和校准算法,参考的是AFE4404EVM_FW_SRC_v1.5_Release代码,现在有问题请教如下:

1,Calibration_AFE4404.c中自动校准算法(AGC) 若应用到人体额头部位,相关参数是否需要优化,该如何优化？

2,我现在用默认的Calibration_AFE4404.c 的自动校准算法(AGC)测试额头部位的心率值,心率算法也是默认的statHRMAlgo(led1_aled1),LED_Sel = 1(红灯),会概率出现自动校准算法无法收敛的问题,一直在校准,参考afe4404_自动校准.log ,该log会打印自动校准的值;该问题是低概率问题,大部分情况自动校准算法(AGC) 是可以收敛的,可以得到心率值在70左右,跟第三方的指夹血氧仪器测试的心率值基本一致;

3,从log中看到,若我使用自动增益算法,若LED_Sel = 1,那么对应的LED2 绿灯,LED3红外灯电流值0.0mA,现在需要测试血氧和心率值,至少需要把红灯和红外灯点亮，这个问题该如何解决？

AFE4400: 想问下有关于AFE4600这款芯片的相关参考资料吗？

CAO SHENG — Fri, 03 Jul 2026 02:52:09 GMT

Part Number: AFE4400

想了解及AFE4600/4601的相关资料以及该芯片如何可以采购？