数据转换器论坛 - 最近的话题

AFE58JD32: I am developing an ultrasound system using the AFE58JD32 analog front end and the TX73H32 transmitter.

ke ma — Thu, 29 Oct 2026 07:41:24 GMT

Part Number: AFE58JD32
Other Parts Discussed in Thread: TX73H32, , , TX73H32EVM

Dear Texas Instruments Technical Support Team,

I am developing an ultrasound system using the AFE58JD32 analog front end and the TX73H32 transmitter.

I would like to request the complete technical documentation and development resources for both devices, including the following:

1. Complete datasheets with full package pin/ball assignments and terminal functions.
2. Complete register maps, including register addresses, bit-field definitions, reset values, and access permissions.
3. SPI/serial programming specifications and timing requirements.
4. Power-up, reset, and initialization sequences.
5. AFE58JD32EVM and TX73H32EVM user guides, schematics, and related design files.
6. EVM GUI software, reference source code, register configuration files, and initialization examples, if available.
7. For TX73H32, documentation covering beamformer RAM programming, pattern profiles, delay profiles, and checksum calculation.

I understand that some resources may require an NDA. Please let me know the appropriate process for obtaining these documents and whether any additional documentation is available to qualified customers.

Thank you for your assistance.

Best regards,

AFE159RP8: 恳请提供 AFE159RP8 完整开发资料包，包含数据手册、参考设计、寄存器手册、评估板固件、PCB 指南、时序与校准文档等，支撑 8 通道心电采集方案的技术调研、方案比对与项目可行性评审。

?? ? — Mon, 26 Oct 2026 04:27:12 GMT

Part Number: AFE159RP8
Other Parts Discussed in Thread: ADS1292,

我司是动态心电设备研发生产厂商，现有量产型号 ECG_EG01 采用 ADS1292 级联方案。现阶段开展产品升级迭代，拟评估 AFE159RP8 作为新一代心电模拟前端芯片。现申请获取上述全套开发资料，用于新旧方案对比、软硬件移植评估、性能指标验证以及新产品可行性评审。若存在 NDA 受控资料，烦请告知相关申请流程。

ADC3660: ADC3660Sampling Glitch Filter Design

chao yan — Fri, 23 Oct 2026 03:17:32 GMT

Part Number: ADC3660

目前需要使用ADC3660分时采集5MHz，以及70MHz的信号，公共端是5MHz低通和70MHz带通通过开关切换到如图所是的Ref_CH_OUT端口，器件文件只推荐了dc~30MHz以及30~70MHz的Sampling Glitch Filter，关于这个Sampling Glitch Filter是否有仿真工具？或者推荐一个能够针对目前应用的Sampling Glitch Filter参数。

ADS122C04: 紧急问题TADS122C04IPWR 温度采集低8位数据为零

lifen liang — Fri, 23 Oct 2026 01:50:23 GMT

Part Number: ADS122C04

紧急问题TADS122C04IPWR 温度采集低8位数据为零

ADS1299EEGFE-PDK: 申请资料

wl xie — Wed, 21 Oct 2026 06:17:44 GMT

Part Number: ADS1299EEGFE-PDK
Other Parts Discussed in Thread: ADS1299,

Dear TI Technical Support Team,

I am studying the ADS1299 for personal research and EEG signal acquisition prototyping.

I have reviewed the publicly available ADS1299EEGFE-PDK user guide (SLAU443B), including its schematics, BOM, and PCB layer drawings.

I would like to ask whether the complete Gerber and NC drill files for this evaluation board are available for download or can be shared with individual developers.

I do not currently own the evaluation board, but I would like to build a prototype for learning and testing purposes.

I understand that the original PCB CAD source files may not be publicly available. If the Gerber and drill files can be shared, that would already be very helpful.

Thank you for your time and assistance.

Best regards

ADS1248: ADS1248采集数据饱和

fenqiang wang — Tue, 20 Oct 2026 08:52:35 GMT

Part Number: ADS1248

采用ADS1248测量PT1000，采用3线制，测温范围0-100度，两路激励电流源为100uA，外部参考电阻为10K，当放大倍数为1时，能读取到正常数据，当放大倍数为其他数值时，读到的是满量程数据，通过计算设置的参考电压，共模电压都在正常范围内，烦请分析一下是什么原因导致的

ADS131B24-Q1: ADS131B24Q SPI COM in CRC error

zuotao xu — Tue, 20 Oct 2026 03:02:12 GMT

Part Number: ADS131B24-Q1

Hi teams:

I got an ADS131B24Q in my board, use a uC to communicate with it.I use an logic analyser to check SPI received data is keep 7B D0 which means CRC error.But I use the example code of ADS131B2X to send the date, pls check the pic following:

ADS8568EVM-PDK: ADS8568EVM-PDK

shuyuan chou — Wed, 14 Oct 2026 06:44:48 GMT

Part Number: ADS8568EVM-PDK

HELLO

ti can you send me a

ADS8568EVM-PDK doc

thanks

Bruce

ADS1278: 画一个ads1278的开发电路模块

benbin wang — Tue, 13 Oct 2026 05:52:33 GMT

Part Number: ADS1278

想要一个ads1278的开发电路模块

ADS127L11: the spectrum of output data is not correct

huang yinglai — Sat, 10 Oct 2026 12:28:22 GMT

Part Number: ADS127L11

I use stm32h743 to drive the ads127l11 to acquisite a 1000hz tone sound produced by cell phone speaker, but get 786hz peak from the output data spectrum. the signal conditioning circuit is refer to TI IEPE, and the input signal at AINP AINN is tested to be 1000hz peak by other device. please help me to find the root cause, thanks.

ADC3683: ADC3683与主控芯片的连接方式

yi dong — Sat, 10 Oct 2026 08:24:33 GMT

Part Number: ADC3683

ADC3683芯片数据输出接口为1.8V的差分接口，主控FPGA芯片的bank在1.8V供电的情况下，数据传输速率是否可以达到要求

ADS9324: ADS9324 Phase delay 和 channel-to-channel aperture skew 范围

long ye — Thu, 08 Oct 2026 08:02:24 GMT

Part Number: ADS9324

1, 如图片，我需要知道相位延迟的范围，规格书只给了一个典型值，需要min与max值

2, 通道与通道之间采样时间差的min与max值

DAC8812: DAC8812的替换

dd ss — Thu, 08 Oct 2026 04:33:51 GMT

Part Number: DAC8812

DAC8812的可替换DAC芯片，电压型和电流型都可以，需要用2个通道

AFE58JD28: phase noise

W HT — Wed, 07 Oct 2026 12:50:36 GMT

Part Number: AFE58JD28

I am using the AFE58JD28 as a multi-channel acquisition chip, with a 40-Msps sampling clock and 14-bit resolution, and I am only using the P side. Now, after FFT, my ADC data shows an envelope near 0 Hz. How can I determine whether this envelope comes from the phase noise of the sampling clock or from 1/f noise? I tried changing the sampling clock source from the HMC7044 to a signal generator, but there was no significant improvement.

ADS1278-EP: ADS1278的SCLK和CLK的约束关系

LuXuan Cao — Tue, 29 Sep 2026 23:53:39 GMT

Part Number: ADS1278-EP

从框图上看SPI Interface使用SCLK作为时钟（我理解SCLK是控制移位寄存器进行移位），Control Logic使用CLK作为时钟，两者看起来似乎是独立的，为什么需要有fSCLK <= fCLK的约束条件。如果不满足此条件，会导致什么问题。

我在https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1372240/ads1278-ads1278-reading-issues 看到TI工程师回复如果不满足fSCLK <= fCLK这个条件，会导致数据出错（见下图红框标注），但是之前我们使用时未注意到这个条件，使用的fCLK=12MHz，fSCLK=25MHz，但是一切工作正常，这正常吗？

AFE4432: data

QH LI — Tue, 29 Sep 2026 08:53:20 GMT

Part Number: AFE4432

ADS131E08: pga_gain=8或12时，INL测不到datasheet上的值

Phinney xiong — Mon, 28 Sep 2026 08:59:30 GMT

Part Number: ADS131E08

在ADS131E08的datasheet上可以看到，pga_gain=8或12时，INL最大值在12ppm of FS左右。

但我在实际测试时，pga_gain=8时，INL最大值在18ppm of FS左右，pga_gain=12时，INL最大值在25ppm of FS左右，与datasheet上的值不符合。

我一开始怀疑是信号源noise太大导致INL测不过，因此对比了信号源输入DC电压的noise和芯片内部短接的noise。pga_gain=8时，芯片内部短接的noise=1.73uvrms，与datasheet上的值一致；信号源输入下的noise=2.2uvrms。两种情况下noise相差不大，因此我觉得可以排除信号源noise的影响。另外增加采样点数后，INL的测试结果也不会改善。分析下来感觉是芯片本身的INL在pag_gain=8或12时测不到datasheet上的值。需要帮忙确认下感谢？

我是按照INL=(Vout值-直线拟合值)/(2*FS/gain)来计算的，采用的是最佳直线拟合法。所以想请教下pga_gain=8或12时INL的计算方法是否有问题？感谢~

DAC39RF20: dac39rf20是否支持12bit 40G采样率，20G瞬时带宽？

zhihua zheng — Thu, 24 Sep 2026 00:17:29 GMT

Part Number: DAC39RF20

1）手册中支持，使用双边沿采用可以达到44G采样率，但全文没有给出44G采样率的应用模式。

2）芯片是否支持40G采样率，12bit 单通道，16lane的应用场景呢？

那么，瞬时带宽可以达到20G？是这样吗。

AMC7836: ADC/DAC Product Selection Guide

Chance Zhan — Wed, 23 Sep 2026 15:26:56 GMT

Part Number: AMC7836

The customer was originally using the competitor's TPA7836B-QP, and now they want one with a smaller package than the TPA7836B-QP, supports 16-bit, and has detection accuracy at the uV level. Do we have any recommendations?

ADS1299EEGFE-PDK: EEG外设接线方法是怎么接的

Haodong Chang — Tue, 22 Sep 2026 08:31:18 GMT

Part Number: ADS1299EEGFE-PDK

EEG信号采集。接线的方法是怎那么样的？

三个电极，其实只能出一路信号
（1）测量电极1P
（2）参考电极（REF）这个 jP25 的5 6引脚短接，jp8进入SRB1.这个没有外接引脚
（3）偏置电极（BIAS） JP1进入 biasout然后形成共模抑制

参考电极（REF）是没有外接引脚的。需要飞线接吗

ADS52J66: 需要原理图

YOUPENG FENG — Tue, 22 Sep 2026 02:04:11 GMT

Part Number: ADS52J66

需要ADS52J66IRGCR原理图

AFE4403: PPG原始信号占空比21%以下无噪声，21%以上反而有噪声

wang chao — Fri, 18 Sep 2026 10:19:11 GMT

Part Number: AFE4403

如图，参考最上面的一条曲线，有明显噪声，占空比为22%，下面这幅图占空比为21%，无噪声。

TCA9535: TCA9535PWR-- Lead Color Change Observed After Reflow Soldering

user4727740 — Thu, 17 Sep 2026 08:26:36 GMT

Part Number: TCA9535

I have provided feedback on the TCA9535PWR， A problem has occurred in PB: during the reflow soldering process, the component leads change color(Turning black and dark) from their original plating color...

Please refer to the picture below!

May I ask why? Is it normal?

AFE58JD28: Multiple AFE58JD28 devices synchronization and link establishment repeatability

?? ? — Wed, 16 Sep 2026 12:23:38 GMT

Part Number: AFE58JD28

Hello, we are currently attempting to integrate 8 afe58jd28 devices onto a single PCB. We are currently using subclass 1. Regarding the single afe device, what is the most ideal ramp test result? Does it need to ensure that the first valid data decoded by the FPGA after each link remains the same? Currently, the first ramp test data for each individual afe in our results is constantly changing and fluctuating between two sampling points. This makes it extremely difficult for me to establish a baseline for aligning the 8-device array.
Secondly, when debugging the 8 devices, do the 8 trig signals need to be of equal length?
Thirdly, does the processing of the 8 AFEs in accordance with the JESD204B standard need to be carried out within the same clock domain? Is it necessary to connect the sync signal line?
Looking forward to your reply very much.

DAC39RF12: DDS输出模式是偶尔有底噪抬升现象。

wang xiao — Tue, 15 Sep 2026 07:50:16 GMT

Part Number: DAC39RF12

如图，在DDS模式下，进行相噪测量时，发现偶尔有相位突变的现象。

DAC39RF12的连接方式：OUT1通路输出：P端通过电阻上拉到1.8V后，接滤波电路输出10M以下，N端通过偏置巴伦到1.8V，接滤波电路输出10M以上。（P端和N端用万用表测得电压一致）。可能是哪块原因？