数据转换器论坛 - 最近的话题

AFE4404: 是否可以提供额头部位的血氧算法

yb bai — Tue, 21 Jul 2026 06:00:01 GMT

Part Number: AFE4404

我用贵司的血氧模拟前端AFE4404+SFH7050做血氧模块,用于测试人体额头部位的脉率和血氧,用的参考代码是TI官网下载的:AFE4404EVM_FW_SRC_v1.5_Release,该参考代码中的hrm.c 心率算法测试额头部位的心率比较准确,贵司是否可以提供对应的血氧算法？多谢支持

RE: AFE4404: 是否可以提供额头部位的血氧算法

Daniel — Tue, 21 Jul 2026 06:14:18 GMT

您好

AFE4404EVM：转换为PPG和SPO2信号 - 数据转换器论坛 - 数据转换器 - TI E2E支持论坛

(7) AFE44S30: 关于LED电流范围的咨询 - 数据转换器论坛 - 数据转换器 - E2E™ 设计支持

请您参考这两个帖子说明。

RE: AFE4404: 是否可以提供额头部位的血氧算法

Eirwen — Tue, 21 Jul 2026 06:09:27 GMT

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

AFE4404: 是否可以提供额头部位的血氧算法

yb bai — Tue, 21 Jul 2026 06:01:20 GMT

Part Number: AFE4404

AFE882H1: VREFIO输出

xu xia — Wed, 15 Jul 2026 02:10:38 GMT

Part Number: AFE882H1

我在测试时发现，当IOVDD未通电时，VREFIO无输出，VDD电压1.7V。IOVDD上电，reset引脚拉高后，VREFIO正常输出，VDD电压1.8V。

数字引脚reset会影响VREFIO的输出，这种情况是正常的吗？

RE: AFE882H1: VREFIO输出

Vivian Gao — Tue, 21 Jul 2026 02:59:59 GMT

测试也要建立在电源稳定的情况下，IOVDD不上电，可以理解为不完整的上电状态。

手册里面虽然没有明确写明上电时序，但是在电气参数或者图表的测试条件中，电源都是正常给到之后再做的。

RE: AFE882H1: VREFIO输出

xu xia — Tue, 21 Jul 2026 00:53:44 GMT

你好，似乎是电源的问题，我将IOVDD断开，REF_EN为高电平，此时VREFIO无输出，alarm引脚为低电平。连接IOVDD电源后，VREFIO可以正常输出电压。

RE: ADS1299EEGFE-PDK: ADS1299 共模抑制比无法满足手册要求110dB，且工频噪声有200uV.

? ? — Mon, 20 Jul 2026 12:19:33 GMT

您好，目前布局是按照手册推荐布局进行四层板布局，不同点在于：顶层全部为模拟层，仅电源，INXP，SRB1和BIAS相关信号走线及阻容器件，未进行铺铜处理；第二层是完整的AGND平面；第三层是电源层，使用AGND属性铜皮填充空白区域；底层是SPI相关走线，使用AGND属性铜皮填充空白区域；附件是顶层布局情况，麻烦您给一些建议。

第二点是：在测试过程中发现，按照

ADS1299EEG-FE EEG Front-End Performance Demonstration Kit (Rev. B)

推荐原理图绘制的，但是在测试过程中发现INXP 前端滤波器件和推荐电路存在差异，原理图电路时INXP滤波电路先经过RC电路（先经过串联电阻，在经过对AGND的电容），发现噪声并不是特别好。但是将电路改成（先经过对AGND的电容，再经过串联电阻），噪声能够降低到很低。为什么会有这么大差别呢？

ADS1299EEGFE-PDK: ADS1299 共模抑制比无法满足手册要求110dB，且工频噪声有200uV.

? ? — Tue, 14 Jul 2026 10:13:29 GMT

Part Number: ADS1299EEGFE-PDK

最近也在调试ADS1299 这款芯片，（测试环境如下：ADS1299能够正常工作，根据手册和开发板参考设计进行设计，并且启用了BIAS功能。所有通道的差分负输入都连接到了SRB1，SRB1作为统一参考位点连接到右侧耳垂。BIAS输出电极连接到左侧耳垂。PGA增益都为1。正电源为2.5V，负电源为-2.5V。其余硬件电路按照

ADS1299EEG-FE EEG Front-End Performance Demonstration Kit (Rev. B)

手册进行设计的50-51页）

问题1：在测试过程中，仅开启IN1P通道，（其他通道设置为001=输入短路）配置寄存器将IN1P和SRB1内部短接，测得短接噪声约为5uV，但当外部短接测试，噪声将达到20uV~100uV左右，同时通道2、3、4、5、6、7、8 测试过程中用手触摸，也会影响测试波形；

问题2：在测试过程中，仅开启IN1P通道（其他通道设置为001=输入短路），工频噪声很大，且共模抑制比仅有85dB，

原理图参考

ADS1299EEG-FE EEG Front-End Performance Demonstration Kit (Rev. B)

文件进行设计和布局。请协助解决，谢谢，

DAC39RF10: dac需要直流输出，看手册碰到一些问题

xiao weihua — Fri, 17 Jul 2026 08:09:06 GMT

Part Number: DAC39RF10

我打算使用TRF1305放大器接到DAC的输出，实现差分转单端输出。

数据手册给出了DAC core里的Ibias、Ifs等电流的表达式，后面又给了一个静态电流的表达式，要求静态电流为满幅电流的0.235倍，这是需要我们配置完满幅电流后，再修改寄存器配置Ibias电流为静态电流吗？0.235的关系是从哪里来的，必须要满足吗？

RE: DAC39RF10: dac需要直流输出，看手册碰到一些问题

Alice — Mon, 20 Jul 2026 04:10:15 GMT

您好，

如图所示，IFSSWITCH的公式中已包含了确定Ibias的参数（COARSE_CUR_A or COARSE_CUR_B， CUR_2X_EN)，然后根据公式1可计算出Ibias。

0.235是芯片的固定性能决定的，您只需设置IFSSWITCH即可。

DAC39RF10, DAC39RFS10 10.24, 20.48-GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204B, C Interface datasheet (Rev. B)

RE: DAC39RF10: dac需要直流输出，看手册碰到一些问题

Lydia — Sun, 19 Jul 2026 23:31:34 GMT

您好，已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

TX73H32: Questions about the datasheet

sifeng lian — Thu, 16 Jul 2026 11:02:18 GMT

Part Number: TX73H32

P116.Section 9.4, item 7 of the technical manual（sbasb47a_TX73H32_Datasheet） says the wake-up time is 200us, but Figure 9-3 below says 200ms. Which one is correct?

RE: TX73H32: Questions about the datasheet

Lydia — Fri, 17 Jul 2026 07:54:53 GMT

Hi,

As this device is covered under NDA,

please drop a mail to support_us_afe_tx@list.ti.com explaining the details of the intended applications, to get further support.

RE: TX7364: 哪可以提供TX7364和AFE5832的数据手册？

Taylor — Fri, 17 Jul 2026 06:53:02 GMT

这两款的完整数据手册都需要申请，请点击下面链接申请：

https://www.ti.com/drr/opn/TX7364-DESIGN

https://www.ti.com/drr/opn/AFE5832-DESIGN

由于我们这里并没有审批权限，如遇申请未通过，请联系客服部门说明具体情况

www.ti.com.cn/.../customer-support.html

TX7364: 哪可以提供TX7364和AFE5832的数据手册？

Yuan CL — Fri, 17 Jul 2026 06:26:58 GMT

Part Number: TX7364

您好！

我们设计新产品，使用TX7364+AFE5832器件,哪里可以提供数据手册？

谢谢

CL Yuan

RE: TX7364: 哪可以提供TX7364和AFE5832的数据手册？

Taylor — Fri, 17 Jul 2026 06:27:43 GMT

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: TSW14J57EVM: Alternative Recommendation for TSW14J57EVM

Lydia — Fri, 17 Jul 2026 05:46:50 GMT

Hi,

Please refer to this thread:TRF1208-ADC12DJ5200RFEVM: Alternative capture board of TSW14J57EVM - Data converters forum - Data converters - TI E2E support forums

TSW14J57EVM: Alternative Recommendation for TSW14J57EVM

國文陳 — Fri, 17 Jul 2026 01:34:04 GMT

Part Number: TSW14J57EVM

Hi TI Team,

I reviewed the ADC12DJ5200SEEVM user guide and noticed that the evaluation module requires the TSW14J57EVM for data capture and evaluation.

However, it appears that the TSW14J57EVM has been discontinued, and we are currently unable to procure this product.We also find the product TSW14J58EVM TSW14J59EVM seems also been discontinued

Could you please recommend an alternative evaluation or data capture platform that is compatible with the ADC12DJ5200SEEVM?

We would appreciate any suggestions regarding:

Direct replacement products for TSW14J57EVM
Newer TI evaluation platforms

RE: ADS1299EEGFE-PDK: ADS1299 共模抑制比无法满足手册要求110dB，且工频噪声有200uV.

Eirwen — Fri, 17 Jul 2026 02:48:37 GMT

当仅使用IN1时，需要把未使用的模拟输入直接接到 AVDD 上。

数据表中12.1 Layout Guidelines有很多注意事项，有助于减少噪声。

RE: TX73H32: Questions about the datasheet，TX73H32

Lydia — Thu, 16 Jul 2026 23:15:48 GMT

Hi,

Thank you for reaching out to us and showing interest in our parts. As this device is covered under NDA, please drop a mail to support_us_afe_tx@list.ti.com explaining the details of the intended applications, to get further support.

TX73H32: Questions about the datasheet，TX73H32

sifeng lian — Thu, 16 Jul 2026 10:51:22 GMT

Part Number: TX73H32

P116.Section 9.4, item 7 of the technical manual（sbasb47a_TX73H32_Datasheet） says the wake-up time is 200us, but Figure 9-3 below says 200ms. Which one is correct?

RE: TX73H32: Questions about the datasheet，TX73H32

Lydia — Thu, 16 Jul 2026 22:53:24 GMT

Hello, we have received your case and the investigation will take some time. Thank you for your patience.

RE: AFE882H1: VREFIO输出

Vivian Gao — Thu, 16 Jul 2026 06:16:11 GMT

VREFIO受如下内容的影响，您需要测其他引脚在reset时候是什么情况

DAC8551: DAC8551 bipolar offset output increases system noise when connected to a difference amplifier

Maoliang Jian — Wed, 08 Jul 2026 08:12:28 GMT

Part Number: DAC8551

Hello everyone,

I am designing a high-precision analog front-end for measuring small voltage variations. The system includes an instrumentation amplifier, a DAC-based dynamic offset cancellation stage, a fixed-gain difference amplifier, a programmable gain stage, and a high-speed SAR ADC.

The issue I am seeing is that once the DAC offset path is connected to the fixed-gain difference amplifier, the input-referred RMS noise increases from a few µV to about 30–40 µV RMS. More interestingly, even when the inputs of the DAC offset amplifier are both tied to AGND, so that its output should ideally be 0 V, the noise is still almost the same as when the full DAC offset circuit is connected.

1. System structure

The measured signal first goes through an instrumentation amplifier and is converted to a single-ended signal. It then enters a fixed-gain difference amplifier, which implements:

Vout = 5 × (Vsignal - VDAC_bias)

The fixed difference amplifier currently uses a high-speed, low-noise op amp. The resistor values are:

Input resistors: 300 Ω Feedback / reference-side resistors: 1.5 kΩ Gain: 5 V/V

After this stage, there is a non-inverting PGA with gain settings:

1 / 2 / 4 / 8

Therefore, the total analog gains are:

5 / 10 / 20 / 40

All noise data below is input-referred RMS noise, calculated after dividing by the corresponding total analog gain.

2. DAC offset circuit

The DAC offset path is used to generate a bipolar offset voltage, so that the DC component of the measured signal can be subtracted before further amplification.

The offset circuit is:

2.048 V precision reference → DAC8551 reference

DAC8551 output → 34 kΩ + 470 nF RC low-pass filter → non-inverting input of offset op amp

2.048 V precision reference → 5 kΩ → inverting input of offset op amp

offset op amp output → 5 kΩ → inverting input of offset op amp

Therefore, the low-frequency transfer function is:

VDAC_bias = 2 × VDAC - 2.048 V

When the DAC output is 1.024 V, the offset amplifier output should be approximately 0 V.

I have tried both OPA189 and OPA828 as the offset amplifier, but the noise level did not change significantly. I also tried different capacitors in parallel with the 5 kΩ feedback resistor, such as 10 nF and 330 pF, but there was no fundamental improvement.

3. Test data

The following data is input-referred RMS noise in volts. Each row corresponds to PGA gain settings:

1 / 2 / 4 / 8

3.1 Full circuit connected

The DAC offset output is connected normally to the fixed 5× difference amplifier.

1 MSPS:
3.95E-05   3.71E-05   3.39E-05   3.18E-05

2 MSPS, average every 2 samples:
3.28E-05   3.20E-05   3.08E-05   2.90E-05

The input-referred noise is around 30–40 µV RMS.

3.2 DAC offset path disconnected

In this test, the DAC offset output is disconnected from the fixed difference amplifier. The original DAC offset input of the difference amplifier is tied directly to AGND. The main signal path is still connected normally.

1 MSPS:
6.46E-06   6.15E-06   4.76E-06   3.92E-06

2 MSPS, average every 2 samples:
4.77E-07   1.46E-06   2.13E-06   2.17E-06

In this condition, the main signal chain can reach a few µV RMS input-referred noise.

3.3 Offset amplifier inputs tied to AGND, but output still connected

In this test:

The non-inverting input of the offset amplifier is tied to AGND.

The 5 kΩ resistor that normally connects the 2.048 V reference to the inverting input is also tied to AGND instead of 2.048 V.

The 5 kΩ feedback resistor remains connected.

The offset amplifier output is still connected to the fixed 5× difference amplifier.

In this condition, the offset amplifier should ideally output 0 V.

However, the measured noise is:

1 MSPS:
3.88E-05   3.94E-05   3.52E-05   3.47E-05

2 MSPS, average every 2 samples:
3.41E-05   3.38E-05   3.31E-05   3.08E-05

This result is almost the same as when the full DAC offset circuit is connected.

Therefore, the noise does not seem to come mainly from the DAC8551 output code itself, nor only from the 2.048 V reference. Even when the offset amplifier inputs are both grounded and the expected output is 0 V, connecting this active 0 V output to the difference amplifier still brings the noise back to the 30–40 µV RMS level.

4. Other tests already performed

To rule out cable effects, I used a shielded cable. The shield is connected to AGND only at the acquisition board side, while the far end of the shield is left floating. The far-end Sense+ and Sense− wires are shorted together.

I also tried removing the cable and shorting Sense+ and Sense− directly at the input connector of the board. As long as the DAC offset amplifier output is connected to the fixed difference amplifier, the noise remains much higher than when the DAC offset path is disconnected.

I also tried splitting the original 300 Ω DAC-bias input resistor of the fixed difference amplifier into:

DAC offset op amp output → 100 Ω → middle node → 200 Ω → difference amplifier input

Then I added a capacitor from the middle node to AGND. However, the noise increased by about 10–20 µV. After removing this capacitor, the noise returned to the original 30–40 µV RMS level.

So this middle-node capacitor did not help. It may have introduced AGND noise or parasitic effects from the temporary wiring.

5. Current thoughts

At this point, I suspect the issue may be related to one or more of the following:

The DAC offset amplifier output, used as an “active 0 V” or active bias source, is not as quiet as a direct AGND connection.
The offset amplifier is driving a relatively low input resistance of 300 Ω into the difference amplifier, which may make its output noise, power-supply noise, or stability issues more visible.
When the active DAC offset source is connected to the difference amplifier, the input network or layout parasitics of the difference amplifier may cause noise peaking.
The 5 kΩ / 5 kΩ feedback network of the offset amplifier may have too high an impedance, making the inverting node sensitive to parasitic coupling and noise.

6. Planned modification

I am planning to reduce the two 5 kΩ resistors in the DAC offset amplifier to 2.2 kΩ:

Feedback resistor = 2.2 kΩ
Reference input resistor = 2.2 kΩ
Feedback capacitor ≈ 10 nF

This should still keep the same transfer function:

VDAC_bias = 2 × VDAC - 2.048 V

but with a lower impedance at the inverting node, which may reduce thermal noise and sensitivity to parasitic coupling.

7. Questions

In this type of circuit, can the noise increase from a few µV RMS to 30–40 µV RMS simply because an active DAC offset source is connected to the difference amplifier?
Could the 300 Ω DAC-bias input resistor of the difference amplifier be too low for the DAC offset amplifier, causing output noise, supply noise, or stability issues to be injected into the following stage?
For this kind of structure:

Vout = 5 × (Vsignal - VDAC_bias)

should the DAC offset source be designed as a lower-output-impedance and lower-bandwidth precision bias source?

Is reducing the offset amplifier resistor pair from 5 kΩ / 5 kΩ to 2.2 kΩ / 2.2 kΩ a reasonable direction for reducing noise and parasitic sensitivity?

8. Summary

The main point that confuses me is:

When the DAC offset amplifier inputs are both tied to AGND, its output should ideally be 0 V. However, as soon as this output is connected to the fixed 5× difference amplifier, the system noise becomes almost the same as when the full DAC offset circuit is connected.

Does this behavior look more like a noise / stability problem of the active offset source itself, or more like an issue with the input network / layout of the following difference amplifier?

Thank you.