数据转换器论坛 - 最近的话题

DAC37J82EVM: DAC37J82: Unexpectedly Long Trigger-to-Analog-Output Latency in JESD204B Subclass 1 Mode

ShiHao wang — Wed, 22 Jul 2026 06:57:34 GMT

Part Number: DAC37J82EVM

Hello,

We are evaluating the deterministic latency of a DAC37J82 operating with
a JESD204B Subclass 1 interface. We measure approximately 250 to 260 ns
from an FPGA waveform-change trigger to the observable change at the DAC
analog output. This is significantly longer than we expected from the
known FPGA, GTY, RBD and documented DAC pipeline contributions.

Our current JESD204B configuration is:

- Device: DAC37J82
- Subclass: 1
- L = 4
- M = 2
- F = 1
- S = 1
- K = 32
- N = N' = 16
- DAC sample clock / DACCLK: 983.04 MHz
- JESD lane rate: approximately 9.8304 Gbps
- RBD = 22 frame cycles
- Interpolation disabled
- PAP disabled
- Mixer, QMC and inverse-sinc functions disabled

The FPGA continuously transmits valid JESD204B sample data. The trigger
only changes the generated sample waveform; it does not reset or
reinitialize the JESD link. SYNC remains asserted during the normal
latency measurement.

Our measured latency breakdown is approximately:

1. Trigger to waveform-generator data change:
4.1 ns

2. Trigger to the GTY TX parallel-data interface:
28.5 ns

3. Trigger through a GTY near-end PMA loopback to the GTY RX parallel
interface:
82 to 90 ns

4. Trigger to the DAC analog-output waveform change:
approximately 250 to 260 ns

Changing RBD from 22 to 26 increases the total analog-output latency by
approximately 4 ns. This agrees with four frame periods at 983.04 MHz:

4 / 983.04 MHz = approximately 4.07 ns

Therefore, the RBD setting appears to be active and behaves as expected.
However, the overall trigger-to-analog-output latency remains around
250 ns.

As an additional diagnostic, we tested the SIFDAC path by changing the
SIFDAC data through the serial interface. The approximate response times
were:

- DACCLK = 983.04 MHz: approximately 151 to 153 ns
- DACCLK = 491.52 MHz: approximately 300 ns

The response time approximately doubles when DACCLK is halved, suggesting
that a large portion of this response is determined by a DACCLK-cycle-
based synchronization or digital pipeline.

We also tested the PAP function at 491.52 MHz:

- PAP disabled: approximately 300 ns
- PAP enabled: approximately 440 ns
- Increment: approximately 140 ns

This increment corresponds to approximately 69 DACCLK cycles and is close
to the documented PAP latency of 68 DACCLK cycles. This gives us
confidence that our measurement can identify DACCLK-cycle-based latency
changes.

We understand that the SIFDAC path may include serial-register update and
clock-domain synchronization latency, and that it may not follow exactly
the same path as normal JESD204B sample data. We therefore do not assume
that the measured SIFDAC latency directly represents the JESD receive
latency. We are using it only as a diagnostic indication that a relatively
long clocked path may exist inside the DAC.

Could you please clarify the following points?

1. What is the expected latency from the DAC37J82 JESD serial input to the
analog output for the configuration listed above?

2. Which internal blocks contribute to this latency, and how many DACCLK
or frame-clock cycles does each block contribute?

3. Is there an elastic buffer, JESD receive FIFO, synchronization stage or
common digital pipeline after the SerDes/8b10b block that contributes
significant latency?

4. Can this FIFO or digital pipeline be bypassed or configured for minimum
latency while retaining JESD204B Subclass 1 deterministic latency?

5. Does the documented 11-DACCLK-cycle latency apply to this exact
configuration with interpolation, PAP, mixer, QMC and inverse-sinc
disabled? If so, from which internal reference point to which output
point are those 11 cycles defined?

6. Which internal blocks are shared by the SIFDAC path and the normal
JESD204B sample-data path?

7. Does a SIFDAC response of approximately 150 DACCLK cycles indicate a
normal register-update synchronization delay, or does it indicate the
latency of a shared DAC digital-output pipeline?

8. Is there a recommended register configuration or test method for
measuring the minimum deterministic JESD-input-to-analog-output latency
of the DAC37J82?

Our primary concern is the approximately 250 to 260 ns total
trigger-to-analog-output latency. The SIFDAC measurement is only an
additional observation that may help identify where the unexpected delay
is introduced.

K32.txt

Thank you.

RE: DAC37J82EVM: DAC37J82: Unexpectedly Long Trigger-to-Analog-Output Latency in JESD204B Subclass 1 Mode

Daniel — Wed, 22 Jul 2026 07:10:38 GMT

您好

关于您所关心造成的原因以及相关可能性，官方有以下相关指导文档请您参考进行排查。

https://www.ti.com/lit/an/sbaa045/sbaa045.pdf?ts=1784703979468&ref_url=https%253A%252F%252Fwww.ti.com.cn%252Fproduct%252Fcn%252FDAC37J82

https://www.ti.com.cn/cn/lit/an/slaa523a/slaa523a.pdf?ts=1784703720872&ref_url=https%253A%252F%252Fwww.ti.com.cn%252Fproduct%252Fcn%252FDAC37J82

https://www.ti.com.cn/cn/lit/an/slaa696/slaa696.pdf?ts=1784703731061&ref_url=https%253A%252F%252Fwww.ti.com.cn%252Fproduct%252Fcn%252FDAC37J82

以下是相关帖子以及相关处理方法。

DAC37J82：配置错误：alarm_sysref_err - 数据转换器论坛 - 数据转换器 - TI E2E 支持论坛

DAC37J82：使用AD9528的Xilinx FPGA和DAC37J82的确定性延迟JESD204B - 数据转换器论坛 - 数据转换器 - TI E2E支持论坛

RE: AFE4404: 是否可以提供额头部位的血氧算法

Daniel — Tue, 21 Jul 2026 06:14:18 GMT

您好

AFE4404EVM：转换为PPG和SPO2信号 - 数据转换器论坛 - 数据转换器 - TI E2E支持论坛

(7) AFE44S30: 关于LED电流范围的咨询 - 数据转换器论坛 - 数据转换器 - E2E™ 设计支持

请您参考这两个帖子说明。

AFE4404: 是否可以提供额头部位的血氧算法

yb bai — Tue, 21 Jul 2026 06:00:01 GMT

Part Number: AFE4404

我用贵司的血氧模拟前端AFE4404+SFH7050做血氧模块,用于测试人体额头部位的脉率和血氧,用的参考代码是TI官网下载的:AFE4404EVM_FW_SRC_v1.5_Release,该参考代码中的hrm.c 心率算法测试额头部位的心率比较准确,贵司是否可以提供对应的血氧算法？多谢支持

AFE4404: 是否可以提供额头部位的血氧算法

yb bai — Tue, 21 Jul 2026 06:01:20 GMT

Part Number: AFE4404

RE: AFE4404: 是否可以提供额头部位的血氧算法

Eirwen — Tue, 21 Jul 2026 06:09:27 GMT

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

AFE882H1: VREFIO输出

xu xia — Wed, 15 Jul 2026 02:10:38 GMT

Part Number: AFE882H1

我在测试时发现，当IOVDD未通电时，VREFIO无输出，VDD电压1.7V。IOVDD上电，reset引脚拉高后，VREFIO正常输出，VDD电压1.8V。

数字引脚reset会影响VREFIO的输出，这种情况是正常的吗？

RE: AFE882H1: VREFIO输出

Vivian Gao — Tue, 21 Jul 2026 02:59:59 GMT

测试也要建立在电源稳定的情况下，IOVDD不上电，可以理解为不完整的上电状态。

手册里面虽然没有明确写明上电时序，但是在电气参数或者图表的测试条件中，电源都是正常给到之后再做的。

RE: AFE882H1: VREFIO输出

xu xia — Tue, 21 Jul 2026 00:53:44 GMT

你好，似乎是电源的问题，我将IOVDD断开，REF_EN为高电平，此时VREFIO无输出，alarm引脚为低电平。连接IOVDD电源后，VREFIO可以正常输出电压。

RE: ADS1299EEGFE-PDK: ADS1299 共模抑制比无法满足手册要求110dB，且工频噪声有200uV.

? ? — Mon, 20 Jul 2026 12:19:33 GMT

您好，目前布局是按照手册推荐布局进行四层板布局，不同点在于：顶层全部为模拟层，仅电源，INXP，SRB1和BIAS相关信号走线及阻容器件，未进行铺铜处理；第二层是完整的AGND平面；第三层是电源层，使用AGND属性铜皮填充空白区域；底层是SPI相关走线，使用AGND属性铜皮填充空白区域；附件是顶层布局情况，麻烦您给一些建议。

第二点是：在测试过程中发现，按照

ADS1299EEG-FE EEG Front-End Performance Demonstration Kit (Rev. B)

推荐原理图绘制的，但是在测试过程中发现INXP 前端滤波器件和推荐电路存在差异，原理图电路时INXP滤波电路先经过RC电路（先经过串联电阻，在经过对AGND的电容），发现噪声并不是特别好。但是将电路改成（先经过对AGND的电容，再经过串联电阻），噪声能够降低到很低。为什么会有这么大差别呢？

ADS1299EEGFE-PDK: ADS1299 共模抑制比无法满足手册要求110dB，且工频噪声有200uV.

? ? — Tue, 14 Jul 2026 10:13:29 GMT

Part Number: ADS1299EEGFE-PDK

最近也在调试ADS1299 这款芯片，（测试环境如下：ADS1299能够正常工作，根据手册和开发板参考设计进行设计，并且启用了BIAS功能。所有通道的差分负输入都连接到了SRB1，SRB1作为统一参考位点连接到右侧耳垂。BIAS输出电极连接到左侧耳垂。PGA增益都为1。正电源为2.5V，负电源为-2.5V。其余硬件电路按照

ADS1299EEG-FE EEG Front-End Performance Demonstration Kit (Rev. B)

手册进行设计的50-51页）

问题1：在测试过程中，仅开启IN1P通道，（其他通道设置为001=输入短路）配置寄存器将IN1P和SRB1内部短接，测得短接噪声约为5uV，但当外部短接测试，噪声将达到20uV~100uV左右，同时通道2、3、4、5、6、7、8 测试过程中用手触摸，也会影响测试波形；

问题2：在测试过程中，仅开启IN1P通道（其他通道设置为001=输入短路），工频噪声很大，且共模抑制比仅有85dB，

原理图参考

ADS1299EEG-FE EEG Front-End Performance Demonstration Kit (Rev. B)

文件进行设计和布局。请协助解决，谢谢，

DAC39RF10: dac需要直流输出，看手册碰到一些问题

xiao weihua — Fri, 17 Jul 2026 08:09:06 GMT

Part Number: DAC39RF10

我打算使用TRF1305放大器接到DAC的输出，实现差分转单端输出。

数据手册给出了DAC core里的Ibias、Ifs等电流的表达式，后面又给了一个静态电流的表达式，要求静态电流为满幅电流的0.235倍，这是需要我们配置完满幅电流后，再修改寄存器配置Ibias电流为静态电流吗？0.235的关系是从哪里来的，必须要满足吗？

RE: DAC39RF10: dac需要直流输出，看手册碰到一些问题

Alice — Mon, 20 Jul 2026 04:10:15 GMT

您好，

如图所示，IFSSWITCH的公式中已包含了确定Ibias的参数（COARSE_CUR_A or COARSE_CUR_B， CUR_2X_EN)，然后根据公式1可计算出Ibias。

0.235是芯片的固定性能决定的，您只需设置IFSSWITCH即可。

DAC39RF10, DAC39RFS10 10.24, 20.48-GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204B, C Interface datasheet (Rev. B)

RE: DAC39RF10: dac需要直流输出，看手册碰到一些问题

Lydia — Sun, 19 Jul 2026 23:31:34 GMT

您好，已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

TX73H32: Questions about the datasheet

sifeng lian — Thu, 16 Jul 2026 11:02:18 GMT

Part Number: TX73H32

P116.Section 9.4, item 7 of the technical manual（sbasb47a_TX73H32_Datasheet） says the wake-up time is 200us, but Figure 9-3 below says 200ms. Which one is correct?

RE: TX73H32: Questions about the datasheet

Lydia — Fri, 17 Jul 2026 07:54:53 GMT

Hi,

As this device is covered under NDA,

please drop a mail to support_us_afe_tx@list.ti.com explaining the details of the intended applications, to get further support.

RE: TX7364: 哪可以提供TX7364和AFE5832的数据手册？

Taylor — Fri, 17 Jul 2026 06:53:02 GMT

这两款的完整数据手册都需要申请，请点击下面链接申请：

https://www.ti.com/drr/opn/TX7364-DESIGN

https://www.ti.com/drr/opn/AFE5832-DESIGN

由于我们这里并没有审批权限，如遇申请未通过，请联系客服部门说明具体情况

www.ti.com.cn/.../customer-support.html

TX7364: 哪可以提供TX7364和AFE5832的数据手册？

Yuan CL — Fri, 17 Jul 2026 06:26:58 GMT

Part Number: TX7364

您好！

我们设计新产品，使用TX7364+AFE5832器件,哪里可以提供数据手册？

谢谢

CL Yuan

RE: TX7364: 哪可以提供TX7364和AFE5832的数据手册？

Taylor — Fri, 17 Jul 2026 06:27:43 GMT

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

TSW14J57EVM: Alternative Recommendation for TSW14J57EVM

國文陳 — Fri, 17 Jul 2026 01:34:04 GMT

Part Number: TSW14J57EVM

Hi TI Team,

I reviewed the ADC12DJ5200SEEVM user guide and noticed that the evaluation module requires the TSW14J57EVM for data capture and evaluation.

However, it appears that the TSW14J57EVM has been discontinued, and we are currently unable to procure this product.We also find the product TSW14J58EVM TSW14J59EVM seems also been discontinued

Could you please recommend an alternative evaluation or data capture platform that is compatible with the ADC12DJ5200SEEVM?

We would appreciate any suggestions regarding:

Direct replacement products for TSW14J57EVM
Newer TI evaluation platforms

RE: TSW14J57EVM: Alternative Recommendation for TSW14J57EVM

Lydia — Fri, 17 Jul 2026 05:46:50 GMT

Hi,

Please refer to this thread:TRF1208-ADC12DJ5200RFEVM: Alternative capture board of TSW14J57EVM - Data converters forum - Data converters - TI E2E support forums

RE: ADS1299EEGFE-PDK: ADS1299 共模抑制比无法满足手册要求110dB，且工频噪声有200uV.

Eirwen — Fri, 17 Jul 2026 02:48:37 GMT

当仅使用IN1时，需要把未使用的模拟输入直接接到 AVDD 上。

数据表中12.1 Layout Guidelines有很多注意事项，有助于减少噪声。

RE: TX73H32: Questions about the datasheet，TX73H32

Lydia — Thu, 16 Jul 2026 23:15:48 GMT

Hi,

Thank you for reaching out to us and showing interest in our parts. As this device is covered under NDA, please drop a mail to support_us_afe_tx@list.ti.com explaining the details of the intended applications, to get further support.

TX73H32: Questions about the datasheet，TX73H32

sifeng lian — Thu, 16 Jul 2026 10:51:22 GMT

Part Number: TX73H32

P116.Section 9.4, item 7 of the technical manual（sbasb47a_TX73H32_Datasheet） says the wake-up time is 200us, but Figure 9-3 below says 200ms. Which one is correct?

RE: TX73H32: Questions about the datasheet，TX73H32

Lydia — Thu, 16 Jul 2026 22:53:24 GMT

Hello, we have received your case and the investigation will take some time. Thank you for your patience.