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DLP4100 FPGA VHDL代码移植

Other Parts Discussed in Thread: DLPC410, DLP9500, DLPR410

您好,

        由于项目中需要在fpga中进行一些关键运算,原来的V5改为K7,通讯接口也有USB2该为10Gmac,在研究原来的VHDL代码后我们认为对于DMD控制部分只要用appsfpga_io模块可以满足我们的要求,只是按行输入数据,全局reset。有没有对appsfpga_io模块输入端功能时序的控制的资料?

    谢谢!

  zlwang