DLP®︎ 产品论坛 - 最近的话题

DLP472TP: DLP472TP: Clarification on 1800 lm System Brightness Limit for RGB Laser Projectors

dai mubai — Mon, 19 Oct 2026 08:34:55 GMT

Part Number: DLP472TP

您好，TI DLP 技术支持工程师：

我正在研究德州仪器 DLP472TP（0.47 英寸 4K UHD DMD）在高亮度 RGB 三色激光投影系统中的应用，希望咨询该芯片的系统亮度规格、光学工作条件以及长期可靠性问题。

查阅 TI 官方技术资料后，我注意到以下信息：

DLP472TP 官方产品页面将 System Brightness (max) 标注为 1800 lm。

www.ti.com/.../DLP472TP
TI 发布的激光电视技术文章（SBAA715）中，该型号的系统亮度指标为 2000 lm。
TI 的 DLP 系统选型技术资料中，DLP472TP 的 Suggested Brightness（建议亮度）约为 1600 lm。
DLP472TP 数据手册（DLPS247）还规定了可见光入射功率密度、蓝光入射功率密度、微镜阵列温度等推荐工作条件。

但目前市场上已有采用 DLP472TP、搭配 RGB 三色激光光源的消费级投影产品，其标称整机输出亮度超过 4000 CVIA 流明。

我理解投影系统输出的流明数与 DMD 表面的实际入射光功率并不是同一个物理量，不能直接根据整机亮度判断 DMD 是否超出推荐工作条件。

因此，希望向 TI 技术工程师确认以下问题：

问题一：1800 lm 系统亮度的具体含义

DLP472TP 产品页面中的 System Brightness (max) = 1800 lm，究竟属于：

DMD 在正常工作条件下不应超过的系统输出亮度上限；
还是基于典型光源、光学效率及系统设计条件给出的参考性设计指标？

另外，不同官方技术资料中出现 1600 lm、1800 lm、2000 lm 的原因是什么？是否对应不同的设计假设或应用场景？

问题二：高亮度 RGB 三色激光应用的可行性

假设一套 RGB 三色激光投影系统能够确保 DLP472TP 的：

可见光入射功率密度；
各蓝光波段的入射功率密度；
微镜阵列工作温度；
其他 Recommended Operating Conditions（推荐工作条件）；

均满足 DLPS247 数据手册的相关规定。

那么，是否允许使用 DLP472TP 设计实际整机输出亮度超过 4000 lm 的投影系统？

或者说，除了数据手册中的光功率密度与温度限制外，是否还存在必须遵守的独立系统输出亮度上限？

问题三：亮度指标的测试与计算口径

TI 官方所标注的 1800 lm，是基于什么样的测试方法、参考光源和光学系统条件得到的？

它是否可以与按照 ANSI 或 CVIA 测试方法得到的投影仪整机亮度直接进行数值比较？

对于高效率 RGB 三色激光系统，是否需要考虑不同的光谱分布、光学效率或测试条件？

问题四：长期可靠性和寿命限制

如果实际 DMD 的入射光功率密度、蓝光功率密度、微镜阵列温度等全部满足 TI 数据手册的推荐工作条件，但整机输出亮度明显高于产品页面中的 1800 lm，那么：

是否仍属于 TI 推荐或支持的正常应用范围？
是否存在额外的长期可靠性或寿命风险？
是否需要进行额外的光学、热设计或可靠性验证？

本次咨询的核心目的，是确认 DLP472TP 官方 1800 lm 系统亮度指标的工程含义，以及在满足芯片所有推荐工作条件的前提下，能否用于超过 4000 lm 的 RGB 三色激光投影系统。

本次问题仅涉及 DLP472TP 的一般技术规格和应用边界，不要求提供任何整机厂商的保密设计数据。

感谢 TI 技术工程师的解答！

DLPLCR65EVM: 请问DLPLCR65EVM参考设计中的22uH电感是否合理呢？

meng wen — Wed, 14 Oct 2026 07:14:20 GMT

Part Number: DLPLCR65EVM

上图网页下的设计文件【2511979B_LCR6500_DMDBOARD_P65_1080P_S600_CSTACK_FLEX_CONN.pdf】中位号为U1的TPS65145芯片的L1采用的是22uH的电感（参考设计如下图所示），而TPS65145芯片手册中推荐的电感感值为3.3uH-6.8uH,请问为什么参考设计中的22uH的电感呢，是基于纹波考虑还是什么呢？

DLPC3436: 使用DLPC3436做投影仪选型HDMI转RGB芯片要求

ZHAO BO — Tue, 29 Sep 2026 09:52:17 GMT

Part Number: DLPC3436

您好，

我们使用DLPC3436+DLPA3000这套方案想实现投影仪的功能，看DLPC3436的参考设计要在HDMI转RGB信号后连接FPGA，我们想把HDMI转RGB的信号直接给DLPC3436，不知道是否可行，如果可行的话可以推荐一下TI测试过的相关HDMI转RGB的芯片吗？还有RGB到DLPC3436转视频信号的固件是否可以提供下；

感谢！

DLPC3478: Request for DLPC3478 v9.2.0 firmware supporting one blue LED on DLPA3005 CH3

Hongkun Li — Thu, 24 Sep 2026 06:51:37 GMT

Part Number: DLPC3478

Hi TI DLP team,

We are developing a projector using DLPC3478, DLPA3005 and DLP3010LC. Our design has one blue LED connected to the DLPA3005 CH3 LED channel. No red or green LEDs are installed.

Could you provide a v9.2.0 firmware image configured to use only CH3 for illumination, including display mode and internal and external light control pattern modes? The firmware should not require LEDs on the unused channels during startup or operation.

Our I²C address is 0x36, and the LED current sense resistor is 25 mΩ. Please advise what DMD pin mapping, LED specifications, or other hardware information you need to generate the correct image. We can share the schematic privately.

If a ready-to-flash image is unavailable, could you provide the appropriate DLP Composer project and configuration guidance?

Thank you.

DLPC3479: DLPC3479固件参数文档

zhao yue — Mon, 07 Sep 2026 08:48:33 GMT

Part Number: DLPC3479

希望获得DLPC3479v7.0.1版本的固件参数文档，请有的人发我下

DLPDLCR2000EVM: 该产品投影影响闪烁不稳定

Vivian Sun — Wed, 19 Aug 2026 12:41:12 GMT

Part Number: DLPDLCR2000EVM

该产品投影影响闪烁不稳定，请问是什么原因？

DLPC230-Q1: Request for DLP5533A-Q1 + DLPC230-Q1 + TPS99001-Q1 Automotive Headlight Development Resources

Huang San — Mon, 17 Aug 2026 02:02:39 GMT

Part Number: DLPC230-Q1

Hello,

I am a graduate student at a university and am currently conducting academic research on an automotive ADB (Adaptive Driving Beam) headlight system based on DLP5533A-Q1 + DLPC230-Q1 + TPS99001-Q1. The project is for university research and educational purposes only.

I have already reviewed the publicly available TI resources, including the DLP5533A-Q1, DLPC230-Q1 and TPS99001-Q1 datasheets, the DLPC230 Programmer's Guide, DLPC230 Control Program Lite, and the related Headlight reference resources in TI Resource Explorer.

To complete the bring-up, Flash image generation and programming of our custom hardware, I would like to request access to the following resources:

DLP Composer for Automotive
DLP Composer for Automotive Project Files
Reference project/configuration files for DLP5533A-Q1 + DLPC230-Q1 + TPS99001-Q1 Headlight
The corresponding DMD Configuration, Sequencer, TPS99001 Configuration, and recommended DLPC23x software/firmware release

If a dedicated DLP5533A-Q1 project is not available, I would also appreciate access to the DLP5531A-Q1 + DLPC230-Q1 + TPS99001-Q1 Headlight project, together with guidance on which configurations must be changed for DLP5533A-Q1.

These resources will be used solely for university research, learning, and experimental validation.

Thank you for your support.

DLP991U: DMD产品选型：尽可能多的像素数和尽可能高的刷新率

Lee Talen — Mon, 03 Aug 2026 06:52:34 GMT

Part Number: DLP991U

Dear TI Teams,

您好，我司想要采购DMD，需要尽可能多的像素数和尽可能高的刷新率。
我看到官网上在400-700nm波段有4K的DLP991U可供选择，请问：
1. 像素数有无更高的DMD阵列如8K？
2. 刷新率有无尽可能快的DMD如百微秒量级？(区分局部刷新率和全局刷新率)

感谢帮助

RE: DLP991U: DMD产品选型：尽可能多的像素数和尽可能高的刷新率

Taylor — Mon, 03 Aug 2026 07:06:16 GMT

400-700nm的只有下面的13款，

Visible (420 to 700nm) DMDs product selection | TI.com

4K的只有DLP991U，没有更高的了。

刷新率有更高的，DLP9000X，DLP9500，DLP7000

RE: DLP991U: DMD产品选型：尽可能多的像素数和尽可能高的刷新率

Taylor — Mon, 03 Aug 2026 07:03:12 GMT

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: DLPC231S-Q1: DLPC231S+TPS99002S参考设计器件选型

FRANK1 — Mon, 03 Aug 2026 06:26:41 GMT

你好，这个评估板的电路图或BOM没体现NTC的型号的话，我们也获取不到这个信息。可能是另一侧的设计资源

DLPC231S-Q1: DLPC231S+TPS99002S参考设计器件选型

ryan zeng — Fri, 31 Jul 2026 07:52:13 GMT

Part Number: DLPC231S-Q1

Hello Teams，

在参考设计DLP121E2_SCH_20260311.pdf 中，TPS9900S有使用NTC进行温度采集反馈，但是在图纸未体现NTC电阻及其型号，能否告知接插件另一端使用的NTC电阻的完整型号呢？

谢谢！

RE: DLPC231S-Q1: DLPC231S+TPS99002S参考设计器件选型

FRANK1 — Fri, 31 Jul 2026 08:03:57 GMT

感谢您对TI产品的关注！
关于你的咨询，我们正在确认您的问题，感谢您的耐心等待。

DLPC231S-Q1: DLPC231S+TPS99002S参考设计器件选型

ryan zeng — Fri, 31 Jul 2026 07:55:55 GMT

Part Number: DLPC231S-Q1

Hello Teams，

谢谢！

DLPC350: I'm not quite clear about the meanings of different trigger modes in the pattern mode of the DLPC350. I would like to seek your advice on this.

yongning chen — Thu, 30 Jul 2026 14:09:50 GMT

Part Number: DLPC350

Dear TI Technical Expert!
In the pattern mode of dlpc350, the trigger modes include trigger mode 0, trigger mode 1, and trigger mode 2.
We are engaged in industrial-grade 3D scanning applications. The requirement is: to reliably update and project the pattern through an external control signal, and achieve precise coordination with the camera's photography, so as to achieve the most optimized photography and acquisition of the projected pattern.
Under such requirements, may I ask:
1. Is it better to use trigger mode 0 or trigger mode 1? Or can both modes achieve the same effect well? Why?
2. In trigger mode 0, is VSYNC considered an external trigger signal or an internal trigger signal? Is the function of VSYNC the same as TRIG_IN_1 in trigger mode 1, which is to advance to the next pattern?
For the register (I2C: 0x78), does bit[1:0] of byte0 select b00 = Internal or can it choose b01 = External positive or b10 = External negative or b11 = No input trigger (continue from previous; the pattern still has full exposure time)? What does selecting b00 = Internal specifically refer to? Is it the internal trigger, VSYNC, or the register writing? When can b11 = No input trigger be selected?
Can TRIG_OUT_1 be used to provide exposure for camera shooting?
In Table 4-2. Trigger Mode 0 Example of the document DLPU010G, is the setting of registers 0x77, 0x76, 0x78 only applicable if using images from flash memory? If not using images from flash memory, are the registers 0x77, 0x76, 0x78 not set?
Does this Table 4-2. Trigger Mode 0 Example mean that while inputting a pattern through the RGB channels, it is also possible to read the images stored in the flash memory simultaneously? How can this be done, and how is the timing of the projection of different sources of pattern patterns controlled?
If VSYNC is controlled by FPGA logic, can the pattern images be precisely controlled to change by using the rising and falling of VSYNC? Or is VSYNC like a video stream, only being a fixed period signal and not easily changing the period value? What are its limitations?
3. In trigger mode 1, is it through TRIG_IN_1 to control the replacement of the pattern, and through TRIG_IN_2 to achieve the stable display of the pattern (by projecting the pattern through DLP)?
Is the display of the pattern by DLP4500 a simultaneous flipping of all related mirrors, or a line-by-line flipping?
Due to the urgency of the project, we hope to receive a reply as soon as possible!

DLPC350: DLPU010G regarding "pattern exposure time" and "frame period" seems to have inconsistent statements. What is the relationship between them?

yongning chen — Thu, 30 Jul 2026 13:17:42 GMT

Part Number: DLPC350

Dear Technical Expert!

In the document DLPU010G – May 2013 – Revised July 2018, on page 48 of the description of the dlp0x66 register, in the external video input pattern sequence modes, the pattern exposure time must be equal to the frame period.
However, on page 61, in Table 4-2. Trigger Mode 0 Example, for register 0x66, Set the exposure and frame rate (4 bytes for each) so that the time between vsync triggers will allow three patterns to be shown For example,
for a 60-Hz vsync, the maximum exposure time is 16667 ÷ 3.
These two points are clearly in conflict. On page 48, it states that the pattern exposure time must be equal to the frame period. However, on page 61, it says that the time between vsync triggers will allow three patterns to be displayed.
Is "the frame period" here referring to the frame period of VSYNC?
We input the pattern through RGB, and select an 8-bit pattern. Then we have pattern num 1 (green 8-bit), pattern num 2 (red 8-bit), and pattern num 3 (blue 8-bit). In this case, what is the relationship between the pattern exposure time and the frame period? How should the register 0x66 be set?
If the frame period of VSYNC is 12000us, should the pattern exposure time be set to 4000us or 12000us?
How can we project 3 pattern patterns within one VSYNC frame period? These three pattern patterns correspond to the pattern num 1, pattern num 2, and pattern num 3 described in Table 2-70 of Document DLPU010G?
In the above situation, how should the registers 0x75 and 0x78 be set?

Due to the urgency of the project, we hope to receive a reply as soon as possible!

DLPC350: DLPC350: The projection design using dlpc350 + DLP4500, with pattern mode and trigger mode 0, fails the register design verification. What could be the reason?

yongning chen — Thu, 30 Jul 2026 12:37:04 GMT

Part Number: DLPC350

Dear TI expert!

We are using the DLPC350 + DLP4500 for projection design, with the following requirements:
Input graphics via RGB interface only throughout the entire process. Select trigger mode 0, VSYNC triggering, 8-bit pattern, and a total of 3 patterns. The VSYNC period is 16,080 μs.
We expect to output three patterns within one VSYNC cycle. These three patterns correspond respectively to the graphic data inputs of the RGB channels. All three patterns have the same exposure time and are triggered identically by VSYNC.
Our register settings are as follows:

#Write: Set the display mode to pattern display
W 0x34 0x69|0x80 0x01

# Write: Stop Sequence (Display if running)
W 0x34 0x65|0x80 0x00

#Write: Set the graphics display mode source to RGB
W 0x34 0x6f|0x80 0x00

#Write: Set mode number 1 - Mode
W 0x34 0x75|0x80 0x02 0x01 0x02 0x00

#Write: Set mode trigger mode - 0
W 0x34 0x70|0x80 0x00

#Write: Exposure Time
W 0x34 0x66|0x80 0xF0 0x14 0x00 0x00 0xD0 0x3E 0x00 0x00 // 0x3ED0 corresponds to 16080us, 0x14F0 corresponds to 5360us. 5360x3=16080

#Write: Set Pat LUT
W 0x34 0x77|0x80 0x02

#Write: Pat LUT offset //Set the first LUT
W 0x34 0x76|0x80 0x00

#Write: Fill Pat LUT data
W 0x34 0x78|0x80 0x00 0x28 0x00

#Write: Close email
W 0x34 0x77|0x80 0x00

#Write: Set Pat LUT
W 0x34 0x77|0x80 0x02

#Write: Pat LUT offset //Set the 2nd LUT
W 0x34 0x76|0x80 0x01

#Write: Fill Pat LUT data
W 0x34 0x78|0x80 0x00 0x18 0x00

#Write: Close email
W 0x34 0x77|0x80 0x00

#Write: Set Pat LUT
W 0x34 0x77|0x80 0x02

#Write: Pat LUT offset //Set the 3rd LUT
W 0x34 0x76|0x80 0x02

#Write: Fill Pat LUT data
W 0x34 0x78|0x80 0x00 0x48 0x00

#Write: Close email
W 0x34 0x77|0x80 0x00

#Write: Verify LUT
W 0x34 0x7D|0x80 0x00

# Add validation to complete delay or polling status

#Write: Start pattern sequence
W 0x34 0x65|0x80 0x02

After completing the above register settings, we found that the read value of register 0x7D is 0x01. What could be the cause of this issue, and how can it be resolved?

One more point to add: The video stream of the RGB channels we input to the dlpc350 is FPGA-simulated. During the DE active period, the resolution is 1280x800, the data clock of RGB is 72 MHz, and the VSYNC period = 1340x862/72 = 16080 us.

Looking forward to your reply!

DLPC350: The projection design using dlpc350 + DLP4500, with pattern mode and trigger mode 0, fails the register design verification. What could be the reason?

yongning chen — Thu, 30 Jul 2026 09:29:21 GMT

Part Number: DLPC350

Dear TI expert!

# Write: Stop Sequence (Display if running) W 0x34 0x65|0x80 0x00

#Write: Set the graphics display mode source to RGB W 0x34 0x6f|0x80 0x00

#Write: Set mode number 1 - Mode W 0x34 0x75|0x80 0x02 0x01 0x02 0x00

#Write: Set mode trigger mode - 0 W 0x34 0x70|0x80 0x00

#Write: Exposure Time
W 0x34 0x66|0x80 0xF0 0x14 0x00 0x00 0xD0 0x3E 0x00 0x00 // 0x3ED0 corresponds to 16080us, 0x14F0 corresponds to 5360us. 5360x3=16080

#Write: Set Pat LUT W 0x34 0x77|0x80 0x02

#Write: Pat LUT offset //Set the first LUT W 0x34 0x76|0x80 0x00

#Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x28 0x00

#Write: Close email W 0x34 0x77|0x80 0x00

#Write: Set Pat LUT W 0x34 0x77|0x80 0x02

#Write: Pat LUT offset //Set the 2nd LUT W 0x34 0x76|0x80 0x01

#Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x18 0x00

#Write: Close email W 0x34 0x77|0x80 0x00

#Write: Set Pat LUT W 0x34 0x77|0x80 0x02

#Write: Pat LUT offset //Set the 3rd LUT W 0x34 0x76|0x80 0x01

#Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x48 0x00

#Write: Close email W 0x34 0x77|0x80 0x00

#Write: Verify LUT W 0x34 0x7D|0x80 0x00

# Add validation to complete delay or polling status
#Write: Start pattern sequence W 0x34 0x65|0x80 0x02

After completing the above register settings, we found that the read value of register 0x7D is 0x01. What could be the cause of this issue, and how can it be resolved?

Looking forward to your reply!

RE: DLPC350: The projection design using dlpc350 + DLP4500, with pattern mode and trigger mode 0, fails the register design verification. What could be the reason?

yongning chen — Thu, 30 Jul 2026 10:00:25 GMT

One more point to add:

The video stream of the RGB channels we input to the dlpc350 is FPGA-simulated. During the DE active period, the resolution is 1280x800, the data clock of RGB is 72 MHz, and the VSYNC period = 1340x862/72 = 16080 us.

RE: DLPC350: The projection design using dlpc350 + DLP4500, with pattern mode and trigger mode 0, fails the register design verification. What could be the reason?

yongning chen — Thu, 30 Jul 2026 09:35:46 GMT

The above setting command is not very user-friendly. After adjustment, it looks like this:

#Write: Set the display mode to pattern display
W 0x34 0x69|0x80 0x01

# Write: Stop Sequence (Display if running)
W 0x34 0x65|0x80 0x00

#Write: Set the graphics display mode source to RGB
W 0x34 0x6f|0x80 0x00

#Write: Set mode number 1 - Mode
W 0x34 0x75|0x80 0x02 0x01 0x02 0x00

#Write: Set mode trigger mode - 0
W 0x34 0x70|0x80 0x00

#Write: Exposure Time
W 0x34 0x66|0x80 0xF0 0x14 0x00 0x00 0xD0 0x3E 0x00 0x00 // 0x3ED0 corresponds to 16080us, 0x14F0 corresponds to 5360us. 5360x3=16080

#Write: Set Pat LUT
W 0x34 0x77|0x80 0x02

#Write: Pat LUT offset //Set the first LUT
W 0x34 0x76|0x80 0x00

#Write: Fill Pat LUT data
W 0x34 0x78|0x80 0x00 0x28 0x00

#Write: Close email
W 0x34 0x77|0x80 0x00

#Write: Set Pat LUT
W 0x34 0x77|0x80 0x02

#Write: Pat LUT offset //Set the 2nd LUT
W 0x34 0x76|0x80 0x01

#Write: Fill Pat LUT data
W 0x34 0x78|0x80 0x00 0x18 0x00

#Write: Close email
W 0x34 0x77|0x80 0x00

#Write: Set Pat LUT
W 0x34 0x77|0x80 0x02

#Write: Pat LUT offset //Set the 3rd LUT
W 0x34 0x76|0x80 0x02

#Write: Fill Pat LUT data
W 0x34 0x78|0x80 0x00 0x48 0x00

#Write: Close email
W 0x34 0x77|0x80 0x00

#Write: Verify LUT
W 0x34 0x7D|0x80 0x00

# Add validation to complete delay or polling status

#Write: Start pattern sequence
W 0x34 0x65|0x80 0x02

Looking forward to your reply!

DLP3010EVM-LC: DLP功能

wang yu wang — Thu, 30 Jul 2026 01:41:01 GMT

Part Number: DLP3010EVM-LC

DLP3010EVM-LC能否通过内部图案模式让RGB通道分别点亮，并通过Trigger Out逐图触发海康相机

DLP230NP: TIDA-80009的TI公版板卡更换新光机异常

chuanghong wu — Tue, 28 Jul 2026 02:19:20 GMT

Part Number: DLP230NP

After replacing the new projector, the screen was supposed to display color bars, but it showed a grayish image with some parts black. The colors and images are abnormal. Can you help suggest some ways to analyze the problem?

DLP650TE: Test raw data

molly Tseng — Fri, 24 Jul 2026 10:14:35 GMT

Part Number: DLP650TE

We need test raw data for the ship date on 7/8.

CustPartNumber	Shipping date	BoxQty	ProFormaInv	Customer_PO	ACO/CCO
48.7JL01G001	2026/7/8	3,300	5537829184	300818710	TW/JP

DLP3010EVM-LC: DLP3010EVM-LC, can the device still function properly after removing the plastic casing and the light source?

Hawkin Fong — Thu, 23 Jul 2026 16:18:27 GMT

Part Number: DLP3010EVM-LC

我们想把外壳拆掉，然后替换我们自己的光源，是买回来就可以直接用还是？光源是否有外接设备接口，接口协议是否有要求。

We want to remove the outer casing and replace it with our own light source. Can we just use it directly after purchasing or not? Does the light source have an external device interface? And are there any interface protocol requirements?

然后外显想接自己的显示屏或者投影，外显接口有什么要求?电源有什么要求?

Then I want to connect my own display or projector. What are the requirements for the external display interface? And what about the power supply?

以上总共三个问题，大伙有空看到帮忙解答一下。确认之后我就准备购置一套来实验看看。

Out of the three questions above, if anyone has the time, please feel free to answer them. After confirming the answers, I will be ready to purchase a set to conduct an experiment with.
套件链接如下：The link for the evaluation board is as follows:
DLP3010EVM-LC 评估板 | 德州仪器 TI.com.cn

RE: DLP3010EVM-LC: DLP3010EVM-LC, can the device still function properly after removing the plastic casing and the light source?

Hawkin Fong — Thu, 23 Jul 2026 17:00:25 GMT

主板、电源板、光源、外显屏幕总成，应该就这4部分。我想要的是4个部分可以随意插拔更换后组装在一起的。
The mainboard, power board, light source, and external display assembly - these are the four components. What I want is that these four parts can be easily plugged in, removed, and replaced, and then assembled together.

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