https://e2echina.ti.com/support/dlp/zh-CNTelligent Community 13https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087471/dlp991u-dmd/3914068Mon, 03 Aug 2026 07:06:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:c68e865b-b9c2-452d-9c80-006a397335faTaylor400-700nm的只有下面的13款， Visible (420 to 700nm) DMDs product selection | TI.com 4K的只有DLP991U，没有更高的了。 刷新率有更高的， DLP9000X ， DLP9500 ， DLP7000https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087471/dlp991u-dmd/3914066Mon, 03 Aug 2026 07:03:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:4500f685-fa2a-4a23-9103-eb369c4c0a55Taylor您好， 已经收到了您的案例，调查需要些时间，感谢您的耐心等待。https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087471/dlp991u-dmdMon, 03 Aug 2026 06:52:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:23bd6006-af03-4292-a437-efaa303b5bc8Lee TalenPart Number: DLP991U Dear TI Teams, 您好，我司想要采购DMD，需要尽可能多的像素数和尽可能高的刷新率。 我看到官网上在400-700nm波段有4K的DLP991U可供选择，请问： 1. 像素数有无更高的DMD阵列如8K？ 2. 刷新率有无尽可能快的DMD如百微秒量级？(区分局部刷新率和全局刷新率) 感谢帮助DLP9500DLP991UDLP7000DLP9000Xhttps://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087289/dlpc231s-q1-dlpc231s-tps99002s/3914061Mon, 03 Aug 2026 06:26:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:e6e3c4de-0f18-483e-a495-0731deeb804cFRANK1你好，这个评估板的电路图或BOM没体现NTC的型号的话，我们也获取不到这个信息。可能是另一侧的设计资源https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087289/dlpc231s-q1-dlpc231s-tps99002s/3913533Fri, 31 Jul 2026 08:03:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:6b193349-ed27-4239-8198-aa07f3d19a7aFRANK1感谢您对TI产品的关注！ 关于你的咨询，我们正在确认您的问题，感谢您的耐心等待。https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087290/dlpc231s-q1-dlpc231s-tps99002sFri, 31 Jul 2026 07:55:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:5bd55ee4-63a6-4e63-9408-6e5e34739d19ryan zengPart Number: DLPC231S-Q1 Hello Teams， 在参考设计 DLP121E2_SCH_20260311.pdf 中，TPS9900S有使用NTC进行温度采集反馈，但是在图纸未体现NTC电阻及其型号，能否告知接插件另一端使用的NTC电阻的完整型号呢？ 谢谢！DLPC231S-Q1https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087289/dlpc231s-q1-dlpc231s-tps99002sFri, 31 Jul 2026 07:52:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:9e09caa7-62c2-43b9-815e-53bbf879885dryan zengPart Number: DLPC231S-Q1 Hello Teams， 在参考设计 DLP121E2_SCH_20260311.pdf 中，TPS9900S有使用NTC进行温度采集反馈，但是在图纸未体现NTC电阻及其型号，能否告知接插件另一端使用的NTC电阻的完整型号呢？ 谢谢！DLPC231S-Q1https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087275/dlpc350-i-m-not-quite-clear-about-the-meanings-of-different-trigger-modes-in-the-pattern-mode-of-the-dlpc350-i-would-like-to-seek-your-advice-on-thisThu, 30 Jul 2026 14:09:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:dcbf2638-28d0-4eb0-92d7-980eefda1151yongning chenPart Number: DLPC350 Other Parts Discussed in Thread: DLP4500 Dear TI Technical Expert! In the pattern mode of dlpc350, the trigger modes include trigger mode 0, trigger mode 1, and trigger mode 2. We are engaged in industrial-grade 3D scanning applications. The requirement is: to reliably update and project the pattern through an external control signal, and achieve precise coordination with the camera's photography, so as to achieve the most optimized photography and acquisition of the projected pattern. Under such requirements, may I ask: 1. Is it better to use trigger mode 0 or trigger mode 1? Or can both modes achieve the same effect well? Why? 2. In trigger mode 0, is VSYNC considered an external trigger signal or an internal trigger signal? Is the function of VSYNC the same as TRIG_IN_1 in trigger mode 1, which is to advance to the next pattern? For the register (I2C: 0x78), does bit[1:0] of byte0 select b00 = Internal or can it choose b01 = External positive or b10 = External negative or b11 = No input trigger (continue from previous; the pattern still has full exposure time)? What does selecting b00 = Internal specifically refer to? Is it the internal trigger, VSYNC, or the register writing? When can b11 = No input trigger be selected? Can TRIG_OUT_1 be used to provide exposure for camera shooting? In Table 4-2. Trigger Mode 0 Example of the document DLPU010G, is the setting of registers 0x77, 0x76, 0x78 only applicable if using images from flash memory? If not using images from flash memory, are the registers 0x77, 0x76, 0x78 not set? Does this Table 4-2. Trigger Mode 0 Example mean that while inputting a pattern through the RGB channels, it is also possible to read the images stored in the flash memory simultaneously? How can this be done, and how is the timing of the projection of different sources of pattern patterns controlled? If VSYNC is controlled by FPGA logic, can the pattern images be precisely controlled to change by using the rising and falling of VSYNC? Or is VSYNC like a video stream, only being a fixed period signal and not easily changing the period value? What are its limitations? 3. In trigger mode 1, is it through TRIG_IN_1 to control the replacement of the pattern, and through TRIG_IN_2 to achieve the stable display of the pattern (by projecting the pattern through DLP)? Is the display of the pattern by DLP4500 a simultaneous flipping of all related mirrors, or a line-by-line flipping? Due to the urgency of the project, we hope to receive a reply as soon as possible!DLP4500DLPC350https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087274/dlpc350-dlpu010g-regarding-pattern-exposure-time-and-frame-period-seems-to-have-inconsistent-statements-what-is-the-relationship-between-themThu, 30 Jul 2026 13:17:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:40ee0fd2-8d65-48f4-8010-2251e0e8a7f5yongning chenPart Number: DLPC350 Dear Technical Expert! In the document DLPU010G – May 2013 – Revised July 2018, on page 48 of the description of the dlp0x66 register, in the external video input pattern sequence modes, the pattern exposure time must be equal to the frame period. However, on page 61, in Table 4-2. Trigger Mode 0 Example, for register 0x66, Set the exposure and frame rate (4 bytes for each) so that the time between vsync triggers will allow three patterns to be shown For example, for a 60-Hz vsync, the maximum exposure time is 16667 ÷ 3. These two points are clearly in conflict. On page 48, it states that the pattern exposure time must be equal to the frame period. However, on page 61, it says that the time between vsync triggers will allow three patterns to be displayed. Is "the frame period" here referring to the frame period of VSYNC? We input the pattern through RGB, and select an 8-bit pattern. Then we have pattern num 1 (green 8-bit), pattern num 2 (red 8-bit), and pattern num 3 (blue 8-bit). In this case, what is the relationship between the pattern exposure time and the frame period? How should the register 0x66 be set? If the frame period of VSYNC is 12000us, should the pattern exposure time be set to 4000us or 12000us? How can we project 3 pattern patterns within one VSYNC frame period? These three pattern patterns correspond to the pattern num 1, pattern num 2, and pattern num 3 described in Table 2-70 of Document DLPU010G? In the above situation, how should the registers 0x75 and 0x78 be set? Due to the urgency of the project, we hope to receive a reply as soon as possible!DLPC350https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087271/dlpc350-dlpc350-the-projection-design-using-dlpc350-dlp4500-with-pattern-mode-and-trigger-mode-0-fails-the-register-design-verification-what-could-be-the-reasonThu, 30 Jul 2026 12:37:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:1bf78634-80f3-4055-8a93-e83fdbcc94b8yongning chenPart Number: DLPC350 Other Parts Discussed in Thread: DLP4500 , Dear TI expert! We are using the DLPC350 + DLP4500 for projection design, with the following requirements: Input graphics via RGB interface only throughout the entire process. Select trigger mode 0, VSYNC triggering, 8-bit pattern, and a total of 3 patterns. The VSYNC period is 16,080 μs. We expect to output three patterns within one VSYNC cycle. These three patterns correspond respectively to the graphic data inputs of the RGB channels. All three patterns have the same exposure time and are triggered identically by VSYNC. Our register settings are as follows: #Write: Set the display mode to pattern display W 0x34 0x69|0x80 0x01 # Write: Stop Sequence (Display if running) W 0x34 0x65|0x80 0x00 #Write: Set the graphics display mode source to RGB W 0x34 0x6f|0x80 0x00 #Write: Set mode number 1 - Mode W 0x34 0x75|0x80 0x02 0x01 0x02 0x00 #Write: Set mode trigger mode - 0 W 0x34 0x70|0x80 0x00 #Write: Exposure Time W 0x34 0x66|0x80 0xF0 0x14 0x00 0x00 0xD0 0x3E 0x00 0x00 // 0x3ED0 corresponds to 16080us, 0x14F0 corresponds to 5360us. 5360x3=16080 #Write: Set Pat LUT W 0x34 0x77|0x80 0x02 #Write: Pat LUT offset //Set the first LUT W 0x34 0x76|0x80 0x00 #Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x28 0x00 #Write: Close email W 0x34 0x77|0x80 0x00 #Write: Set Pat LUT W 0x34 0x77|0x80 0x02 #Write: Pat LUT offset //Set the 2nd LUT W 0x34 0x76|0x80 0x01 #Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x18 0x00 #Write: Close email W 0x34 0x77|0x80 0x00 #Write: Set Pat LUT W 0x34 0x77|0x80 0x02 #Write: Pat LUT offset //Set the 3rd LUT W 0x34 0x76|0x80 0x02 #Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x48 0x00 #Write: Close email W 0x34 0x77|0x80 0x00 #Write: Verify LUT W 0x34 0x7D|0x80 0x00 # Add validation to complete delay or polling status #Write: Start pattern sequence W 0x34 0x65|0x80 0x02 After completing the above register settings, we found that the read value of register 0x7D is 0x01. What could be the cause of this issue, and how can it be resolved? One more point to add: The video stream of the RGB channels we input to the dlpc350 is FPGA-simulated. During the DE active period, the resolution is 1280x800, the data clock of RGB is 72 MHz, and the VSYNC period = 1340x862/72 = 16080 us. Looking forward to your reply!DLP4500DLPC350https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087257/dlpc350-the-projection-design-using-dlpc350-dlp4500-with-pattern-mode-and-trigger-mode-0-fails-the-register-design-verification-what-could-be-the-reason/3913440Thu, 30 Jul 2026 10:00:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:6870d523-6ec3-4504-ae99-80c968320780yongning chenOne more point to add: The video stream of the RGB channels we input to the dlpc350 is FPGA-simulated. During the DE active period, the resolution is 1280x800, the data clock of RGB is 72 MHz, and the VSYNC period = 1340x862/72 = 16080 us.https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087257/dlpc350-the-projection-design-using-dlpc350-dlp4500-with-pattern-mode-and-trigger-mode-0-fails-the-register-design-verification-what-could-be-the-reason/3913439Thu, 30 Jul 2026 09:35:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:7c408166-2bcd-4285-ab39-6d3fcd6f9136yongning chenThe above setting command is not very user-friendly. After adjustment, it looks like this: #Write: Set the display mode to pattern display W 0x34 0x69|0x80 0x01 # Write: Stop Sequence (Display if running) W 0x34 0x65|0x80 0x00 #Write: Set the graphics display mode source to RGB W 0x34 0x6f|0x80 0x00 #Write: Set mode number 1 - Mode W 0x34 0x75|0x80 0x02 0x01 0x02 0x00 #Write: Set mode trigger mode - 0 W 0x34 0x70|0x80 0x00 #Write: Exposure Time W 0x34 0x66|0x80 0xF0 0x14 0x00 0x00 0xD0 0x3E 0x00 0x00 // 0x3ED0 corresponds to 16080us, 0x14F0 corresponds to 5360us. 5360x3=16080 #Write: Set Pat LUT W 0x34 0x77|0x80 0x02 #Write: Pat LUT offset //Set the first LUT W 0x34 0x76|0x80 0x00 #Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x28 0x00 #Write: Close email W 0x34 0x77|0x80 0x00 #Write: Set Pat LUT W 0x34 0x77|0x80 0x02 #Write: Pat LUT offset //Set the 2nd LUT W 0x34 0x76|0x80 0x01 #Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x18 0x00 #Write: Close email W 0x34 0x77|0x80 0x00 #Write: Set Pat LUT W 0x34 0x77|0x80 0x02 #Write: Pat LUT offset //Set the 3rd LUT W 0x34 0x76|0x80 0x02 #Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x48 0x00 #Write: Close email W 0x34 0x77|0x80 0x00 #Write: Verify LUT W 0x34 0x7D|0x80 0x00 # Add validation to complete delay or polling status #Write: Start pattern sequence W 0x34 0x65|0x80 0x02 Looking forward to your reply!https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087257/dlpc350-the-projection-design-using-dlpc350-dlp4500-with-pattern-mode-and-trigger-mode-0-fails-the-register-design-verification-what-could-be-the-reasonThu, 30 Jul 2026 09:29:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:f5960583-7db7-4556-95b5-8883fb247edayongning chenPart Number: DLPC350 Other Parts Discussed in Thread: DLP4500 , Dear TI expert! We are using the DLPC350 + DLP4500 for projection design, with the following requirements: Input graphics via RGB interface only throughout the entire process. Select trigger mode 0, VSYNC triggering, 8-bit pattern, and a total of 3 patterns. The VSYNC period is 16,080 μs. We expect to output three patterns within one VSYNC cycle. These three patterns correspond respectively to the graphic data inputs of the RGB channels. All three patterns have the same exposure time and are triggered identically by VSYNC. Our register settings are as follows: #Write: Set the display mode to pattern display W 0x34 0x69|0x80 0x01 # Write: Stop Sequence (Display if running) W 0x34 0x65|0x80 0x00 #Write: Set the graphics display mode source to RGB W 0x34 0x6f|0x80 0x00 #Write: Set mode number 1 - Mode W 0x34 0x75|0x80 0x02 0x01 0x02 0x00 #Write: Set mode trigger mode - 0 W 0x34 0x70|0x80 0x00 #Write: Exposure Time W 0x34 0x66|0x80 0xF0 0x14 0x00 0x00 0xD0 0x3E 0x00 0x00 // 0x3ED0 corresponds to 16080us, 0x14F0 corresponds to 5360us. 5360x3=16080 #Write: Set Pat LUT W 0x34 0x77|0x80 0x02 #Write: Pat LUT offset //Set the first LUT W 0x34 0x76|0x80 0x00 #Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x28 0x00 #Write: Close email W 0x34 0x77|0x80 0x00 #Write: Set Pat LUT W 0x34 0x77|0x80 0x02 #Write: Pat LUT offset //Set the 2nd LUT W 0x34 0x76|0x80 0x01 #Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x18 0x00 #Write: Close email W 0x34 0x77|0x80 0x00 #Write: Set Pat LUT W 0x34 0x77|0x80 0x02 #Write: Pat LUT offset //Set the 3rd LUT W 0x34 0x76|0x80 0x01 #Write: Fill Pat LUT data W 0x34 0x78|0x80 0x00 0x48 0x00 #Write: Close email W 0x34 0x77|0x80 0x00 #Write: Verify LUT W 0x34 0x7D|0x80 0x00 # Add validation to complete delay or polling status #Write: Start pattern sequence W 0x34 0x65|0x80 0x02 After completing the above register settings, we found that the read value of register 0x7D is 0x01. What could be the cause of this issue, and how can it be resolved? Looking forward to your reply!DLP4500DLPC350https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1087232/dlp3010evm-lc-dlpThu, 30 Jul 2026 01:41:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:966597f8-0747-4ffa-bb44-6c4d7bf5fa51wang yu wangPart Number: DLP3010EVM-LC DLP3010EVM-LC能否通过内部图案模式让RGB通道分别点亮，并通过Trigger Out逐图触发海康相机DLP3010EVM-LChttps://e2echina.ti.com/support/dlp/f/dlp-products-forum/1086783/dlp230np-tida-80009-tiTue, 28 Jul 2026 02:19:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:8f8bd9b0-972e-470a-944b-e41f7118a11fchuanghong wuPart Number: DLP230NP After replacing the new projector, the screen was supposed to display color bars, but it showed a grayish image with some parts black. The colors and images are abnormal. Can you help suggest some ways to analyze the problem?DLP230NP家庭影院和娱乐https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1086308/dlp650te-test-raw-dataFri, 24 Jul 2026 10:14:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:25fad3ed-a6ce-436e-bef1-938cf4c0590bmolly TsengPart Number: DLP650TE We need test raw data for the ship date on 7/8. CustPartNumber Shipping date BoxQty ProFormaInv Customer_PO ACO/CCO 48.7JL01G001 2026/7/8 3,300 5537829184 300818710 TW/JPDLP650TEhttps://e2echina.ti.com/support/dlp/f/dlp-products-forum/1086043/dlp3010evm-lc-dlp3010evm-lc-can-the-device-still-function-properly-after-removing-the-plastic-casing-and-the-light-source/3909024Thu, 23 Jul 2026 17:00:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:5e0c4a6d-53f3-4313-aa38-22af7ab78315Hawkin Fong主板、电源板、光源、外显屏幕总成，应该就这4部分。我想要的是4个部分可以随意插拔更换后组装在一起的。 The mainboard, power board, light source, and external display assembly - these are the four components. What I want is that these four parts can be easily plugged in, removed, and replaced, and then assembled together.https://e2echina.ti.com/support/dlp/f/dlp-products-forum/1086043/dlp3010evm-lc-dlp3010evm-lc-can-the-device-still-function-properly-after-removing-the-plastic-casing-and-the-light-sourceThu, 23 Jul 2026 16:18:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:070c6e66-3e06-4589-8a21-a36acbd91ec5Hawkin FongPart Number: DLP3010EVM-LC 我们想把外壳拆掉，然后替换我们自己的光源，是买回来就可以直接用还是？光源是否有外接设备接口，接口协议是否有要求。 We want to remove the outer casing and replace it with our own light source. Can we just use it directly after purchasing or not? Does the light source have an external device interface? And are there any interface protocol requirements? 然后外显想接自己的显示屏或者投影，外显接口有什么要求?电源有什么要求? Then I want to connect my own display or projector. What are the requirements for the external display interface? And what about the power supply? 以上总共三个问题，大伙有空看到帮忙解答一下。确认之后我就准备购置一套来实验看看。 Out of the three questions above, if anyone has the time, please feel free to answer them. After confirming the answers, I will be ready to purchase a set to conduct an experiment with. 套件链接如下：The link for the evaluation board is as follows: DLP3010EVM-LC 评估板 | 德州仪器 TI.com.cnDLP3010EVM-LChttps://e2echina.ti.com/support/dlp/f/dlp-products-forum/1085375/dlpnirscanevmMon, 20 Jul 2026 06:58:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:68fb26d9-1bb6-43f3-b7dd-9c9d7c554655Qirui JiangPart Number: DLPNIRSCANEVM 通电后绿灯和蓝灯常亮，红灯报警报错，无法正常工作和连接电脑usb测试和测量DLPNIRSCANEVMhttps://e2echina.ti.com/support/dlp/f/dlp-products-forum/1085009/dlp4710evm-lc-dlp4710Fri, 17 Jul 2026 12:27:00 GMT91561404-af28-475a-b96b-cb6cbaadd097:3e355ef9-ea84-43dd-92ed-373c6aed6993rongliang zhuPart Number: DLP4710EVM-LC Other Parts Discussed in Thread: DLP4710 如何使用dlp4710光机投影出二维随机散斑图案，我想要连续投射三张条纹加一张散斑并可以同步触发相机采集DLP4710DLP4710EVM-LC