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DP83TG720S-Q1: RGMII cannot communicate

Part Number: DP83TG720S-Q1

Hi TI team:

    When debugging DP83TG720S-Q1, I configured the PHY to RGMII mode and completed the initialization sequence. After the initialization is completed, the relevant registers are dumped, and the working mode and Link Up status of the PHY chip are confirmed:

    But when I communicated through RGMII, it's failed. I guess it's the timing of RGMII. I caught the waveform of RGMII through the oscilloscope, but I couldn't analyze it.

    I want to confirm whether it is a RGMII timing problem? If it is the RGMII timing, how can I adjust it?

  • Hi Alex,

    Simply looking at the signal amplitude is not correct, did the probe attenuate when you measured it?

  • The actual voltage amplitude is correct, this may be a problem with my oscilloscope Settings.

  • Hi Alex,

    To solve your problem more effectively, I ask a TI senior engineer who knows more about the IC,  and I'll get back to you as soon as I get a response. 

  • Hi Alex,

    Below is the reply I received from senior engineer, please try his advice:

    It's possible this is an RGMII timing problem between the MAC and PHY.

    Please try testing the device in RGMII shift mode by strapping RX_D2 and RX_D1 high.

    Shift mode can also be enabled by programming register 0x602[1:0] = '11', and the shift delay can be tuned using register 0x430[11:4].

    This FAQ is a useful reference for selecting the correct RGMII delay mode.



  • Hi Amy,

    I tried this advice:Enable shift mode by programming register 0x602 [1:0] = '11'; and all TX delay values were tried on register 0x430[11:8].

    (Why did I not change the RX delay because there are many ways to combine the two delays and I intend to switch on the tx link first.)

    My test equipment is "VECTOR VN5620". I haven't seen the data coming from VN5620.I would like to ask if this method of only looking at TX data and only adjusting TX delay is correct?

    The following figure shows the waveform on the TX link:

    Below I dump the relevant registers for use with reference:

    This data goes from MAC to PHY. Is there any way to check whether the phy is receiving data correctly?

    My MAC terminal uses SJA1110, have you tried this combination?

  • Hi Alex,

    I have submitted your case to this engineer, and I will get back to you when I get reply. 

  • If the TX/RX traces between the MAC and PHY are length-matched, I recommend testing with the same delay applied to both TX and RX in shift mode.

    To check if the PHY is receiving the data from the MAC:

    Enable RGMII loopback with reg<0x0000> = 0x4140, and probe the RGMII RX pins to see if the same data from the MAC is looped back. Register 0x063C[15:0] reports the total received packets, this can be compared to the number of packets sent from the MAC.

  • Thanks, luo. I have solved the problem. It's because of VDDIO level mismatch

  • Hi Alex,

    I'm glad your issue has been resolved and thank you for your feedback.