Other Parts Discussed in Thread: ALP
1.981和988均在本地初始化。脚本见附件
2.981的pattern--VP0--可以正常点亮988侧的TFT
3.开阳输出MIPI信号，981切换为MIPI--VP0。当前排查981侧VP_total为0，异常
page4:
0x2A = 0x3E
0x30 = 0x7E
0x31 = 0x59
page12:
0x30= 0x00
981配置源码：
""" Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ ALL RIGHTS RESERVED """ """ Global Setups - Do Not Change """ FPD4 = [0,0] FPD4Rate = [0,0] FPD3Stream = [0,0] THW = [0,0,0,0] TVW = [0,0,0,0] AHW = [0,0,0,0] AVW = [0,0,0,0] HBP = [0,0,0,0] VBP = [0,0,0,0] HSW = [0,0,0,0] VSW = [0,0,0,0] HFP = [0,0,0,0] VFP = [0,0,0,0] HSP = [0,0,0,0] VSP = [0,0,0,0] PCLK = [0,0,0,0] Bits_per_pixel = [0,0,0,0] PATGEN = [0,0,0,0] CropEnable = [0,0,0,0] FilterEnable = [0,0,0,0] CropXStart = [0,0,0,0] CropXStop = [0,0,0,0] CropYStart = [0,0,0,0] CropYStop = [0,0,0,0] FilterEnable = [0,0,0,0] FilterA = [0,0,0,0] FilterN = [0,0,0,0] DSI_PORT0 = 0 DSI_PORT1 = 0 MAPSEL = [0,0] OLDIBpp = [0,0] HDCP = [0,0] Des0_DaisyVPs = [0,0,0,0] FPD4RateDaisy0 = [0,0,0] FPD4RateDaisy1 = [0,0,0] FPD4Daisy0 = [1,1] DP0_ON = [0,0,0,0] DP1_ON = [0,0,0,0] DP_Output_0_Source = [0,0,0,0] DP_Output_1_Source = [0,0,0,0] Des_Device = [0,0,0,0] DP_Rate = [0,0,0,0] DP_Lane_Num = [0,0,0,0] RGBMode = [0,0,0,0] OLDIEnabled = [0,0,0,0] MAPSEL0 = [0,0,0,0] MAPSEL1 = [0,0,0,0] RGBBpp = [0,0,0,0] OLDIBpp0 = [0,0,0,0] OLDIBpp1 = [0,0,0,0] OLDI_RGB_Port0_Source = [0,0,0,0] OLDI_Port1_Source = [0,0,0,0] DaisyConf = [0,0,0] FPD4LinkEN0 = [0,0,0,0] FPD4LinkEN1 = [0,0,0,0] DES_Display_SSCG = [0,0,0,0] DES_Display_SSCG_FDEV = [0,0,0,0] DES_Display_SSCG_FMOD = [0,0,0,0] serFPDSSCG = [0,0] serFPDSSCG_fdev = [0,0] serFPDSSCG_fmod = [0,0] eFuseOV = 0 FPD3DaisyVP_P0 = [0,0,0] FPD3DaisyVP_P1 = [0,0,0] DES_BC_SSCG = [0,0,0,0] DES_BC_SSCG_FDEV = [0,0,0,0] DES_BC_SSCG_FMOD = [0,0,0,0] """ General Configurations - Set by the user """ # Serializer Address # Ignore if using DES only configurations SER_Address = 0x18 # First deserializer Address Port 0 # For dual FPD-Link configurations use this address for the first deserializer. P1 addresses are ignored # For single port 0 or independent FPD configurations this is the address of the first DES attached to port 0 DES0_Address = 0x58 DES0_Alias = 0x58 # First deserializer Address Port 1 # Only used for single port 1 or independent FPD link configurations P1DES0_Address = 0x58 P1DES0_Alias = 0x60 # Deserializer Daisy Chain Addresses DES1_Address = 0x58 DES1_Alias = 0x62 DES2_Address = 0x58 DES2_Alias = 0x64 DES3_Address = 0x58 DES3_Alias = 0x66 # Serializer Device # For FPD IV serializer, options are 983 or 981 # For FPD III serializer, options are 925, 926, 921, 929, 949, 941AS, 947 Device = "981" # DES eFuse Override Enable # Enabling eFuse override will generate a script to # manually override the eFuse settings for the DES # to the final production version when using either 984 or 988 eFuseOV = 0 # If Des_Only = 1, 98x Serialzier configuration will be ignored but # 94x/92x SER configuration will be included if Fes_FPD3_Only = 1 # Only applicable for configurations with 988/984 DES # Use this setting when the SER is 94x or 92x FPD III or to generate a 98x to 98x script # which only includes the DES side configurations Des_Only = 0 # Select deserializer PatGen enable # Only applicable for FPD IV DES configurations - ignore for FPD III DES configurations # 0 = disable # 1 = enable DES_Patgen_on = 0 # If Des_FPD3_Only = 1, Serialzier configuration will be ignored and Deserializer will be configured to FPD3 mode. # Only applicable for 988/984 configurations - ignore if using FPD III DES device Des_FPD3_Only = 0 # Set the deserializer FPD port configuration # Ignored if serializer is 98x # Options: # FPD3 Dual = 5 # FPD3 Single Port 0 = 6 DES_FPDIII_Conf = 5 # Set the serializer FPD port configuration # Options: # FPD4 Dual = 1 # FPD4 Single Port 0 = 2 # FPD4 Single Port 1 = 3 # FPD4 Independent = 4 # FPD3 Dual = 5 # FPD3 Single Port 0 = 6 # FPD3 Single Port 1 = 7 # FPD3 Independent = 8 # FPD4 Port 0/FPD3 Port 1 = 9 # FPD3 Port 0/FPD4 Port 1 = 10 FPDConf = 2 # Enable HDCP1.4 per FPD Channel (Only applicable for UH to UH connections) # Options: 0 = No HDCP, 1 = HDCP Enabled # HDCP[0] controls FPD port 0 # HDCP[1] controls FPD port 1 # Unused FPD ports are ignored and only the HDCP[0] setting is used for dual FPD modes HDCP[0] = 0 HDCP[1] = 0 # Enter number of VPs used # Options: # 1 Display = 1 (VP0) # 2 Displays = 2 (VP0/VP1) # 3 Displays = 3(VP0/VP1/VP2) # 4 Displays = 4 (VP0/VP1/VP2/VP3) numVPs = 1 # Enter Video Processor 0 Properties # THW = Horizontal Total Pixels = AHW + HBP + HFP + HSW # TVW = Vertical Total Lines = AVW + VBP + VFP + VSW # AHW = Hoizontal Active Pixels # AVW = Vertical Active Lines # HBP = Horizontal Back Porch Pixels # VBP = Vertical Back Porch Pixels # HSW = Horizontal Sync Width Pixels # VSW = Vertical Sync Width Lines # HSP = Horizontal Sync Polarity: 0 = Positive, 1 = Negative # VSP = Vertical Sync Polarity: 0 = Positive, 1 = Negative # PCLK = Pixel Clock Rate in MHz # Bits_per_pixel = 18, 24, or 30 (30bpp only available for FPD IV) # PATGEN = 1 - Generate PATGEN from the VP # PATGEN = 0 - Configure the VP but don't enable PATGEN (use for end to end video) # If Des is set to FPD3 mode only, VP0 timing is used to configure Des. AHW[0] = 1280 AVW[0] = 720 HBP[0] = 48 HFP[0] = 16 HSW[0] = 32 VBP[0] = 8 VFP[0] = 36 VSW[0] = 4 THW[0] = HFP[0] + AHW[0] + HBP[0] + HSW[0] TVW[0] = VFP[0] + AVW[0] + VBP[0] + VSW[0] HSP[0] = 0 VSP[0] = 0 PCLK[0] = 62 Bits_per_pixel[0] = 24 PATGEN[0] = 0 # Crop and filter parameters (Optional - Ignored if CropEnable[x] is 0) CropEnable[0] = 0 CropXStart[0] = 0 CropXStop[0] = 1279 CropYStart[0] = 0 CropYStop[0] = 719 # Filter parameters (Optional - Ignored if FilterEnable[x] is 0) FilterEnable[0] = 0 FilterA[0] = 1 FilterN[0] = 2 # Enter Video Processor 1 Properties (Optional) AHW[1] = 1920 AVW[1] = 720 HBP[1] = 48 HFP[1] = 48 HSW[1] = 12 VBP[1] = 40 VFP[1] = 4 VSW[1] = 4 THW[1] = HFP[1] + AHW[1] + HBP[1] + HSW[1] TVW[1] = VFP[1] + AVW[1] + VBP[1] + VSW[1] HSP[1] = 0 VSP[1] = 0 PCLK[1] = 93 Bits_per_pixel[1] = 24 PATGEN[1] = 1 # Crop and filter parameters (Optional - Ignored if CropEnable[x] is 0) CropEnable[1] = 0 CropXStart[1] = 0 CropXStop[1] = 1399 CropYStart[1] = 0 CropYStop[1] = 1199 # Filter parameters (Optional - Ignored if FilterEnable[x] is 0) FilterEnable[1] = 0 FilterA[1] = 1 FilterN[1] = 2 # Enter Video Processor 2 Properties (Optional) AHW[2] = 1400 AVW[2] = 1200 HBP[2] = 16 HFP[2] = 16 HSW[2] = 12 VBP[2]= 92 VFP[2] = 12 VSW[2] = 2 THW[2] = HFP[2] + AHW[2] + HBP[2]+ HSW[2] TVW[2] = VFP[2] + AVW[2] + VBP[2]+ VSW[2] HSP[2] = 0 VSP[2] = 0 PCLK[2] = 113 Bits_per_pixel[2] = 24 PATGEN[2] = 1 # Crop and filter parameters (Optional - Ignored if CropEnable[x] is 0) CropEnable[2] = 1 CropXStart[2] = 1400 CropXStop[2] = 2799 CropYStart[2] = 0 CropYStop[2] = 1199 # Filter parameters (Optional - Ignored if FilterEnable[x] is 0) FilterEnable[2] = 0 FilterA[2] = 1 FilterN[2] = 2 # Enter Video Processor 3 Properties (Optional) THW[3] = 2200 TVW[3] = 1125 AHW[3] = 1920 AVW[3] = 1080 HBP[3] = 148 VBP[3] = 36 HSW[3] = 44 VSW[3] = 5 HFP[3] = THW[3] - AHW[3] - HBP[3] - HSW[3] VFP[3] = TVW[3] - AVW[3] - VBP[3] - VSW[3] HSP[3] = 0 VSP[3] = 0 PCLK[3] = 148.5 Bits_per_pixel[3] = 24 PATGEN[3] = 0 # Crop and filter parameters (Optional - Ignored if CropEnable[x] is 0) CropEnable[3] = 1 CropXStart[3] = 1920 CropXStop[3] = 3839 CropYStart[3] = 0 CropYStop[3] = 1079 # Filter parameters (Optional - Ignored if FilterEnable[x] is 0) FilterEnable[3] = 1 FilterA[3] = 1 FilterN[3] = 2 # Enter stream mapping for FPD3 Mode (ignored if using FPD4) # Ignore map setting for unused port in single FPD3 mode # If using dual mode, set FPD3Stream[0] and FPD3Stream[1] to the same VP # Options: 0 = VP0, 1 = VP1, 2 = VP2, 3 = VP3: Maps the corresponding VP to the FPD3 port FPD3Stream[0] = 0 FPD3Stream[1] = 0 # FPD4 Rate Selection (Gbps) # Ignored if the port is set to FPD3 mode # FPD4Rate[0] sets FPD TX Port 0 # FPD4Rate[1] sets FPD TX Port 1 # Options: 3.375, 6.75, 10.8, 13.5, 12.528 FPD4Rate[0] = 6.75 FPD4Rate[1] = 6.75 # FPD4 Port SSCG Configuration # serFPDSSCG[0] controls FPD Port 0 # serFPDSSCG[1] controls FPD Port 1 # Options: # 0 = Disabled # 1 = Enable SSCG Center Spread # 2 = Enable SSCG Down Spread serFPDSSCG[0] = 0 serFPDSSCG[1] = 0 # Serializer SSCG FDEV % # serFPDSSCG_fdev[0] controls FPD Port 0 # serFPDSSCG_fdev[1] controls FPD Port 1 # Ignored is serFPDSSCG = 0 # Sets the SSCG frequency deviation percentage for FPD4 port 0 # Options: 0-0.5 (%) serFPDSSCG_fdev[0] = 0.25 serFPDSSCG_fdev[1] = 0.25 # Display SSCG FMOD kHz # serFPDSSCG_fmod[0] controls FPD Port 0 # serFPDSSCG_fmod[1] controls FPD Port 1 # Ignored is DES_Display_SSCG = 0 # Set the SSCG modulation frequency for display interface SSCG # Options: 30-33 (kHz) serFPDSSCG_fmod[0] = 33 serFPDSSCG_fmod[1] = 33 # FPD4 Link Layer Selection for independent FPD IV Mode or mixed FPD III/IV modes # Ignored for dual FPD IV or single FPD IV modes # Select which VPs are forwarded to FPD Port 0 and Port 1 Link layers # FPD4LinkEN0 controls SER FPD Port 0 # FPD4LinkEN1 controls SER FPD Port 1 # For example, to send VP 0 to port 0 and VP1 to port 1, use the following # Note that in order to send any stream to both FPD ports, the FPD IV links rate must be the same # FPD4LinkEN0 = [1,0,0,0] # FPD4LinkEN1 = [0,1,0,0] FPD4LinkEN0 = [1,0,0,0] FPD4LinkEN1 = [0,1,0,0] """ 983 Configs - Ignored if using 981 """ # Set max DP lane count # Options: 1, 2, 4 DPlanes = 4 # Set max advertised DP lane rate in Gbps # Options: 1.62, 2.7, 5.4, 8.1 maxRate = 5.4 # Set MST or SST mode # Options: 0 = SST mode, 1 = MST mode # MST mode always uses VP0 for MST0 and VP1 for MST1 MST = 0 # Set DP receiver to expect SSC or no SSC from the DPTX # Options: 0 = No SSC, 1 = SSC SSC = 0 #Set DP receiver to DP or eDP mode # Options: 0 = DP Mode, 1 = eDP Mode eDP = 0 """ 981 Configs - Ignored if using 983 """ #DSI ports active # 0 = DSI 0 only # 1 = DSI 1 only # 2 = DSI 0 and DSI 1 DSI_PORTS_ACTIVE = 2 # Set max DSI lane count # Options: 1, 2, 3, 4 Port0_DSI_Lanes = 4 Port1_DSI_Lanes = 4 # Set DSI in Continuous or Non-Continuous Clock # 1 = Continuous ; 0 = Non-Continuous Clock Port0_Contin = 1 Port1_Contin = 1 # Set the DSI rate # example: 500 Mbps= 500, 1.2 Gbps = 1200Mbps Port0_DSI_Rate = 372 Port1_DSI_Rate = 372 #DSI Source for Video Processors #0 = DPHY 0 virtual Channel 0 #1 = DPHY 0 virtual Channel 1 #2 = DPHY 0 virtual Channel 2 #3 = DPHY 0 virtual Channel 3 #4 = DPHY 1 virtual Channel 0 #5 = DPHY 1 virtual Channel 1 #6 = DPHY 1 virtual Channel 2 #7 = DPHY 1 virtual Channel 3 VP_0_Source = 0 VP_1_Source = 4 VP_2_Source = 0 VP_3_Source = 0 """ ##################################### DES0 (First Deserialzier) Configurations - Ignored for FPD III Modes This section is referenced for FPD IV Dual mode or Single FPD IV Port 0 mode (NOT FPD IV Single Port 1 Mode) ##################################### """ # Des_Device # Only used for FPD IV deserializer configurations - ignore if using FPD III deserializer # Options 984, 988 Des_Device[0] = "988" # Set the deserializer Daisy Chain TX FPD port configuration # Options: # Daisy Chaining Disabled = 0 # FPD4 Dual = 1 # FPD4 Single Port 0 = 2 # FPD4 Single Port 1 = 3 # Net yet functional # FPD4 Independent = 4 # Net yet functional # FPD3 Dual = 5 # FPD3 Single Port 0 = 6 # FPD3 Single Port 1 = 7 # FPD3 Independent = 8 # FPD4 Port 0/FPD3 Port 1 = 9 # Net yet functional # FPD3 Port 0/FPD4 Port 1 = 10 # Net yet functional DaisyConf[0] = 2 # Enable daisy chain TX forwarding for deserializer 0 (first DES in the chain) # Set VPs 0-4 = 1 to enable forwarding of that VP to the next DES # If all VP forwarding is set to 0, then daisy chaining is disabled # Example: Forward only VP0 to the next DES: Des0_DaisyVPs = [1,0,0,0] # Example Forward VP1 and VP2 to the next DES: Des0_DaisyVPs = [0,1,1,0] Des0_DaisyVPs = [0,1,0,0] # Set which VP is forwarded to chain chain output in FPD III mode # FPD3DaisyVP_P0 controls daisy chain FPD port 0 # FPD3DaisyVP_P1 controls daisy chain FPD port 1 # FPD3DaisyVP_P0 and FPD3DaisyVP_P1 must be set to the same VP for dual FPD III mode # Setting the daisy chain output to FPD III mode terminates the daisy chain at the connected deserializer # This is ignored if the daisy chain is set up for FPD IV output mode # Example: Forward VP1 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 1 # Example: Forward VP3 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 3 FPD3DaisyVP_P0[0] = 1 FPD3DaisyVP_P1[0] = 1 # FPD4 Rate Selection for DES0 Daisy Chain TX (Gbps) # Ignored if the port is set to FPD3 mode # FPD4RateDaisy0[0] sets DES0 Daisy Chain TX Port 0 # FPD4RateDaisy1[0] sets DES0 Daisy Chain TX Port 1 # Options: 3.375, 6.75, 10.8, 13.5, 12.528 FPD4RateDaisy0[0] = 6.75 FPD4RateDaisy1[0] = 6.75 # FPD BC SSCG Configuration # SSCG options for the deserializer back channel output # Options: # 0 = Disable SSCG on FPD back channel interface # 1 = Enable SSCG with Center Spread # 2 = Enable SSCG with Down Spread DES_BC_SSCG[0] = 1 # FPD BC SSCG FDEV % # Ignored is DES_BC_SSCG = 0 # Sets the SSCG frequency deviation percentage for FPD back channel interface SSCG # Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread # Options: 0-0.5 (%) in Center Spread Mode # Options: 0-0.25 (%) in Down Spread Mode DES_BC_SSCG_FDEV[0] = 0.25 # FPD SSCG FMOD kHz # Ignored is DES_BC_SSCG = 0 # Set the SSCG modulation frequency for FPD back channel interface SSCG # Options: 30-33 (kHz) DES_BC_SSCG_FMOD[0] = 33 # Display SSCG Configuration # SSCG options for the deserializer display output (OLDI or DP/eDP Interface) # This is independent of the FPD-Link SSCG # Options: # 0 = Disable SSCG on display interface # 1 = Enable SSCG with Center Spread (988 only) # 2 = Enable SSCG with Down Spread DES_Display_SSCG[0] = 0 # Display SSCG FDEV % # Ignored is DES_Display_SSCG = 0 # Sets the SSCG frequency deviation percentage for display interface SSCG # Options: 0-6 (%) for 988 in Center Spread Mode (+/-3%) # Options: 0-3 (%) for 988 in Down Spread Mode # Options: 0-0.5 (%) for 984 (Down Spread Only) DES_Display_SSCG_FDEV[0] = 1 # Display SSCG FMOD kHz # Ignored is DES_Display_SSCG = 0 # Set the SSCG modulation frequency for display interface SSCG # Options: 10-100 (kHz) for 988 # Options: 30-33 (kHz) for 984 DES_Display_SSCG_FMOD[0] = 10 """ ##################################### DES0 (First Deserialzier) Configurations - Ignored for FPD III Modes ##################################### """ """ DES0 984 Configs - Ignored if using 988 """ #Select DP ports to be enabled # Enabled = 1, Disabled = 0 DP0_ON[0] = 1 DP1_ON[0] = 0 #Select video source for DP output #Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. # 0 = Stream 0 # 1 = Stream 1 # 2 = Stream 2 # 3 = Stream 3 DP_Output_0_Source[0] = 0 DP_Output_1_Source[0] = 0 # Select DP output lane rate and number of lanes # Options (in Gbps): # 1.62 # 2.7 # 5.4 # 8.1 DP_Rate[0] = 2.7 DP_Lane_Num[0] = 4 """ DES0 988 Configs - Ignored if using 984 """ # Select OLDI or RGB mode # Options: # 1 = RGB Mode Enabled # 0 = OLDI Mode RGBMode[0] = 0 # Select OLDI port configuration (Ignored for RGB mode) # Options: # 0 = Single OLDI port 0 # 1 = Single OLDI port 1 # 2 = Dual OLDI # 3 = Dual OLDI Swap OLDIEnabled[0] = 0 # Select MAPSEL Setting for port 0 and port 1 (Ignored for RGB mode) # 0 = MAPSEL = L (LSB on D3/D4) # 1 = MAPSEL = H (MSB on D3/D4) MAPSEL0[0] = 1 MAPSEL1[0] = 1 # Set OLDI Bits Per Pixel for port 0 and 1 (Ignored in RGB mode) # Options: 18, 24, 30 OLDIBpp0[0] = 24 OLDIBpp1[0] = 24 # Set RGB mode Bits Per Pixel (Ignored in OLDI mode) RGBBpp[0] = 24 # Select video source for OLDI/RGB output # Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. # For Dual OLDI, use same stream for both ports # OLDI_Port1_Source is ignored for single OLDI port 0 or RGB mode # OLDI_RGB_Port0_Source is ignored for single OLDI port 1 mode # 0 = Stream 0 # 1 = Stream 1 # 2 = Stream 2 # 3 = Stream 3 OLDI_RGB_Port0_Source[0] = 0 OLDI_Port1_Source[0] = 0 """ ##################################### DES1 (Second Deserialzier) Configurations - Ignored for FPD III Modes For Y-split (Independent FPD IV) configurations, DES1 is the device attached to SER TX port 1 For single port 1 FPD IV configurations, this is the device attached to SER TX port 1 ##################################### """ # Des_Device # Only used for FPD IV deserializer configurations - ignore if using FPD III deserializer # Options 984, 988 Des_Device[1] = "988" # Set the deserializer Daisy Chain TX FPD port configuration # Options: # Daisy Chaining Disabled = 0 # FPD4 Dual = 1 # FPD4 Single Port 0 = 2 # FPD4 Single Port 1 = 3 # Net yet functional # FPD4 Independent = 4 # Net yet functional # FPD3 Dual = 5 # FPD3 Single Port 0 = 6 # FPD3 Single Port 1 = 7 # FPD3 Independent = 8 # FPD4 Port 0/FPD3 Port 1 = 9 # Net yet functional # FPD3 Port 0/FPD4 Port 1 = 10 # Net yet functional DaisyConf[1] = 0 # Enable daisy chain TX forwarding for deserializer 1 (second DES in the chain) # Set VPs 0-4 = 1 to enable forwarding of that VP to the next DES # If all VP forwarding is set to 0, then daisy chaining is disabled # Example: Forward only VP0 to the next DES: Des1_DaisyVPs = [1,0,0,0] # Example Forward VP1 and VP2 to the next DES: Des1_DaisyVPs = [0,1,1,0] Des1_DaisyVPs = [0,0,0,0] # Set which VP is forwarded to chain chain output in FPD III mode # FPD3DaisyVP_P0 controls daisy chain FPD port 0 # FPD3DaisyVP_P1 controls daisy chain FPD port 1 # FPD3DaisyVP_P0 and FPD3DaisyVP_P1 must be set to the same VP for dual FPD III mode # Setting the daisy chain output to FPD III mode terminates the daisy chain at the connected deserializer # This is ignored if the daisy chain is set up for FPD IV output mode # Example: Forward VP1 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 1 # Example: Forward VP3 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 3 FPD3DaisyVP_P0[1] = 2 FPD3DaisyVP_P1[1] = 2 # FPD4 Rate Selection for DES1 Daisy Chain TX (Gbps) # Ignored if the port is set to FPD3 mode # FPD4RateDaisy0[1] sets DES1 Daisy Chain TX Port 0 # FPD4RateDaisy1[1] sets DES1 Daisy Chain TX Port 1 # Options: 3.375, 6.75, 10.8, 13.5, 12.528 FPD4RateDaisy0[1] = 6.75 FPD4RateDaisy1[1] = 6.75 # FPD BC SSCG Configuration # SSCG options for the deserializer back channel output # Options: # 0 = Disable SSCG on FPD back channel interface # 1 = Enable SSCG with Center Spread # 2 = Enable SSCG with Down Spread DES_BC_SSCG[1] = 0 # FPD BC SSCG FDEV % # Ignored is DES_BC_SSCG = 0 # Sets the SSCG frequency deviation percentage for FPD back channel interface SSCG # Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread # Options: 0-0.5 (%) in Center Spread Mode # Options: 0-0.25 (%) in Down Spread Mode DES_BC_SSCG_FDEV[1] = 0.25 # FPD SSCG FMOD kHz # Ignored is DES_BC_SSCG = 0 # Set the SSCG modulation frequency for FPD back channel interface SSCG # Options: 30-33 (kHz) DES_BC_SSCG_FMOD[1] = 33 # Display SSCG Configuration # SSCG options for the deserializer display output (OLDI or DP/eDP Interface) # This is independent of the FPD-Link SSCG # Options: # 0 = Disable SSCG on display interface # 1 = Enable SSCG with Center Spread # 2 = Enable SSCG with Down Spread DES_Display_SSCG[1] = 0 # Display SSCG FDEV % # Ignored is DES_Display_SSCG = 0 # Sets the SSCG frequency deviation percentage for display interface SSCG # Options: 0-6 (%) for 988 in Center Spread Mode (+/-3%) # Options: 0-3 (%) for 988 in Down Spread Mode # Options: 0-0.5 (%) for 984 (Down Spread Only) DES_Display_SSCG_FDEV[1] = 1 # Display SSCG FMOD kHz # Ignored is DES_Display_SSCG = 0 # Set the SSCG modulation frequency for display interface SSCG # Options: 10-100 (kHz) for 988 # Options: 30-33 (kHz) for 984 DES_Display_SSCG_FMOD[1] = 10 """ ##################################### DES1 (Second Deserialzier) Configurations ##################################### """ """ DES1 984 Configs - Ignored if using 988 """ #Select DP ports to be enabled # Enabled = 1, Disabled = 0 DP0_ON[1] = 1 DP1_ON[1] = 0 #Select video source for DP output #Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. # 0 = Stream 0 # 1 = Stream 1 # 2 = Stream 2 # 3 = Stream 3 DP_Output_0_Source[1] = 1 DP_Output_1_Source[1] = 1 # Select DP output lane rate and number of lanes # Options (in Gbps): # 1.62 # 2.7 # 5.4 # 8.1 DP_Rate[1] = 1.62 DP_Lane_Num[1] = 4 """ DES1 988 Configs - Ignored if using 984 """ # Select OLDI or RGB mode # Options: # 1 = RGB Mode Enabled # 0 = OLDI Mode RGBMode[1] = 0 # Select OLDI port configuration (Ignored for RGB mode) # Options: # 0 = Single OLDI port 0 # 1 = Single OLDI port 1 # 2 = Dual OLDI # 3 = Dual OLDI Swap OLDIEnabled[1] = 2 # Select MAPSEL Setting for port 0 and port 1 (Ignored for RGB mode) # 0 = MAPSEL = L (LSB on D3/D4) # 1 = MAPSEL = H (MSB on D3/D4) MAPSEL0[1] = 1 MAPSEL1[1] = 1 # Set OLDI Bits Per Pixel for port 0 and 1 (Ignored in RGB mode) # Options: 18, 24, 30 OLDIBpp0[1] = 24 OLDIBpp1[1] = 24 # Set RGB mode Bits Per Pixel (Ignored in OLDI mode) RGBBpp[1] = 24 # Select video source for OLDI/RGB output # Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. # For Dual OLDI, use same stream for both ports # OLDI_Port1_Source is ignored for single OLDI port 0 or RGB mode # OLDI_RGB_Port0_Source is ignored for single OLDI port 1 mode # 0 = Stream 0 # 1 = Stream 1 # 2 = Stream 2 # 3 = Stream 3 OLDI_RGB_Port0_Source[1] = 0 OLDI_Port1_Source[1] = 0 """ ##################################### DES2 (Third Deserialzier) Configurations ##################################### """ # Des_Device # Only used for FPD IV deserializer configurations - ignore if using FPD III deserializer # Options 984, 988 Des_Device[2] = "988" # Set the deserializer Daisy Chain TX FPD port configuration # Options: # Daisy Chaining Disabled = 0 # FPD4 Dual = 1 # FPD4 Single Port 0 = 2 # FPD4 Single Port 1 = 3 # Net yet functional # FPD4 Independent = 4 # Net yet functional # FPD3 Dual = 5 # FPD3 Single Port 0 = 6 # FPD3 Single Port 1 = 7 # FPD3 Independent = 8 # FPD4 Port 0/FPD3 Port 1 = 9 # Net yet functional # FPD3 Port 0/FPD4 Port 1 = 10 # Net yet functional DaisyConf[2] = 0 # Enable daisy chain TX forwarding for deserializer 2 (third DES in the chain) # Set VPs 0-4 = 1 to enable forwarding of that VP to the next DES # If all VP forwarding is set to 0, then daisy chaining is disabled # Example: Forward only VP0 to the next DES: Des2_DaisyVPs = [1,0,0,0] # Example Forward VP1 and VP2 to the next DES: Des2_DaisyVPs = [0,1,1,0] Des2_DaisyVPs = [0,0,0,1] # Set which VP is forwarded to chain chain output in FPD III mode # FPD3DaisyVP_P0 controls daisy chain FPD port 0 # FPD3DaisyVP_P1 controls daisy chain FPD port 1 # FPD3DaisyVP_P0 and FPD3DaisyVP_P1 must be set to the same VP for dual FPD III mode # Setting the daisy chain output to FPD III mode terminates the daisy chain at the connected deserializer # This is ignored if the daisy chain is set up for FPD IV output mode # Example: Forward VP1 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 1 # Example: Forward VP3 to Daisy Chain Output in FPD III mode: FPD3DaisyVP[0] = 3 FPD3DaisyVP_P0[2] = 1 FPD3DaisyVP_P1[2] = 1 # FPD4 Rate Selection for DES2 Daisy Chain TX (Gbps) # Ignored if the port is set to FPD3 mode # FPD4RateDaisy0[2] sets DES2 Daisy Chain TX Port 0 # FPD4RateDaisy1[2] sets DES2 Daisy Chain TX Port 1 # Options: 3.375, 6.75, 10.8, 13.5, 12.528 FPD4RateDaisy0[2] = 10.8 FPD4RateDaisy1[2] = 10.8 # FPD BC SSCG Configuration # SSCG options for the deserializer back channel output # Options: # 0 = Disable SSCG on FPD back channel interface # 1 = Enable SSCG with Center Spread # 2 = Enable SSCG with Down Spread DES_BC_SSCG[2] = 0 # FPD BC SSCG FDEV % # Ignored is DES_BC_SSCG = 0 # Sets the SSCG frequency deviation percentage for FPD back channel interface SSCG # Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread # Options: 0-0.5 (%) in Center Spread Mode # Options: 0-0.25 (%) in Down Spread Mode DES_BC_SSCG_FDEV[2] = 0.25 # FPD SSCG FMOD kHz # Ignored is DES_BC_SSCG = 0 # Set the SSCG modulation frequency for FPD back channel interface SSCG # Options: 30-33 (kHz) DES_BC_SSCG_FMOD[2] = 33 # Display SSCG Configuration # SSCG options for the deserializer display output (OLDI or DP/eDP Interface) # This is independent of the FPD-Link SSCG # Options: # 0 = Disable SSCG on display interface # 1 = Enable SSCG with Center Spread # 2 = Enable SSCG with Down Spread DES_Display_SSCG[2] = 0 # Display SSCG FDEV % # Ignored is DES_Display_SSCG = 0 # Sets the SSCG frequency deviation percentage for display interface SSCG # Options: 0-6 (%) for 988 in Center Spread Mode (+/-3%) # Options: 0-3 (%) for 988 in Down Spread Mode # Options: 0-0.5 (%) for 984 (Down Spread Only) DES_Display_SSCG_FDEV[2] = 1 # Display SSCG FMOD kHz # Ignored is DES_Display_SSCG = 0 # Set the SSCG modulation frequency for display interface SSCG # Options: 10-100 (kHz) for 988 # Options: 30-33 (kHz) for 984 DES_Display_SSCG_FMOD[2] = 50 """ DES2 984 Configs - Ignored if using 988 """ #Select DP ports to be enabled # Enabled = 1, Disabled = 0 DP0_ON[2] = 1 DP1_ON[2] = 0 #Select video source for DP output #Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. # 0 = Stream 0 # 1 = Stream 1 # 2 = Stream 2 # 3 = Stream 3 DP_Output_0_Source[2] = 2 DP_Output_1_Source[2] = 1 # Select DP output lane rate and number of lanes # Options (in Gbps): # 1.62 # 2.7 # 5.4 # 8.1 DP_Rate[2] = 2.7 DP_Lane_Num[2] = 4 """ DES2 988 Configs - Ignored if using 984 """ # Select OLDI or RGB mode # Options: # 1 = RGB Mode Enabled # 0 = OLDI Mode RGBMode[2] = 0 # Select OLDI port configuration (Ignored for RGB mode) # Options: # 0 = Single OLDI port 0 # 1 = Single OLDI port 1 # 2 = Dual OLDI # 3 = Dual OLDI Swap OLDIEnabled[2] = 0 # Select MAPSEL Setting for port 0 and port 1 (Ignored for RGB mode) # 0 = MAPSEL = L (LSB on D3/D4) # 1 = MAPSEL = H (MSB on D3/D4) MAPSEL0[2] = 1 MAPSEL1[2] = 1 # Set OLDI Bits Per Pixel for port 0 and 1 (Ignored in RGB mode) # Options: 18, 24, 30 OLDIBpp0[2] = 24 OLDIBpp1[2] = 24 # Set RGB mode Bits Per Pixel (Ignored in OLDI mode) RGBBpp[2] = 24 # Select video source for OLDI/RGB output # Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. # For Dual OLDI, use same stream for both ports # OLDI_Port1_Source is ignored for single OLDI port 0 or RGB mode # OLDI_RGB_Port0_Source is ignored for single OLDI port 1 mode # 0 = Stream 0 # 1 = Stream 1 # 2 = Stream 2 # 3 = Stream 3 OLDI_RGB_Port0_Source[2] = 2 OLDI_Port1_Source[2] = 2 """ ##################################### DES3 (Fourth Deserialzier) Configurations ##################################### """ # Des_Device # Only used for FPD IV deserializer configurations - ignore if using FPD III deserializer # Options 984, 988 Des_Device[3] = "984" # FPD BC SSCG Configuration # SSCG options for the deserializer back channel output # Options: # 0 = Disable SSCG on FPD back channel interface # 1 = Enable SSCG with Center Spread # 2 = Enable SSCG with Down Spread DES_BC_SSCG[3] = 1 # FPD BC SSCG FDEV % # Ignored is DES_BC_SSCG = 0 # Sets the SSCG frequency deviation percentage for FPD back channel interface SSCG # Note: Combined FPD FC and BC FDEV should not exceed 0.5% for center spread or 0.25% for down spread # Options: 0-0.5 (%) in Center Spread Mode # Options: 0-0.25 (%) in Down Spread Mode DES_BC_SSCG_FDEV[3] = 0.25 # FPD SSCG FMOD kHz # Ignored is DES_BC_SSCG = 0 # Set the SSCG modulation frequency for FPD back channel interface SSCG # Options: 30-33 (kHz) DES_BC_SSCG_FMOD[3] = 33 # Display SSCG Configuration # SSCG options for the deserializer display output (OLDI or DP/eDP Interface) # This is independent of the FPD-Link SSCG # Options: # 0 = Disable SSCG on display interface # 1 = Enable SSCG with Center Spread # 2 = Enable SSCG with Down Spread DES_Display_SSCG[3] = 0 # Display SSCG FDEV % # Ignored is DES_Display_SSCG = 0 # Sets the SSCG frequency deviation percentage for display interface SSCG # Options: 0-6 (%) for 988 in Center Spread Mode (+/-3%) # Options: 0-3 (%) for 988 in Down Spread Mode # Options: 0-0.5 (%) for 984 (Down Spread Only) DES_Display_SSCG_FDEV[3] = 1 # Display SSCG FMOD kHz # Ignored is DES_Display_SSCG = 0 # Set the SSCG modulation frequency for display interface SSCG # Options: 10-100 (kHz) for 988 # Options: 30-33 (kHz) for 984 DES_Display_SSCG_FMOD[3] = 50 """ DES3 984 Configs - Ignored if using 988 """ #Select DP ports to be enabled # Enabled = 1, Disabled = 0 DP0_ON[3] = 1 DP1_ON[3] = 0 #Select video source for DP output #Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. # 0 = Stream 0 # 1 = Stream 1 # 2 = Stream 2 # 3 = Stream 3 DP_Output_0_Source[3] = 3 DP_Output_1_Source[3] = 1 # Select DP output lane rate and number of lanes # Options (in Gbps): # 1.62 # 2.7 # 5.4 # 8.1 DP_Rate[3] = 2.7 DP_Lane_Num[3] = 4 """ DES3 988 Configs - Ignored if using 984 """ # Select OLDI or RGB mode # Options: # 1 = RGB Mode Enabled # 0 = OLDI Mode RGBMode[3] = 0 # Select OLDI port configuration (Ignored for RGB mode) # Options: # 0 = Single OLDI port 0 # 1 = Single OLDI port 1 # 2 = Dual OLDI # 3 = Dual OLDI Swap OLDIEnabled[3] = 2 # Select MAPSEL Setting for port 0 and port 1 (Ignored for RGB mode) # 0 = MAPSEL = L (LSB on D3/D4) # 1 = MAPSEL = H (MSB on D3/D4) MAPSEL0[3] = 1 MAPSEL1[3] = 1 # Set OLDI Bits Per Pixel for port 0 and 1 (Ignored in RGB mode) # Options: 18, 24, 30 OLDIBpp0[3] = 24 OLDIBpp1[3] = 24 # Set RGB mode Bits Per Pixel (Ignored in OLDI mode) RGBBpp[3] = 24 # Select video source for OLDI/RGB output # Ser VP0 is mapped to Stream 0, Ser VP1 is mapped to Stream 1, and etc. # For Dual OLDI, use same stream for both ports # OLDI_Port1_Source is ignored for single OLDI port 0 or RGB mode # OLDI_RGB_Port0_Source is ignored for single OLDI port 1 mode # 0 = Stream 0 # 1 = Stream 1 # 2 = Stream 2 # 3 = Stream 3 OLDI_RGB_Port0_Source[3] = 1 OLDI_Port1_Source[3] = 1
981配置ALP生成代码：
## TI Confidential - NDA Restrictions
##
## Copyright 2018 Texas Instruments Incorporated. All rights reserved.
##
## IMPORTANT: Your use of this Software is limited to those specific rights
## granted under the terms of a software license agreement between the user who
## downloaded the software, his/her employer (which must be your employer) and
## Texas Instruments Incorporated (the License). You may not use this Software
## unless you agree to abide by the terms of the License. The License limits your
## use, and you acknowledge, that the Software may not be modified, copied or
## distributed unless embedded on a Texas Instruments microcontroller which is
## integrated into your product. Other than for the foregoing purpose, you may
## not use, reproduce, copy, prepare derivative works of, modify, distribute,
## perform, display or sell this Software and/or its documentation for any
## purpose.
##
## YOU FURTHER ACKNOWLEDGE AND AGREE THAT THE SOFTWARE AND DOCUMENTATION ARE
## PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED,
## INCLUDING WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY, TITLE,
## NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TEXAS
## INSTRUMENTS OR ITS LICENSORS BE LIABLE OR OBLIGATED UNDER CONTRACT,
## NEGLIGENCE, STRICT LIABILITY, CONTRIBUTION, BREACH OF WARRANTY, OR OTHER LEGAL
## EQUITABLE THEORY ANY DIRECT OR INDIRECT DAMAGES OR EXPENSES INCLUDING BUT NOT
## LIMITED TO ANY INCIDENTAL, SPECIAL, INDIRECT, PUNITIVE OR CONSEQUENTIAL
## DAMAGES, LOST PROFITS OR LOST DATA, COST OF PROCUREMENT OF SUBSTITUTE GOODS,
## TECHNOLOGY, SERVICES, OR ANY CLAIMS BY THIRD PARTIES (INCLUDING BUT NOT
## LIMITED TO ANY DEFENSE THEREOF), OR OTHER SIMILAR COSTS.
##
## Should you have any questions regarding your right to use this Software,
## contact Texas Instruments Incorporated at www.TI.com.
##
## DS90Ux98x-Q1 Auto Script Generation Output
## Tool Version 3.3
import time
## Serializer: DS90Ux981-Q1
## User Inputs:
## Serializer I2C Address= 0x18
## Port 0 DSI Lanes = 4
## Port 0 DSI Rate = 372 Mbps/lane
## Port 1 DSI Lanes = 4
## Port 1 DSI Rate = 372 Mbps/lane
## FPD-Link Configuration: FPD-Link IV Single Port 0 - 6.75Gbps
## Number of Displays = 1
## Video Processor 0 Properties:
## Total Horizontal Pixels = 1376
## Total Vertical Lines = 768
## Active Horizontal Pixels = 1280
## Active Vertical Lines = 720
## Horizontal Back Porch = 48
## Vertical Back Porch = 8
## Horizontal Sync = 32
## Vertical Sync = 4
## Horizontal Front Porch = 16
## Vertical Front Porch = 36
## Horizontal Sync Polarity = Positive
## Vertical Sync Polarity = Positive
## Bits per pixel = 24
## Pixel Clock = 62MHz
## PATGEN Disabled
## Deserializer 0: DS90Ux988-Q1
## Note: The 988 should be strapped to 6.75Gbps FPD IV mode using MODE_SEL0
## User Inputs:
## Deserializer I2C Address = 0x58
## Deserializer I2C Alias = 0x58
## FPD BC SSCG Enabled:
## Spread Type: Center
## fMOD = 33kHz
## fDEV = 0.25%
## Daisy Chain Output Enabled
## Daisy Chain Output Mode: FPD IV Single Port 0 - 6.75Gbps
## 988 OLDI Output Mode
## Single OLDI Port 0
## OLDI Port 0 Bpp = 24
## OLDI Port 0 MAPSEL = H (MSB on D3/D4)
## OLDI Port 0 Video Source = Serializer Stream 0
## OLDI PATGEN Disabled
## Deserializer 1: DS90Ux988-Q1
## Note: The 988 should be strapped to 6.75Gbps FPD IV mode using MODE_SEL0
## User Inputs:
## Deserializer I2C Address = 0x58
## Deserializer I2C Alias = 0x62
## 988 OLDI Output Mode
## Dual OLDI Mode
## OLDI Port 0 Bpp = 24
## OLDI Port 1 Bpp = 24
## OLDI Port 0 MAPSEL = H (MSB on D3/D4)
## OLDI Port 1 MAPSEL = H (MSB on D3/D4)
## Dual OLDI Video Source = Serializer Stream 0
## OLDI PATGEN Disabled
## *********************************************
## Set up Variables
## *********************************************
serAddr = 0x18
desAddr0 = 0x58
desAlias0 = 0x58
des_daisy1_Addr = 0x58
des_daisy1_Alias = 0x62
board.WriteI2C(serAddr,0x70,desAddr0)
board.WriteI2C(serAddr,0x78,desAlias0)
board.WriteI2C(serAddr,0x88,0x0)
board.WriteI2C(serAddr,0x72,des_daisy1_Addr)
board.WriteI2C(serAddr,0x7A,des_daisy1_Alias)
board.WriteI2C(serAddr,0x8a,0x1)
## *********************************************
## Program DSI Configs
## *********************************************
Reg_value = board.ReadI2C(serAddr,0x2,1)
Reg_value = Reg_value | 0x8
board.WriteI2C(serAddr,0x2,Reg_value) #Disable DSI
board.WriteI2C(serAddr,0x2d,0x1) #Select port 0
board.WriteI2C(serAddr,0x40,0x10) #Change indirect page to page 4
board.WriteI2C(serAddr,0x41,0x5)
board.WriteI2C(serAddr,0x42,0x6) #Port 0 TSKIP value:3
Reg_value = board.ReadI2C(serAddr,0x4f,1)
Reg_value = Reg_value & 0x73
Reg_value = Reg_value | 0x8c
board.WriteI2C(serAddr,0x4f,Reg_value) #Set number of lanes and continuous or non-continuous
board.WriteI2C(serAddr,0x2d,0x12) #Select port 1
board.WriteI2C(serAddr,0x40,0x18) #Change indirect page to page 6
board.WriteI2C(serAddr,0x41,0x5)
board.WriteI2C(serAddr,0x42,0x6) #Port 1 TSKIP value:3
Reg_value = board.ReadI2C(serAddr,0x4f,1)
Reg_value = Reg_value & 0x73
Reg_value = Reg_value | 0x8c
board.WriteI2C(serAddr,0x4f,Reg_value) #Set number of lanes and continuous or non-continuous
board.WriteI2C(serAddr,0x2d,0x3) #Select write port 0 and 1
board.WriteI2C(serAddr,0xbd,0x20) #Set DSI source for the Video processors 0 and 1
board.WriteI2C(serAddr,0xbe,0x0) #Set DSI source for the Video processors 2 and 3
board.WriteI2C(serAddr,0x2d,0x1) #Select port 0
## *********************************************
## Program SER to FPD-Link IV mode
## *********************************************
board.WriteI2C(serAddr,0x5b,0x23) #Disable FPD3 FIFO pass through
board.WriteI2C(serAddr,0x5,0x2c) #Force FPD4_TX single port 0 mode
## *********************************************
## Set up FPD IV PLL Settings - This section can be commented out to improve bringup time if 983/981 MODE_SEL0 and MODE_SEL2 are strapped to the correct FPD IV speed
## *********************************************
board.WriteI2C(serAddr,0x40,0x8) #Select PLL reg page
board.WriteI2C(serAddr,0x41,0x1b)
board.WriteI2C(serAddr,0x42,0x8) #Disable PLL0
board.WriteI2C(serAddr,0x41,0x5b)
board.WriteI2C(serAddr,0x42,0x8) #Disable PLL1
board.WriteI2C(serAddr,0x2,0xd1) #Enable mode overwrite
board.WriteI2C(serAddr,0x2d,0x1)
board.WriteI2C(serAddr,0x40,0x24)
board.WriteI2C(serAddr,0x41,0x84)
board.WriteI2C(serAddr,0x42,0x2) #Switch encoder from ADAS to IVI on port 0
board.WriteI2C(serAddr,0x40,0x8) #Select PLL page
board.WriteI2C(serAddr,0x41,0x5) #Select Ncount Reg
board.WriteI2C(serAddr,0x42,0x7d) #Set Ncount
board.WriteI2C(serAddr,0x41,0x13) #Select post div reg
board.WriteI2C(serAddr,0x42,0x90) #Set post div for 6.75 Gbps
board.WriteI2C(serAddr,0x2d,0x1) #Select write reg to port 0
board.WriteI2C(serAddr,0x6a,0xa) #set BC sampling rate
board.WriteI2C(serAddr,0x6e,0x80) #set BC fractional sampling
board.WriteI2C(serAddr,0x40,0x4) #Select FPD page and set BC settings for FPD IV port 0
board.WriteI2C(serAddr,0x41,0x6)
board.WriteI2C(serAddr,0x42,0x0)
board.WriteI2C(serAddr,0x41,0xd)
board.WriteI2C(serAddr,0x42,0x34)
board.WriteI2C(serAddr,0x41,0xe)
board.WriteI2C(serAddr,0x42,0x53)
board.WriteI2C(serAddr,0x2,0x51) #Set HALFRATE_MODE
## *********************************************
## Zero out PLL fractional - This section can be commented out to improve bringup time if 983/981 MODE_SEL0 and MODE_SEL2 are strapped to the correct FPD IV speed
## *********************************************
board.WriteI2C(serAddr,0x40,0x8) #Select PLL page
board.WriteI2C(serAddr,0x41,0x4)
board.WriteI2C(serAddr,0x42,0x1)
board.WriteI2C(serAddr,0x41,0x1e)
board.WriteI2C(serAddr,0x42,0x0)
board.WriteI2C(serAddr,0x41,0x1f)
board.WriteI2C(serAddr,0x42,0x0)
board.WriteI2C(serAddr,0x41,0x20)
board.WriteI2C(serAddr,0x42,0x0)
## *********************************************
## Configure and Enable PLLs - This section can be commented out to improve bringup time if 983/981 MODE_SEL0 and MODE_SEL2 are strapped to the correct FPD IV speed
## *********************************************
board.WriteI2C(serAddr,0x41,0xe) #Select VCO reg
board.WriteI2C(serAddr,0x42,0xc7) #Set VCO
board.WriteI2C(serAddr,0x1,0x30) #soft reset PLL
board.WriteI2C(serAddr,0x41,0x1b)
board.WriteI2C(serAddr,0x42,0x0) #Enable PLL0
board.WriteI2C(serAddr,0x1,0x1) #soft reset Ser
time.sleep(0.04)
## *********************************************
## Enable I2C Passthrough
## *********************************************
I2C_PASS_THROUGH = board.ReadI2C(serAddr,0x7,1)
I2C_PASS_THROUGH_MASK = 0x08
I2C_PASS_THROUGH_REG = I2C_PASS_THROUGH | I2C_PASS_THROUGH_MASK
board.WriteI2C(serAddr,0x07,I2C_PASS_THROUGH_REG) #Enable I2C Passthrough
board.WriteI2C(desAlias0,0x1,0x1) #Soft reset Des
time.sleep(0.04)
board.WriteI2C(serAddr,0x2d,0x1) #Select write to port0 reg
## *********************************************
## Program VP Configs
## *********************************************
# Configure VP 0
board.WriteI2C(serAddr,0x40,0x32)
board.WriteI2C(serAddr,0x41,0x2)
board.WriteI2C(serAddr,0x42,0x0) #VID H Active
board.WriteI2C(serAddr,0x42,0x5) #VID H Active
board.WriteI2C(serAddr,0x41,0x10)
board.WriteI2C(serAddr,0x42,0x0) #Horizontal Active
board.WriteI2C(serAddr,0x42,0x5) #Horizontal Active
board.WriteI2C(serAddr,0x42,0x30) #Horizontal Back Porch
board.WriteI2C(serAddr,0x42,0x0) #Horizontal Back Porch
board.WriteI2C(serAddr,0x42,0x20) #Horizontal Sync
board.WriteI2C(serAddr,0x42,0x0) #Horizontal Sync
board.WriteI2C(serAddr,0x42,0x60) #Horizontal Total
board.WriteI2C(serAddr,0x42,0x5) #Horizontal Total
board.WriteI2C(serAddr,0x42,0xd0) #Vertical Active
board.WriteI2C(serAddr,0x42,0x2) #Vertical Active
board.WriteI2C(serAddr,0x42,0x8) #Vertical Back Porch
board.WriteI2C(serAddr,0x42,0x0) #Vertical Back Porch
board.WriteI2C(serAddr,0x42,0x4) #Vertical Sync
board.WriteI2C(serAddr,0x42,0x0) #Vertical Sync
board.WriteI2C(serAddr,0x42,0x24) #Vertical Front Porch
board.WriteI2C(serAddr,0x42,0x0) #Vertical Front Porch
board.WriteI2C(serAddr,0x41,0x27)
board.WriteI2C(serAddr,0x42,0x0) #HSYNC Polarity = +, VSYNC Polarity = +
board.WriteI2C(serAddr,0x41,0x23) #M/N Register
board.WriteI2C(serAddr,0x42,0xc2) #M value
board.WriteI2C(serAddr,0x42,0xb) #M value
board.WriteI2C(serAddr,0x42,0xf) #N value
## *********************************************
## Enable VPs
## *********************************************
board.WriteI2C(serAddr,0x43,0x0) #Set number of VPs used = 1
board.WriteI2C(serAddr,0x44,0x1) #Enable video processors
## *********************************************
## Configure Serializer TX Link Layer
## *********************************************
board.WriteI2C(serAddr,0x40,0x2e) #Link layer Reg page
board.WriteI2C(serAddr,0x41,0x1) #Link layer 0 stream enable
board.WriteI2C(serAddr,0x42,0x1) #Link layer 0 stream enable
board.WriteI2C(serAddr,0x41,0x6) #Link layer 0 time slot 0
board.WriteI2C(serAddr,0x42,0x41) #Link layer 0 time slot
board.WriteI2C(serAddr,0x41,0x20) #Set Link layer vp bpp
board.WriteI2C(serAddr,0x42,0x55) #Set Link layer vp bpp according to VP Bit per pixel
board.WriteI2C(serAddr,0x41,0x0) #Link layer 0 enable
board.WriteI2C(serAddr,0x42,0x3) #Link layer 0 enable
Reg_value = board.ReadI2C(serAddr,0x2,1)
Reg_value = Reg_value & 0xf7
board.WriteI2C(serAddr,0x2,Reg_value) #Enable DSI
## *********************************************
## Configure DES 0 FPD Back Channel SSCG
## *********************************************
board.WriteI2C(desAlias0,0x40,0xa)
board.WriteI2C(desAlias0,0x41,0x5)
board.WriteI2C(desAlias0,0x42,0x7c) #Set NDIV = 124
board.WriteI2C(desAlias0,0x42,0x0) #Set NDIV = 124
board.WriteI2C(desAlias0,0x41,0x18)
board.WriteI2C(desAlias0,0x42,0xf6) #Set DEN = 16777206
board.WriteI2C(desAlias0,0x42,0xff)
board.WriteI2C(desAlias0,0x42,0xff)
board.WriteI2C(desAlias0,0x41,0x1e)
board.WriteI2C(desAlias0,0x42,0xf6) #Set NUM = 16777206
board.WriteI2C(desAlias0,0x42,0xff)
board.WriteI2C(desAlias0,0x42,0xff)
board.WriteI2C(desAlias0,0x41,0x14)
board.WriteI2C(desAlias0,0x42,0xb2) #Set Spread Type = Center and Set RAMPX_INC = 12850
board.WriteI2C(desAlias0,0x41,0x15)
board.WriteI2C(desAlias0,0x42,0x64)
board.WriteI2C(desAlias0,0x41,0x16)
board.WriteI2C(desAlias0,0x42,0xcc) #Set RAMPX_STOP = 204
board.WriteI2C(desAlias0,0x41,0x17)
board.WriteI2C(desAlias0,0x42,0x40)
board.WriteI2C(desAlias0,0x41,0x4)
board.WriteI2C(desAlias0,0x42,0x9) #Set PLL Order to Fractional
board.WriteI2C(desAlias0,0x1,0x1) #Soft Reset Des
time.sleep(0.04)
## *********************************************
## Read Deserializer 0 Temp
## *********************************************
board.WriteI2C(desAlias0,0x40,0x6c)
board.WriteI2C(desAlias0,0x41,0xd)
board.WriteI2C(desAlias0,0x42,0x0)
board.WriteI2C(desAlias0,0x41,0x13)
TEMP_FINAL = board.ReadI2C(desAlias0,0x42,1)
TEMP_FINAL_C = 2*TEMP_FINAL - 273
## *********************************************
## Set up Deserializer 0 Temp Ramp Optimizations
## *********************************************
Efuse_TS_CODE = 2
Ramp_UP_Range_CODES_Needed = int((150-TEMP_FINAL_C)/(190/11)) + 1
Ramp_DN_Range_CODES_Needed = int((TEMP_FINAL_C-30)/(190/11)) + 1
Ramp_UP_CAP_DELTA = Ramp_UP_Range_CODES_Needed - 4
Ramp_DN_CAP_DELTA = Ramp_DN_Range_CODES_Needed - 7
board.WriteI2C(desAlias0,0x40,0x3c)
board.WriteI2C(desAlias0,0x41,0xf5)
board.WriteI2C(desAlias0,0x42,(Efuse_TS_CODE<<4)+1) # Override TS_CODE Efuse Code
if Ramp_UP_CAP_DELTA > 0:
TS_CODE_UP = Efuse_TS_CODE - Ramp_UP_CAP_DELTA
if TS_CODE_UP < 0:
TS_CODE_UP = 0
board.WriteI2C(desAlias0,0x41,0xf5)
rb = board.ReadI2C(desAlias0,0x42,1)
rb &= 0x8F
rb |= (TS_CODE_UP << 4)
board.WriteI2C(desAlias0,0x42,rb)
rb = board.ReadI2C(desAlias0,0x42,1)
rb &= 0xFE
rb |= 0x01
board.WriteI2C(desAlias0,0x42,rb)
board.WriteI2C(desAlias0,0x1,0x1)
time.sleep(0.04)
if Ramp_DN_CAP_DELTA > 0:
TS_CODE_DN = Efuse_TS_CODE + Ramp_DN_CAP_DELTA
if TS_CODE_DN >= 7:
TS_CODE_DN = 7
board.WriteI2C(desAlias0,0x41,0xf5)
rb = board.ReadI2C(desAlias0,0x42,1)
rb &= 0x8F
rb |= (TS_CODE_DN << 4)
board.WriteI2C(desAlias0,0x42,rb)
rb = board.ReadI2C(desAlias0,0x42,1)
rb &= 0xFE
rb |= 0x01
board.WriteI2C(desAlias0,0x42,rb)
board.WriteI2C(desAlias0,0x1,0x1)
time.sleep(0.04)
## *********************************************
## Clear CRC errors from initial link process
## *********************************************
Reg_value = board.ReadI2C(serAddr,0x2,1)
Reg_value = Reg_value | 0x20
board.WriteI2C(serAddr,0x2,Reg_value) #CRC Error Reset
Reg_value = board.ReadI2C(serAddr,0x2,1)
Reg_value = Reg_value & 0xdf
board.WriteI2C(serAddr,0x2,Reg_value) #CRC Error Reset Clear
board.WriteI2C(serAddr,0x2d,0x1)
## *********************************************
## Configure Deserializer TX Layer
## *********************************************
board.WriteI2C(desAlias0,0x40,0x44) #Select TX Link Layer Page
board.WriteI2C(desAlias0,0x41,0x1) #Select LINK0_STREAM_EN
board.WriteI2C(desAlias0,0x42,0x2) #Enable forwarded daisy chain streams
board.WriteI2C(desAlias0,0x41,0x7) #Select LINK0_SLOT_REQ1
board.WriteI2C(desAlias0,0x42,0x41) #Set number of time slots
board.WriteI2C(desAlias0,0x41,0x32)
board.WriteI2C(desAlias0,0x42,0x1) #Set FPD_TX_POL_SEL_EN
board.WriteI2C(desAlias0,0x41,0x30)
board.WriteI2C(desAlias0,0x42,0x0) #Configure FPD_TX_HPOL_CTL
board.WriteI2C(desAlias0,0x41,0x31)
board.WriteI2C(desAlias0,0x42,0x0) #Configure FPD_TX_VPOL_CTL
board.WriteI2C(desAlias0,0x41,0x0) #Link layer enable
board.WriteI2C(desAlias0,0x42,0x3) #Link layer enable
## *********************************************
## Program Des Daisy TX
## *********************************************
board.WriteI2C(desAlias0,0xa8,0x2c) #Enable daisy chain TX_FPD_PORTS
board.WriteI2C(desAlias0,0x5,0xc0) #Set half rate mode for 6.75Gbps daisy chain
board.WriteI2C(desAlias0,0x40,0xc) #Select PLL Reg page
board.WriteI2C(desAlias0,0x41,0x5b) #Select Channel 1 PLL Register
board.WriteI2C(desAlias0,0x42,0x8) #Disable Unused Channel 1 PLL
board.WriteI2C(desAlias0,0x1,0x30) #soft reset Des
time.sleep(0.04)
## *********************************************
## Read Deserializer 1 Temp
## *********************************************
board.WriteI2C(des_daisy1_Alias,0x40,0x6c)
board.WriteI2C(des_daisy1_Alias,0x41,0xd)
board.WriteI2C(des_daisy1_Alias,0x42,0x0)
board.WriteI2C(des_daisy1_Alias,0x41,0x13)
TEMP_FINAL = board.ReadI2C(des_daisy1_Alias,0x42,1)
TEMP_FINAL_C = 2*TEMP_FINAL - 273
## *********************************************
## Set up Deserializer 1 Temp Ramp Optimizations
## *********************************************
Efuse_TS_CODE = 2
Ramp_UP_Range_CODES_Needed = int((150-TEMP_FINAL_C)/(190/11)) + 1
Ramp_DN_Range_CODES_Needed = int((TEMP_FINAL_C-30)/(190/11)) + 1
Ramp_UP_CAP_DELTA = Ramp_UP_Range_CODES_Needed - 4
Ramp_DN_CAP_DELTA = Ramp_DN_Range_CODES_Needed - 7
board.WriteI2C(des_daisy1_Alias,0x40,0x3c)
board.WriteI2C(des_daisy1_Alias,0x41,0xf5)
board.WriteI2C(des_daisy1_Alias,0x42,(Efuse_TS_CODE<<4)+1) # Override TS_CODE Efuse Code
if Ramp_UP_CAP_DELTA > 0:
TS_CODE_UP = Efuse_TS_CODE - Ramp_UP_CAP_DELTA
if TS_CODE_UP < 0:
TS_CODE_UP = 0
board.WriteI2C(des_daisy1_Alias,0x41,0xf5)
rb = board.ReadI2C(des_daisy1_Alias,0x42,1)
rb &= 0x8F
rb |= (TS_CODE_UP << 4)
board.WriteI2C(des_daisy1_Alias,0x42,rb)
rb = board.ReadI2C(des_daisy1_Alias,0x42,1)
rb &= 0xFE
rb |= 0x01
board.WriteI2C(des_daisy1_Alias,0x42,rb)
board.WriteI2C(des_daisy1_Alias,0x1,0x1)
time.sleep(0.04)
if Ramp_DN_CAP_DELTA > 0:
TS_CODE_DN = Efuse_TS_CODE + Ramp_DN_CAP_DELTA
if TS_CODE_DN >= 7:
TS_CODE_DN = 7
board.WriteI2C(des_daisy1_Alias,0x41,0xf5)
rb = board.ReadI2C(des_daisy1_Alias,0x42,1)
rb &= 0x8F
rb |= (TS_CODE_DN << 4)
board.WriteI2C(des_daisy1_Alias,0x42,rb)
rb = board.ReadI2C(des_daisy1_Alias,0x42,1)
rb &= 0xFE
rb |= 0x01
board.WriteI2C(des_daisy1_Alias,0x42,rb)
board.WriteI2C(des_daisy1_Alias,0x1,0x1)
time.sleep(0.04)
## *********************************************
## Hold Des DTG in reset
## *********************************************
board.WriteI2C(desAlias0,0x40,0x50) #Select DTG Page
board.WriteI2C(desAlias0,0x41,0x32)
board.WriteI2C(desAlias0,0x42,0x6) #Hold Local Display Output Port 0 DTG in Reset
board.WriteI2C(desAlias0,0x41,0x62)
board.WriteI2C(desAlias0,0x42,0x6) #Hold Local Display Output Port 1 DTG in Reset
## *********************************************
## Disable Stream Mapping
## *********************************************
board.WriteI2C(desAlias0,0xe,0x3) #Select both Output Ports
board.WriteI2C(desAlias0,0xd0,0x0) #Disable FPD4 video forward to Output Port
board.WriteI2C(desAlias0,0xd7,0x0) #Disable FPD3 video forward to Output Port
## *********************************************
## Setup DTG for port 0
## *********************************************
board.WriteI2C(desAlias0,0x40,0x50) #Select DTG Page
board.WriteI2C(desAlias0,0x41,0x20)
board.WriteI2C(desAlias0,0x42,0x13) #Set up Local Display DTG BPP, Sync Polarities, and Measurement Type
board.WriteI2C(desAlias0,0x41,0x29) #Set Hstart
board.WriteI2C(desAlias0,0x42,0x80) #Hstart upper byte
board.WriteI2C(desAlias0,0x41,0x2a)
board.WriteI2C(desAlias0,0x42,0x50) #Hstart lower byte
board.WriteI2C(desAlias0,0x41,0x2f) #Set HSW
board.WriteI2C(desAlias0,0x42,0x40) #HSW upper byte
board.WriteI2C(desAlias0,0x41,0x30)
board.WriteI2C(desAlias0,0x42,0x20) #HSW lower byte
## *********************************************
## Map video to display output
## *********************************************
board.WriteI2C(desAlias0,0xe,0x3) #Select both Output Ports
board.WriteI2C(desAlias0,0xd0,0xd) #Enable FPD_RX video forward to Output Port and Enable FPD_RX to Daisy Output 0
board.WriteI2C(desAlias0,0xd1,0xf) #Every stream forwarded on DC
board.WriteI2C(desAlias0,0xd6,0x0) #Send Stream 0 to Output Port 0 and Send Stream 0 to Output Port 1
board.WriteI2C(desAlias0,0xd7,0x0) #FPD3 to local display output mapping disabled
board.WriteI2C(desAlias0,0xe,0x1) #Select Port 0
## *********************************************
## Configure 988 Display
## *********************************************
board.WriteI2C(desAlias0,0x40,0x2c) #Configure OLDI/RGB Port Settings
board.WriteI2C(desAlias0,0x41,0x0)
board.WriteI2C(desAlias0,0x42,0x2f)
board.WriteI2C(desAlias0,0x41,0x1)
board.WriteI2C(desAlias0,0x42,0xc)
board.WriteI2C(desAlias0,0x40,0x2e) #Configure OLDI/RGB PLL
board.WriteI2C(desAlias0,0x41,0x8)
board.WriteI2C(desAlias0,0x42,0x25) #PLL_NUM23_16
board.WriteI2C(desAlias0,0x42,0xed) #PLL_NUM15_8
board.WriteI2C(desAlias0,0x42,0x8) #PLL_NUM7_0
board.WriteI2C(desAlias0,0x42,0xff) #PLL_DEN23_16
board.WriteI2C(desAlias0,0x42,0xff) #PLL_DEN15_8
board.WriteI2C(desAlias0,0x42,0xf6) #PLL_DEN7_0
board.WriteI2C(desAlias0,0x41,0x18)
board.WriteI2C(desAlias0,0x42,0x20) #PLL_NDIV
board.WriteI2C(desAlias0,0x41,0x2d)
board.WriteI2C(desAlias0,0x42,0x11) #TX_SEL_CLKDIV
## *********************************************
## Release Des DTG reset
## *********************************************
board.WriteI2C(desAlias0,0x40,0x50) #Select DTG Page
board.WriteI2C(desAlias0,0x41,0x32)
board.WriteI2C(desAlias0,0x42,0x4) #Release Local Display Output Port 0 DTG
board.WriteI2C(desAlias0,0x41,0x62)
board.WriteI2C(desAlias0,0x42,0x4) #Release Local Display Output Port 1 DTG
## *********************************************
## Enable OLDI Output
## *********************************************
board.WriteI2C(desAlias0,0x1,0x40) #OLDI Reset
board.WriteI2C(desAlias0,0x40,0x2c) #Enable OLDI/RGB
board.WriteI2C(desAlias0,0x41,0x2)
board.WriteI2C(desAlias0,0x42,0x10)
board.WriteI2C(desAlias0,0x41,0x20) #P0 TX_EN
board.WriteI2C(desAlias0,0x42,0x80)
## *********************************************
## Hold Des DTG in reset
## *********************************************
board.WriteI2C(des_daisy1_Alias,0x40,0x50) #Select DTG Page
board.WriteI2C(des_daisy1_Alias,0x41,0x32)
board.WriteI2C(des_daisy1_Alias,0x42,0x6) #Hold Local Display Output Port 0 DTG in Reset
board.WriteI2C(des_daisy1_Alias,0x41,0x62)
board.WriteI2C(des_daisy1_Alias,0x42,0x6) #Hold Local Display Output Port 1 DTG in Reset
## *********************************************
## Disable Stream Mapping
## *********************************************
board.WriteI2C(des_daisy1_Alias,0xe,0x3) #Select both Output Ports
board.WriteI2C(des_daisy1_Alias,0xd0,0x0) #Disable FPD4 video forward to Output Port
board.WriteI2C(des_daisy1_Alias,0xd7,0x0) #Disable FPD3 video forward to Output Port
## *********************************************
## Setup DTG for port 0
## *********************************************
board.WriteI2C(des_daisy1_Alias,0x40,0x50) #Select DTG Page
board.WriteI2C(des_daisy1_Alias,0x41,0x20)
board.WriteI2C(des_daisy1_Alias,0x42,0x53) #Set up Local Display DTG BPP, Sync Polarities, and Measurement Type
board.WriteI2C(des_daisy1_Alias,0x41,0x29) #Set Hstart
board.WriteI2C(des_daisy1_Alias,0x42,0x80) #Hstart upper byte
board.WriteI2C(des_daisy1_Alias,0x41,0x2a)
board.WriteI2C(des_daisy1_Alias,0x42,0x50) #Hstart lower byte
board.WriteI2C(des_daisy1_Alias,0x41,0x2f) #Set HSW
board.WriteI2C(des_daisy1_Alias,0x42,0x40) #HSW upper byte
board.WriteI2C(des_daisy1_Alias,0x41,0x30)
board.WriteI2C(des_daisy1_Alias,0x42,0x20) #HSW lower byte
## *********************************************
## Map video to display output
## *********************************************
board.WriteI2C(des_daisy1_Alias,0xe,0x3) #Select both Output Ports
board.WriteI2C(des_daisy1_Alias,0xd0,0xc) #Enable FPD_RX video forward to Output Port
board.WriteI2C(des_daisy1_Alias,0xd1,0xf) #Every stream forwarded on DC
board.WriteI2C(des_daisy1_Alias,0xd6,0x0) #Send Stream 0 to Output Port 0 and Send Stream 0 to Output Port 1
board.WriteI2C(des_daisy1_Alias,0xd7,0x0) #FPD3 to local display output mapping disabled
board.WriteI2C(des_daisy1_Alias,0xe,0x1) #Select Port 0
## *********************************************
## Configure 988 Display
## *********************************************
board.WriteI2C(des_daisy1_Alias,0x40,0x2c) #Configure OLDI/RGB Port Settings
board.WriteI2C(des_daisy1_Alias,0x41,0x0)
board.WriteI2C(des_daisy1_Alias,0x42,0x2f)
board.WriteI2C(des_daisy1_Alias,0x41,0x1)
board.WriteI2C(des_daisy1_Alias,0x42,0x2f)
board.WriteI2C(des_daisy1_Alias,0x40,0x2e) #Configure OLDI/RGB PLL
board.WriteI2C(des_daisy1_Alias,0x41,0x8)
board.WriteI2C(des_daisy1_Alias,0x42,0x25) #PLL_NUM23_16
board.WriteI2C(des_daisy1_Alias,0x42,0xed) #PLL_NUM15_8
board.WriteI2C(des_daisy1_Alias,0x42,0x8) #PLL_NUM7_0
board.WriteI2C(des_daisy1_Alias,0x42,0xff) #PLL_DEN23_16
board.WriteI2C(des_daisy1_Alias,0x42,0xff) #PLL_DEN15_8
board.WriteI2C(des_daisy1_Alias,0x42,0xf6) #PLL_DEN7_0
board.WriteI2C(des_daisy1_Alias,0x41,0x18)
board.WriteI2C(des_daisy1_Alias,0x42,0x20) #PLL_NDIV
board.WriteI2C(des_daisy1_Alias,0x41,0x2d)
board.WriteI2C(des_daisy1_Alias,0x42,0x12) #TX_SEL_CLKDIV
## *********************************************
## Release Des DTG reset
## *********************************************
board.WriteI2C(des_daisy1_Alias,0x40,0x50) #Select DTG Page
board.WriteI2C(des_daisy1_Alias,0x41,0x32)
board.WriteI2C(des_daisy1_Alias,0x42,0x4) #Release Local Display Output Port 0 DTG
board.WriteI2C(des_daisy1_Alias,0x41,0x62)
board.WriteI2C(des_daisy1_Alias,0x42,0x4) #Release Local Display Output Port 1 DTG
## *********************************************
## Enable OLDI Output
## *********************************************
board.WriteI2C(des_daisy1_Alias,0x1,0x40) #OLDI Reset
board.WriteI2C(des_daisy1_Alias,0x40,0x2c) #Enable OLDI/RGB
board.WriteI2C(des_daisy1_Alias,0x41,0x2)
board.WriteI2C(des_daisy1_Alias,0x42,0x14)
board.WriteI2C(des_daisy1_Alias,0x41,0x2) #Toggle OLDI_SER_EN for Dual OLDI Mode
board.WriteI2C(des_daisy1_Alias,0x42,0x4)
board.WriteI2C(des_daisy1_Alias,0x42,0x14)
board.WriteI2C(des_daisy1_Alias,0x41,0x20) #P0 TX_EN
board.WriteI2C(des_daisy1_Alias,0x42,0x80)
board.WriteI2C(des_daisy1_Alias,0x41,0x22) #P1 TX_EN
board.WriteI2C(des_daisy1_Alias,0x42,0x80)