接口论坛 - 最近的话题

TCA9803: TCA9803DGKT与TCA9803DGKR是否只是大小包装的区别？

Feng xiutao — Thu, 29 Oct 2026 06:29:32 GMT

Part Number: TCA9803

TCA9803DGKT与TCA9803DGKR是否只是大小包装的区别？

AM26LV32E: AM26LV32EMDREP丝印问题

nan panpan — Thu, 29 Oct 2026 01:16:24 GMT

Part Number: AM26LV32E

请问这款产品的2种丝印都是你们的产品吗，是变更了丝印信息吗

DS160PT801: 现在有几个关于DS160PT801芯片问题想咨询下

user4645094 — Wed, 28 Oct 2026 13:54:59 GMT

Part Number: DS160PT801

现在有几个关于DS160PT801芯片问题想咨询下

我们现有一个vpx架构设计，三个独立的RC端引出来三个pcie4.0×4，通过背板加DS160PT801 retimer设备，后面接三个独立的ep设备，

问题1：三个pcie4.0×4可以使用2片DS160PT801芯片么，每片拆成2组pcie×4，第一片2组都用接EP1，EP2，第二片只用一组接EP3，另一组禁用

问题2：现在RC、 EP设备均带100M时钟，但时钟信号未引到背板。如果采用SRNS时钟架构，在背板上加单独时钟只给DS160PT801芯片用，不连接到RC和EP设备上，只接到DS160PT801芯片 REFCLK+、REFCLK- ，将REFCLK_OUT+ / REFCLK_OUT- 悬空可以不

DS320PR1601RSCEVM: 使用DS320PR1601RSCEVM开发板，sigcon不识别（有专用的USB2ANY烧录器）

S S — Wed, 28 Oct 2026 10:24:28 GMT

Part Number: DS320PR1601RSCEVM
Other Parts Discussed in Thread: USB2ANY,

使用DS320PR1601RSCEVM开发板，sigcon不识别（有专用的USB2ANY烧录器）

SN65DSI84: TI-AM62L+SN65DSI84+TIANMA-P1560FHF3MB02 scheme screen display problem

zhidong zhang — Wed, 28 Oct 2026 08:16:23 GMT

Part Number: SN65DSI84

Question background:The main control chip is ti-AM62L, which bridges SN65DSI84 and outputs it to P1560FHF3MB02 Tianma panel, realizing DSI- > dual-channel LVDS display scheme.

Status: In the expectation of normal display, the screen output is pure white/pure red/pure green/pure blue, which flashes alternately. Tianma manufacturer suspected that the parameter configuration error caused the panel to enter the factory mode.
However, through the matching parameters of DSI tuner tools and designating the mode as the test mode, a clear and stable striped test picture is generated at the screen end.

Refer to the experience of ITEM2 forum, When I set the parameters, the corresponding values of Hactive, HFP and HBP doubled.However, whether the parameter value is single or double, the status quo has not improved.

The parameter configuration file of the screen is:Tianma_panel_timing_settings.txt
Tianma_panel_timing_settings.txt
Its DTS file：alientek-am62l-dual-lvds-15.6-FHD.dtso
alientek-am62l-dual-lvds-15.6-FHD.dtso.txt
The specification of the screen：P1560FHF3MB02_Final+Spec_V2.2.pdf
P1560FHF3MB02_Final+Spec_V2.2.pdf

Rag value dump of SN65DSI84 bridge chip:
i2cdump -f -y 3 0x2c
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: 35 38 49 53 44 20 20 20 01 00 85 28 00 01 00 00
10: 26 00 5a 00 00 00 00 00 6c 05 03 00 00 00 00 00
20: 80 07 00 00 38 04 00 00 21 00 00 00 14 00 00 00
30: 06 00 00 00 78 00 14 00 78 00 13 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 40 00 00 80 00 00 00 00 00 00 00 00

At this time, the value is calculated by the register.
REG 0x21=>0x07 ;REG 0x20=>0x80. ==>>Horizontal active：1920

REG 0x0a=>0x85. ==>> Adopt D-PHY clock，010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz

clk：
REG 0x12 =>0x5a. ==>> 450 ≤ frequency < 455 MHz
REG 0x0B =>0x28. ==>> 0101:Divide by 6
75MHz~75.83MHz,Should meet the screen related requirements.

HPW: Horizontal pulse Width:
REG 0x2C =>0x14. ==>> 20

HBP: Horizontal back porch:
REG 0X34 =>0X78. ==>> 120 ???

HFP: Horizontal front porch:
REG 0X38 =>0X78. ==>> 120 ???

There are doubts about these two values.I tried to write a register to halve these two values.No change in phenomenon。

In the test mode, a clear and stable striped test picture is generated, and its register dump is as follows:
i2cdump -f -y 3 0x2c
0 1 2 3 4 5 6 7 8 9 a b c d e f
00: 35 38 49 53 44 20 20 20 01 00 85 28 00 01 00 00
10: 26 00 5a 00 00 00 00 00 6c 00 03 00 00 00 00 00
20: c0 03 00 00 38 04 00 00 20 00 00 00 14 00 00 00
30: 06 00 00 00 3c 00 13 00 3c 00 14 00 10 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 40 00 00 80 00 00 00 00 00 00 00 00

Now, the tracing of this problem is in trouble. Please ask your engineer friends to provide some ideas. Thank you.

DS280DF810: DS280DF810

user4645094 — Wed, 28 Oct 2026 06:15:01 GMT

Part Number: DS280DF810

Dears，

客户这边现在在用DS280DF810来做100G以太网业务的信号整形，想在设计后，想请帮忙看一下设计有无问题，除此之外这个芯片我看是有TI的上位机软件可以直接操作的，我这边想要一下这个上位机及对应的DEMO程序、以及确定一下该款芯片是否需要专门的下载器进行程序烧写。附件为该模块部分的原理图。DS280DF810.pdf

TCA9617: Low-level interference inquiry

Chance Zhan — Wed, 28 Oct 2026 06:07:10 GMT

Part Number: TCA9617

The customer encountered interference with a low-level output on side B of the TCA9617. The specific waveform is as shown below. We'd like to ask if any other customers have experienced similar issues, and also help us understand why this problem might occur？ Here are the topology diagram and waveform diagram.

PCA9306: PCA9306: 1.8 V 电源未供电时被抬升至 2.3 V

liao junyu — Tue, 27 Oct 2026 20:50:44 GMT

Part Number: PCA9306

您好!

我使用PCA9306DCUR将1.8V的IIC信号转换为3.3V。3.3V处由AMS1117 5V转3.3V供电；1.8V处由连接器接受其他电路供电，同时连接到板上其他器件；两侧IIC端口通过前述连接器接入其他电路。
当连接器未连接时，发现原本没有供电的 1.8 V 网络出现 2.3 V 电压。请问是我的原理图设计导致这个问题的吗？应该怎样修改电路以避免这个问题？

下图为原理图

TUSB211A-Q1: TI商务链接&技术窗口链接，请协助。

Angela Zuo — Thu, 22 Oct 2026 03:05:35 GMT

Part Number: TUSB211A-Q1

TPD2S703QDSKRQ1;TUSB211A-Q1;商务链接&技术支持窗口链接。

苏州泰谷科技信息有限公司

SUZHOU TECHGOOD TECHNOLOGY INFORMATION CO,LTD

苏州市工业园区金浦路8号9号楼

Buildings 8 and 9, Jinpu Road, SuZhou industrial park, Jiangsu, China

浙江泰米电子科技有限公司
ZHEJIANG TEME SCIENCE AND TECHNOLOGY CO.,LTD
浙江省海宁市双利路 39 号
No.39 Shuangli Road, Haining City,Zhejiang Prov. China(314400)

TSB81BA3-EP: 这个芯片支持beta模式下的S100，S200,S400,S800吗？

bo ye — Wed, 21 Oct 2026 11:12:31 GMT

Part Number: TSB81BA3-EP

原先我们用的是TSB41BA3ATPFPEP和TM1062TX3DUA，做的支持beta模式下的S100，S200,S400。现在想升级到S800，并且兼容之前的。在网上搜到是TSB81BA3IPFPEP 可以，但是gpt说不行。希望得到技术支持。如果换芯片不行由对应方案也可以。

TPD4E05U06DQAEVM: TPD4E05U06DQAR 丝印前缀代表的含义

XZ Xu — Wed, 21 Oct 2026 02:05:20 GMT

Part Number: TPD4E05U06DQAEVM

帮忙确认TPD4E05U06DQAR 丝印DQA前缀“63”代表的含义，谢谢~

DP83867IR: DP83867 MDIO Stuck High During Power-Up When Two PHYs Share MDIO/MDC

Yan Wang — Mon, 19 Oct 2026 15:05:57 GMT

Part Number: DP83867IR
Other Parts Discussed in Thread: AM6422

Hi TI Team,

We are using two DP83867 PHYs with an AM6422 processor. The two DP83867 devices share the same MDIO and MDC bus.

In our current hardware design, we have placed one 2.2 kΩ pull-up resistor on the MDIO line close to each DP83867 PHY. Therefore, there are two 2.2 kΩ pull-up resistors connected to the same MDIO bus.

We observed the following issue:

During power-up, the Ethernet PHYs sometimes cannot be accessed/communicated with properly.
When the issue occurs, we measured the MDIO signal and found that MDIO stays continuously HIGH.
If we remove one of the 2.2 kΩ MDIO pull-up resistors and leave only one 2.2 kΩ pull-up resistor on the shared MDIO bus, the issue disappears and the PHYs can be accessed successfully after every power-up.

Could you please help clarify the following questions?

For two DP83867 PHYs sharing the same MDIO/MDC bus, should there be only one MDIO pull-up resistor for the entire bus, rather than one pull-up resistor for each PHY?
What is TI's recommended pull-up resistance for MDIO when two DP83867 devices are connected to the same AM6422 MDIO bus?
Does the physical placement of the MDIO pull-up resistor matter? Should it be placed close to the AM6422 MDIO pin, close to one of the PHYs, or is the location generally not critical?
Since two 2.2 kΩ resistors in parallel result in an effective pull-up resistance of approximately 1.1 kΩ, could this pull-up be too strong for the DP83867/AM6422 MDIO interface?
When the failure occurs, MDIO remains HIGH. Could this indicate that the PHY or AM6422 MDIO controller is unable to pull the MDIO line LOW due to the effective pull-up resistance being too low?
Are there any specific power-up, reset, strap, or MDIO timing requirements we should check for this configuration?

Thanks for your support.

TUSB1046-DCI: TUSB1046与TUSB1064对接使用

zhuf — Fri, 16 Oct 2026 09:53:50 GMT

Part Number: TUSB1046-DCI
Other Parts Discussed in Thread: TUSB1064

我想咨询一下，我想做一个HUB控制器，上行口是一个typec接口，支持alt DP和USB3.1，下行口也是一个typec接口（支持dp），我可以使用TUSB1064作为上行口的接收端，然后下行口直接使用TUSB1046再转成typec接口，中间的DP信号可以直连吗？可以这样使用吗？

TUSB1046-DCI: TUSB1046与TUSB1064对接使用

zhuf — Fri, 16 Oct 2026 09:52:22 GMT

Part Number: TUSB1046-DCI
Other Parts Discussed in Thread: TUSB1064

SN75176B: SN75176BDR 测波形异常

?? ? — Fri, 16 Oct 2026 05:05:19 GMT

Part Number: SN75176B

你好

请问，SN75176BDR的产品22年与26年是否有产品升级 ,两个芯片都未墨西哥产地，但是测试波形异常

图片1（纹波异常，不能使用，丝印为75176B 25M AK2G)

图片2（正常使用，丝印为75176B TI48M A34X）

TUSB8042: Device Replacement and Selection Consultation

Chance Zhan — Fri, 16 Oct 2026 04:00:26 GMT

Part Number: TUSB8042

Do we have the RTS5411E P2P or a model that can be used as a replacement?

DS160PR410: DS160PR410RNQT Eye height consistency issue

Peiwu Ren — Thu, 15 Oct 2026 07:35:42 GMT

Part Number: DS160PR410

Hi TI team:

When soldering different chips on the same PCB for measuring eye diagrams, we found significant differences in the eye heights of the chips. (Default state for power on).

At the same time, the eye heights between data lanes are also different. （PCB routing ΔL< 5mil）

Is there a consistent testing report that can be provided to us?

DS160PR410: DS160PR410RNQT Eye height consistency issue

Peiwu Ren — Thu, 15 Oct 2026 07:33:46 GMT

Part Number: DS160PR410

Hi TI team:

When soldering different chips on the same PCB for measuring eye diagrams, we found significant differences in the eye heights of the chips. (Default state for power on).

At the same time, the eye heights between data lanes are also different. （PCB routing ΔL< 5mil）

Is there a consistent testing report that can be provided to us?

DS90UB983-Q1: 资料申请

wayne zhou — Wed, 14 Oct 2026 06:27:33 GMT

Part Number: DS90UB983-Q1

你好，

申请ub983/984资料被拒，如何能够申请到？

FPC202: FPC202 光口控制器问题，无法读取IIC寄存器

YUCHI ZHANG — Sun, 11 Oct 2026 14:00:58 GMT

Part Number: FPC202

FPC202通讯异常文档.docxFPC202通讯异常文档.docx

1、附件原理图（根据参考设计对比，基本一致）

2、在FPC202 输入端的FPGA IIC无法读取。

3、在FPC202 从I2CS_SCL和I2C2_SDA 引线出来，用IIC独立工具，也是只有一次成功，其他只能读取到0F 这个器件地址，但是寄存器无法读写

4，请帮忙分析是什么原因，协助排查，谢谢！

DS15EA101: 急！DS15EA101SQ/NOPB 散热片掉锡是TI原厂工艺问题吗？会影响上机焊锡吗？Is the heat sink solder joint falling off due to TI's original manufacturing process? Will it affect usage?

Renee Chang — Thu, 08 Oct 2026 10:39:32 GMT

Part Number: DS15EA101

如下图，散热片有掉锡的情况，请问会影响性能吗？会影响焊接吗？属于TI原厂的工艺问题吗？

Is the heat sink solder joint falling off due to TI's original manufacturing process? Will it affect usage?

TPS65994AD: The motherboard NANO501 paired with the TPS65994ADRSLR has an issue where there is no display during POST when connected to a TBT monitor。

lemon peng — Thu, 08 Oct 2026 02:16:15 GMT

Part Number: TPS65994AD

The motherboard NANO501 paired with the TPS65994ADRSLR has an issue where there is no display during POST when connected to a TBT monitor, but the display works when entering the system.

Then we also consulted with the Intel FAE about this issue, and the feedback indicated that there was a problem with the PD peak position. The most obvious issue was between PD and the retimer, though other problems were not ruled out. The Intel FAE suggested we contact PD for further investigation.

The current SOC used in NANO501 is MTL-H (4+8) 125H Intel (supporting TBT4), the retimer is JHL9040R, and the PD is TPS65994ADRSLR.
The attached files contain the I2C logs of the captured PD-soc and PD-retimer, along with the PD peak values used. The logs for NANO501 and OPS17 are included separately, with the only difference being the TCP ports connected to the SOC. NANO501 is connected to the SOC's TCP3 port, while OPS17 is connected to the SOC's TCP0 port. OPS17 is connected to a TBT monitor, and the post interface can display the data.

DS560DF410: About DS560DF4100 output swing

Ian Yu — Sat, 03 Oct 2026 13:57:38 GMT

Part Number: DS560DF410

Hi team,

A 12.4416Ghz input signal to the Rx channel.We configured for 24.8832 Gbps NRZ PRBS7 with a differential swing of 1000 mV using the opcodes given below. however, the measured output is only 200 mV and Bit rate is 24.8832Gbps .We have tried tuning the FFE (opcode 0x0C), yet it still stays at just 200 mV. Do you have any suggestions or troubleshooting steps to resolve this?

WIIC 0X30 0X0 0XA2

RIIC 0X30 0X64

after 500

//opcode 0xD2

WIICS 0X30 0X3C 14 0x04,0xA8,0x61,0x0,0x0,0x0,0x1,0x00,0x1F,0x0,0x00,0xB0,0x7B,0x1

WIIC 0X30 0X3B 0XD2

RIIC 0X30 0X64

after 1000

//opcode 0x61

WIICS 0X30 0X3C 3 0x04,0x1,0x0

WIIC 0X30 0X3B 0X61

RIIC 0X30 0X64

afeter 500

//opcode oxC6

WIIC 0X30 0X3C 0X04

WIIC 0X30 0X3B 0XC6

RIICS 0X30 0X6C 2

TPS65994AD: 主板NANO501搭配TPS65994ADRSLR，有一个问题是接TBT显示器时，post无显，进系统有显。

lemon peng — Tue, 29 Sep 2026 07:52:12 GMT

Part Number: TPS65994AD

主板NANO501搭配TPS65994ADRSLR，有一个问题是接TBT显示器时，post无显，进系统有显。

然后这个问题也跟intel FAE咨询了，反馈说是pd峰位有问题，比较明显的是PD到retimer，不排除还有其他问题。Intel FAE建议我们联系pd看下。

NANO501目前使用SOC是MTL-H (4+8) 125H intel（支持TBT4），Retimer是JHL9040R，PD是TPS65994ADRSLR。

附件是抓的pd-soc和pd-retimer的I2C log以及使用的PD峰位。里面分别抓了NANO501和OPS17的log，只是NANO501和OPS17接的SOC 的TCP口不一样，NANO501接的SOC的TCP3口，OPS17接的是SOC的TCP0口。OPS17接TBT显示器，post界面可显。

SN74LVC1G74: Q sometimes show 0V or around 700mV after power-on

xc t — Fri, 25 Sep 2026 00:10:36 GMT

Part Number: SN74LVC1G74

The application circuit of my SN74LVC1G74DCTR latch uses 100K pull-up to 3.3V for D and PRE#, and CLR# is pulled up to 3.3V with a 100nF capacitor to GND. 1. Why does Q sometimes show 0V or around 700mV after power-on? Changing the 100nF to 10nF improves it a bit, but it still happens. 2. Also, what is the output structure of Q and Q# for this device? It seems not to be push-pull.