隔离论坛 - 最近的话题

ISO6041: 请问ISO6041LDWR芯片隔离SPI的工作机制

Abner Ma — Wed, 29 Jul 2026 09:06:16 GMT

Part Number: ISO6041

你好，

ISO6041LDWR，这款芯片隔离25Mhz时钟的SPI通讯，有以下几个问题需要咨询：

1.为什么芯片的通讯速率是200Mbps，但在3.3V电压下，SPI时钟最高只能到25MHz？

2.SPI隔离后，如何保证SPI信号的时钟、数据、片选的时序统一？靠的是芯片内部的时序重整，还是仅靠隔离的低延时去“硬扛”？

3.SPI时钟大于25MHz后，例如30M，50M等，会出现什么问题？

感谢。

RE: ISO6041: 请问ISO6041LDWR芯片隔离SPI的工作机制

Daniel — Wed, 29 Jul 2026 09:42:59 GMT

您好

[FAQ] ISO7741: 如何计算数字隔离器支持的最大 SPI 速度？

www.ti.com.cn/.../zhct386b.pdf

请您参考这个部分说明。

ISO7741: 【选型求助】请问TI是否有专门的SPI隔离器件？

Abner Ma — Wed, 29 Jul 2026 02:13:24 GMT

Part Number: ISO7741

工程师你好，

我们项目上，目前需要隔离ADS7038H的SPI接口，我们的SPI时钟设置为50MHz，目前需要帮忙选型SPI的隔离器件。要求如下：

1.不需要内置隔离电源

2.支持50MHz的SPI时钟

3.4个通道隔离后，各通道的时延偏差要统一

4.隔离耐压不低于3.75kv

另，请问TI若有针对SPI优化的隔离芯片，技术上是怎么做到隔离后时序统一的呢？

RE: ISO7741: 【选型求助】请问TI是否有专门的SPI隔离器件？

Taylor — Wed, 29 Jul 2026 03:38:54 GMT

这个问题，请重新发个帖子

RE: ISO7741: 【选型求助】请问TI是否有专门的SPI隔离器件？

Abner Ma — Wed, 29 Jul 2026 03:33:57 GMT

请问TI的SPI隔离器，内部是有延迟重组处理吗？会不会隔离出来的信号，时序有偏差？

RE: ISO7741: 【选型求助】请问TI是否有专门的SPI隔离器件？

Taylor — Wed, 29 Jul 2026 02:29:41 GMT

下面是按照条件筛选的，但是SPI最高支持到是27MHz

Digital isolators product selection | TI.com

RE: ISO7741: 【选型求助】请问TI是否有专门的SPI隔离器件？

Taylor — Wed, 29 Jul 2026 02:21:32 GMT

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

TINA-TI_SIMP_CHINESE: 缺少模型

SK R — Tue, 14 Jul 2026 09:00:09 GMT

Part Number: TINA-TI_SIMP_CHINESE

没有ISO124的仿真模型

RE: TINA-TI_SIMP_CHINESE: 缺少模型

Taylor — Tue, 14 Jul 2026 09:13:02 GMT

很遗憾，没有ISO124的模型。

类似的，ISO120有PSPICE模型，ISO224有TINA SPICE模型。

RE: TINA-TI_SIMP_CHINESE: 缺少模型

Taylor — Tue, 14 Jul 2026 09:08:03 GMT

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: TINA-TI_SIMP_CHINESE: 缺少模型

Daniel — Tue, 14 Jul 2026 09:06:54 GMT

您好

ISO124的SPICE模型。紧急。- 放大器论坛- 放大器 - TI 端对端支持论坛

请您参考这个帖子说明。

TINA-TI_SIMP_CHINESE: 缺少模型

SK R — Tue, 14 Jul 2026 08:59:04 GMT

Part Number: TINA-TI_SIMP_CHINESE

没有ISO124的仿真模型

ISO7641FM: 只有输入没有输出

Yicheng Wang — Wed, 08 Jul 2026 04:36:43 GMT

Part Number: ISO7641FM

11角有信号输入，那个6角要有信号输出。但是我们现在测了这11角有信信号输入，6角没有信号输出，所以它都没输出。

RE: ISO7641FM: 只有输入没有输出

Eirwen — Mon, 13 Jul 2026 04:37:29 GMT

下面是数字隔离器设计指南，您可以尝试参考下：

www.ti.com/.../slla284g.pdf

RE: UCC14241-Q1: Why does COM-VEE use two different hysteresis windows (wide and narrow)? Can the narrow window be used alone for lower ripple?

Lydia — Sun, 12 Jul 2026 23:22:45 GMT

Hello, I noticed that you are currently in communication with Shinu. V. Mathew regarding this matter. If you have any further questions, please continue to discuss with Shinu. V. Mathew.

UCC14241-Q1: Why does COM-VEE use two different hysteresis windows (wide and narrow)? Can the narrow window be used alone for lower ripple?

Jiang Luo — Thu, 09 Jul 2026 15:23:50 GMT

Part Number: UCC14241-Q1

Hello TI E2E Experts,

My team is currently in the component selection phase for a new project, and we are strongly considering the UCC14241-Q1 for our application.

Our use case is a bipolar amplifier power supply, where low output voltage ripple on both the positive and negative rails is critical for maintaining signal integrity. While reviewing the device specifications to ensure it matches our system requirements, I noticed that the COM-VEE regulator utilizes two different hysteresis windows — one wide (±20 mV) and one narrow (~1.25 mV) — as shown in the datasheet (Figure 8-2, SLUSF09).

I have the following technical questions:

1. What is the design intent behind using two distinct hysteresis windows for the charge and discharge paths? How does this dual-window approach solve practical problems in the application?

2. Is the wide window (±20 mV) primarily intended for startup and large-signal transient response, while the narrow window (~1.25 mV) handles fine regulation during steady-state operation? Or do they serve a different purpose?

3. For our bipolar amplifier application, where ripple minimization is the top priority, would it be possible to configure the device to use only the narrow hysteresis window (~1.25 mV) for both charge and discharge? If so, what external configuration (e.g., RLIM/RDR network values, capacitor selection, or other pin settings) would be required to achieve this?

4. If the dual-window architecture is fixed and cannot be altered, what practical measures can we take to minimize the COM-VEE output ripple in steady-state operation? For example, would increasing COUT3, optimizing the FBVEE divider, or adjusting RLIM values help reduce the ripple amplitude?

Any technical insights or application guidance would be greatly appreciated.

Best regards,

Luo Jiang

RE: UCC14241-Q1: Why does COM-VEE use two different hysteresis windows (wide and narrow)? Can the narrow window be used alone for lower ripple?

Jiang Luo — Fri, 10 Jul 2026 12:47:32 GMT

Hi Lydia,

Thank you for your attention to this case. I look forward to your further reply.

RE: UCC14241-Q1: Why does COM-VEE use two different hysteresis windows (wide and narrow)? Can the narrow window be used alone for lower ripple?

Jiang Luo — Fri, 10 Jul 2026 12:35:56 GMT

Hi Lydia,
Thank you for your attention to this case. I look forward to your further reply.

RE: UCC14241-Q1: Why does COM-VEE use two different hysteresis windows (wide and narrow)? Can the narrow window be used alone for lower ripple?

Lydia — Thu, 09 Jul 2026 22:57:47 GMT

Hello, we have received your case and the investigation will take some time. Thank you for your patience.

RE: ISO7641FM: 只有输入没有输出

Eirwen — Wed, 08 Jul 2026 04:43:12 GMT

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: TIDA-00785: 使用tida-00785这个驱动出现问题

Daniel — Tue, 23 Jun 2026 00:22:36 GMT

您好

When Q1 conducts, current is sourced from VIN into ground through the lower half of the primary of the transformer. This creates a negative potential at the lower half of the primary, winding with respect to the primary center tap. In order to maintain the previously established current through Q2 , which has now been opened, the upper half of the primary turns positive with respect to the center tap of the primary. This voltage is now transferred to the secondary of the transformer according to the dot convention and the turns ratio of the transformer. CR1 is now forward biased and CR2 is reverse biased; this in turn causes a current to flow through the upper half of the secondary, passing through CR1 into C charging the capacitor and back into the secondary center tap.

根据这个说明，请检查以下D2 和C10/11的情况。

TIDA-00785: 使用tida-00785这个驱动出现问题

?? ? — Fri, 19 Jun 2026 07:20:18 GMT

Part Number: TIDA-00785

我在使用tida-00785这个驱动方案时出现问题，图中绿色的是驱动GaN的Gs电压即Vgs,关断时不是零电压

ISO1042: Do TI have the chip to isolate CAN_H and CAN_L?

Zhanke Zhao — Sun, 21 Jun 2026 01:37:23 GMT

Part Number: ISO1042

As we know, ISO1042 us a chip to isolate between can_tx can_rx and can_h can_l.

Now we want isolate can_h and can_l directly.

Do TI have the chip to isolate CAN_H and CAN_L?

Now out problem is below:

We have only one can controller,so we only connect one can transceiver at can controller by can_tx and can_rx. Now we need connect two device at can transceiver by can_h and can can_l, and two devices,can transceiver should be isoltated each other.

So we need the chip to isolate can_h and can_l.

RE: ISO1042: Do TI have the chip to isolate CAN_H and CAN_L?

Lydia — Mon, 22 Jun 2026 03:09:20 GMT

Hi，we currently do not have a device that isolates CAN bus lines has CANH/CANL lines on both sides.

RE: ISO1042: Do TI have the chip to isolate CAN_H and CAN_L?

Eirwen — Sun, 21 Jun 2026 22:56:29 GMT

Hello, we have received your case and the investigation will take some time. Thank you for your patience.