This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[参考译文] ADS4225EVM:有关计时限制、时钟和输入延迟基元的问题

Guru**** 1138100 points
Other Parts Discussed in Thread: TSW1418EVM, TSW14DL3200EVM
请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1062288/ads4225evm-questions-about-timing-constraints-clocks-and-input-delay-primitives

器件型号:ADS4225EVM
主题中讨论的其他器件:TSW1418EVMTSW14DL3200EVM

你(们)好
我已阅读 SLAA545 (将 Altera FPGA 连接到 ADS4249和 DAC3482 (TIDA-00069参考指南))中有关将 ADS42XX 板连接到 FPGA 开发板的说明。 我已经阅读了数据表、并放置了所需的约束条件。 但是、我的时序不好(至少可以正常工作)。 我将以大约80MSPS 的速率进行采样、因此:  


create_clock -period 10.000 -name aclk -waveform {0.000 5.000} [get_ports -filter { NAME =~  "*aclk*" && DIRECTION == "IN" }]
create_clock -period 13.468 -name ADC_CLK [get_ports {FMC_LA[17]}]
create_clock -period 13.468 -name ADC_CLK_LAUNCH -waveform {3.367 16.835}
create_generated_clock -name ADC_GEN_CLOCK -source [get_pins PLLE2_BASE_inst/CLKIN1] -multiply_by 1 [get_pins PLLE2_BASE_inst/CLKOUT0]
set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA[14]} {FMC_LA[29]} {FMC_LA[25]} {FMC_LA[24]} {FMC_LA[21]} {FMC_LA[22]}}]
set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA[14]} {FMC_LA[29]} {FMC_LA[25]} {FMC_LA[24]} {FMC_LA[21]} {FMC_LA[22]}}]
set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA[19]} {FMC_LA[15]} {FMC_LA[16]} {FMC_LA[11]} {FMC_LA[12]} {FMC_LA[7]}}]
set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA[19]} {FMC_LA[15]} {FMC_LA[16]} {FMC_LA[11]} {FMC_LA[12]} {FMC_LA[7]}}]

但是、我遇到了搁置不可处理的问题。 我放置了 IODELAY 块、但保持可宽延时间是完整的。 如何正确计时 ninterface?

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    Alejandro

    您连接的是哪一个 FPGA 系列? 您是否正在使用 PLL? 请提供有关固件的更多信息和/或发送接口源代码(如果可能)。

    此致、

    Jim

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    我在 nexys 视频板中使用 Xilinx Artix 7 Xc7a200t。 我使用的是 vado2021.2。 这是当前源代码(减少非相关器件)

    RTL

    -------------------------------------------------------------------------------
    -- Title      : ios
    -- Project    : 
    -------------------------------------------------------------------------------
    -- File       : io_1.vhd
    -- Author     : Alejandro Estay  <aestay@dts.cl>
    -- Company    : DTS SpA.
    -- Created    : 2021-12-02
    -- Last update: 2021-12-09
    -- Platform   : Vivado, artix-7
    -- Standard   : VHDL'08
    -------------------------------------------------------------------------------
    -- Description: sistema basico de entrada de adc TI ADS42XX
    -------------------------------------------------------------------------------
    -- Copyright (c) 2021 DTS SpA.
    -------------------------------------------------------------------------------
    -- Revisions  :
    -- Date        Version  Author  Description
    -- 2021-12-02  1.0      aestay  Created
    -------------------------------------------------------------------------------
    
    
    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use ieee.numeric_std.all;
    
    library UNISIM;
    use UNISIM.VComponents.all;
    
    library xpm;
    use xpm.vcomponents.all;
    
    entity ios is
    	generic(of_buttons        : integer := 13;
    	        of_buttons_input  : integer := 2;
    	        of_buttons_output : integer := 8);
    	port (
    		led              : out std_logic_vector(7 downto 0);
    		sw               : in  std_logic_vector(of_buttons -1 downto 0);
    		set_vadj         : out std_logic_vector(1 downto 0);
    		vadj_en          : out std_logic;
    		aclk             : in  std_logic;
    		cpu_resetn       : in  std_logic;
    		FMC_LA, FMC_LA_N : in  std_logic_vector(33 downto 0);
    		jb               : in  std_logic_vector(7 downto 0)
    	);
    end ios;
    
    architecture Behavioral of ios is
    
    	signal FMC_LA_BUS                                      : std_logic_vector(33 downto 0);
    	signal ADC_DA_BUS,ADC_DA_BUS_ND, ADC_DB_BUS, ADC_DC_BUS, ADC_DD_BUS                 : std_logic_vector(0 to 5);
    	signal ADC_DA_BUS_SDR, ADC_DB_BUS_SDR, ADC_DC_BUS_SDR, ADC_DD_BUS_SDR : std_logic_vector(0 to 11);
    
    	signal ADC_CLK_IBUFDS_O                                     : std_logic;
    	signal sys_reset_0, inp_reset_1, sys_resetn_0, inp_resetn_1 : std_logic_vector(0 downto 0);
    	signal sys_reset, inp_reset, sys_resetn, inp_resetn         : std_logic;
    	signal read_clock                                           : std_logic;
    	signal write_clock                                          : std_logic;
    	signal dcm_locked_1, dcm_locked_2                           : std_logic;
    	signal clock_fb, clock_fb_sys                               : std_logic;
    	signal up_down                                              : std_logic_vector(1 downto 0);
    	type pss_state_type is (init, mmcm_wait, mmcm_ready, button_press, button_wait);
    
    	signal pss_state, pss_state_next : pss_state_type;
    
    
    	signal reset_count_a, reset_count_a_next, reset_count_b, reset_count_b_next         : unsigned(3 downto 0);
    	signal reset_count_a_o, reset_count_a_o_next, reset_count_b_o, reset_count_b_o_next : unsigned (8 downto 0);
    
    
    	------------------------------------------------------------------------------------------------------------------------------
    	signal ref_clk				:		std_logic;
    
    
    	component proc_sys_reset_0
    		port (
    			slowest_sync_clk     : in  std_logic;
    			ext_reset_in         : in  std_logic;
    			aux_reset_in         : in  std_logic;
    			mb_debug_sys_rst     : in  std_logic;
    			dcm_locked           : in  std_logic;
    			mb_reset             : out std_logic;
    			bus_struct_reset     : out std_logic_vector(0 downto 0);
    			peripheral_reset     : out std_logic_vector(0 downto 0);
    			interconnect_aresetn : out std_logic_vector(0 downto 0);
    			peripheral_aresetn   : out std_logic_vector(0 downto 0)
    		);
    	end component;
    
    	component proc_sys_reset_1
    		port (
    			slowest_sync_clk     : in  std_logic;
    			ext_reset_in         : in  std_logic;
    			aux_reset_in         : in  std_logic;
    			mb_debug_sys_rst     : in  std_logic;
    			dcm_locked           : in  std_logic;
    			mb_reset             : out std_logic;
    			bus_struct_reset     : out std_logic_vector(0 downto 0);
    			peripheral_reset     : out std_logic_vector(0 downto 0);
    			interconnect_aresetn : out std_logic_vector(0 downto 0);
    			peripheral_aresetn   : out std_logic_vector(0 downto 0)
    		);
    	end component;
    
    
    begin
    	----------------------------------------------------Reset Block---------------------------------------------------------
    	sys_reset  <= sys_reset_0(0);
    	inp_reset  <= inp_reset_1(0);
    	sys_resetn <= sys_resetn_0(0);
    	inp_resetn <= inp_resetn_1(0);
    	------------------------------------------------------------------------------------------------------------------------
    	-----------------------------------------------------wirebox------------------------------------------------------------
    	--*****************************************************FMC************************************************************--  
    	set_vadj <= "01";
    	vadj_en  <= '1';
    
    	ADC_CLK_IBUFDS_O <= FMC_LA_BUS(17);
    
    	ADC_DA_BUS_ND <= (FMC_LA_BUS(29) & FMC_LA_BUS(14) & FMC_LA_BUS(25) & FMC_LA_BUS(24) & FMC_LA_BUS(21) & FMC_LA_BUS(22));
    	ADC_DB_BUS <= (FMC_LA_BUS(19) & FMC_LA_BUS(15) & FMC_LA_BUS(16) & FMC_LA_BUS(11) & FMC_LA_BUS(12) & FMC_LA_BUS(7));
    	--ADC_DC_BUS          <= (FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(7));
    	--ADC_DD_BUS          <= (FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(),FMC_LA_BUS(7));
    	--*******************************************************************************************************************--
    *------------------------------------------------------------------*
    	PLLE2_BASE_sys : MMCME2_ADV
    		generic map (
    			BANDWIDTH          => "OPTIMIZED",   -- OPTIMIZED, HIGH, LOW
    			CLKFBOUT_MULT_F    => 10.0,  -- Multiply value for all CLKOUT, (2-64)
    			CLKFBOUT_PHASE     => 0.0,  -- Phase offset in degrees of CLKFB, (-360.000-360.000).
    			CLKIN1_PERIOD      => 10.0,  -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
    			-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
    			CLKOUT0_DIVIDE_F   => 10.0,       --(100 Mhz)
    			CLKOUT1_DIVIDE     => 30,         --(4.56Mhz)
    			CLKOUT2_DIVIDE     => 5,
    			CLKOUT3_DIVIDE     => 10,
    			CLKOUT4_DIVIDE     => 10,
    			CLKOUT5_DIVIDE     => 10,
    			-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
    			CLKOUT0_DUTY_CYCLE => 0.5,
    			CLKOUT1_DUTY_CYCLE => 0.5,
    			CLKOUT2_DUTY_CYCLE => 0.5,
    			CLKOUT3_DUTY_CYCLE => 0.5,
    			CLKOUT4_DUTY_CYCLE => 0.5,
    			CLKOUT5_DUTY_CYCLE => 0.5,
    			-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
    			CLKOUT0_PHASE      => 0.0,
    			CLKOUT1_PHASE      => 0.0,
    			CLKOUT2_PHASE      => 0.0,
    			CLKOUT3_PHASE      => 0.0,
    			CLKOUT4_PHASE      => 0.0,
    			CLKOUT5_PHASE      => 0.0,
    			DIVCLK_DIVIDE      => 1,          -- Master division value, (1-56)
    			REF_JITTER1        => 0.0,  -- Reference input jitter in UI, (0.000-0.999).
    			STARTUP_WAIT       => true  -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
    		)
    		port map (
    			-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
    			CLKOUT0  => read_clock,           -- 1-bit output: CLKOUT0
    			CLKOUT1  => sw_clock,             -- 1-bit output: CLKOUT1
    			CLKOUT2  => ref_clk,                 -- 1-bit output: CLKOUT2
    			CLKOUT3  => open,                 -- 1-bit output: CLKOUT3
    			CLKOUT4  => open,                 -- 1-bit output: CLKOUT4
    			CLKOUT5  => open,                 -- 1-bit output: CLKOUT5
    			-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
    			CLKFBOUT => clock_fb_sys,         -- 1-bit output: Feedback clock
    			LOCKED   => dcm_locked_1,         -- 1-bit output: LOCK
    			CLKIN1   => aclk,
    			CLKIN2   => '1',
    			CLKINSEL => '1',
    			-- 1-bit input: Input clock
    			-- Control Ports: 1-bit (each) input: PLL control ports
    			PWRDWN   => '0',                  -- 1-bit input: Power-down
    			RST      => not cpu_resetn,       -- 1-bit input: Reset
    			-------------------------------------------------------------------------------------
    			DADDR    => (others => '0'),
    			DCLK     => '0',
    			DI       => (others => '0'),
    			DEN      => '0',
    			DWE      => '0',
    			-----------------------------------------------------------
    			PSCLK    => '0',                  --1-bit input: Phase shift clock
    			PSEN     => '0',                  --1-bit  input: Phase shift enable
    			PSINCDEC => '0',            --1-bit input:Phase shift increment/decrement
    			-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
    			CLKFBIN  => clock_fb_sys          -- 1-bit input: Feedback clock
    		);
    	PLLE2_BASE_inst : MMCME2_ADV
    		generic map (
    			BANDWIDTH           => "OPTIMIZED",  -- OPTIMIZED, HIGH, LOW
    			CLKFBOUT_MULT_F     => 15.0,  -- Multiply value for all CLKOUT, (2-64)
    			CLKFBOUT_PHASE      => 0.00,  -- Phase offset in degrees of CLKFB, (-360.000-360.000).
    			CLKIN1_PERIOD       => 13.468,  -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
    			-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
    			CLKOUT0_DIVIDE_F    => 15.0,
    			CLKOUT1_DIVIDE      => 15,
    			CLKOUT2_DIVIDE      => 15,
    			CLKOUT3_DIVIDE      => 15,
    			CLKOUT4_DIVIDE      => 15,
    			CLKOUT5_DIVIDE      => 15,
    			-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
    			CLKOUT0_DUTY_CYCLE  => 0.5,
    			CLKOUT1_DUTY_CYCLE  => 0.5,
    			CLKOUT2_DUTY_CYCLE  => 0.5,
    			CLKOUT3_DUTY_CYCLE  => 0.5,
    			CLKOUT4_DUTY_CYCLE  => 0.5,
    			CLKOUT5_DUTY_CYCLE  => 0.5,
    			-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
    			CLKOUT0_PHASE       => 0.0,
    			CLKOUT1_PHASE       => 0.0,
    			CLKOUT2_PHASE       => 0.0,
    			CLKOUT3_PHASE       => 0.0,
    			CLKOUT4_PHASE       => 0.0,
    			CLKOUT5_PHASE       => 0.0,
    			DIVCLK_DIVIDE       => 1,         -- Master division value, (1-56)
    			REF_JITTER1         => 0.0,  -- Reference input jitter in UI, (0.000-0.999).
    			CLKOUT0_USE_FINE_PS => true,
    			STARTUP_WAIT        => true  -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
    		)
    		port map (
    			-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
    			CLKOUT0  => write_clock,          -- 1-bit output: CLKOUT0
    			CLKOUT1  => open,                 -- 1-bit output: CLKOUT1
    			CLKOUT2  => open,                 -- 1-bit output: CLKOUT2
    			CLKOUT3  => open,                 -- 1-bit output: CLKOUT3
    			CLKOUT4  => open,                 -- 1-bit output: CLKOUT4
    			CLKOUT5  => open,                 -- 1-bit output: CLKOUT5
    			-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
    			CLKFBOUT => clock_fb,             -- 1-bit output: Feedback clock
    			LOCKED   => dcm_locked_2,         -- 1-bit output: LOCK
    			--      CLKIN1    => ADC_CLK_IBUFDS_O,     -- 1-bit input: Input clock
    			CLKIN1   => ADC_CLK_IBUFDS_O,
    			CLKIN2   => '1',
    			CLKINSEL => '1',
    			-- Control Ports: 1-bit (each) input: PLL control ports
    			PWRDWN   => '0',                  -- 1-bit input: Power-down
    			RST      => not cpu_resetn,       -- 1-bit input: Reset
    			---------------------------------------------------------
    			DADDR    => (others => '0'),
    			DCLK     => '0',
    			DI       => (others => '0'),
    			DEN      => '0',
    			DWE      => '0',
    			-----------------------------------------------------------
    			PSCLK    => write_clock,          --1-bit input: Phase shift clock
    			PSEN     => psen,                 --1-bit  input: Phase shift enable
    			PSINCDEC => psincdec,       --1-bitinput:Phase shift increment/decrement
    			PSDONE   => psdone,
    			-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
    			CLKFBIN  => clock_fb              -- 1-bit input: Feedback clock
    		);
    
    	reset_system : proc_sys_reset_0
    		port map(
    			slowest_sync_clk     => sw_clock,
    			ext_reset_in         => cpu_resetn,
    			aux_reset_in         => '0',
    			mb_debug_sys_rst     => '0',
    			dcm_locked           => dcm_locked_1,
    			mb_reset             => open,
    			bus_struct_reset     => open,
    			peripheral_reset     => sys_reset_0,
    			interconnect_aresetn => open,
    			peripheral_aresetn   => sys_resetn_0
    		);
    	reset_input : proc_sys_reset_1
    		port map(
    			slowest_sync_clk     => write_clock,
    			ext_reset_in         => cpu_resetn,
    			aux_reset_in         => '0',
    			mb_debug_sys_rst     => '0',
    			dcm_locked           => dcm_locked_2,
    			mb_reset             => open,
    			bus_struct_reset     => open,
    			peripheral_reset     => inp_reset_1,
    			interconnect_aresetn => open,
    			peripheral_aresetn   => inp_resetn_1
    		);
    
    	generate_FMC_LA : for index in 0 to 33 generate
    		IBUFDS_A : IBUFDS
    			port map (
    				I  => FMC_LA(index),
    				IB => FMC_LA_N(index),
    				O  => FMC_LA_BUS(index)
    			);
    	end generate generate_FMC_LA;
    
    	generate_DDR_A : for index in 0 to 5 generate
    		IDDR_inst_A : IDDR
    			generic map (
    				DDR_CLK_EDGE => "OPPOSITE_EDGE",  			-- "OPPOSITE_EDGE", "SAME_EDGE" 
    				-- or "SAME_EDGE_PIPELINED" 
    				INIT_Q1      => '0',            			-- Initial value of Q1: '0' or '1'
    				INIT_Q2      => '0',            			-- Initial value of Q2: '0' or '1'
    				SRTYPE       => "SYNC")         			-- Set/Reset type: "SYNC" or "ASYNC" 
    			port map (
    				Q1 => ADC_DA_BUS_SDR(2*index),  			-- 1-bit output for positive edge of clock 
    				Q2 => ADC_DA_BUS_SDR(2*index+1),  			-- 1-bit output for negative edge of clock
    				C  => write_clock,              			-- 1-bit clock input
    				CE => dcm_locked_2,             			-- 1-bit clock enable input
    				D  => ADC_DA_BUS(index),        			-- 1-bit DDR data input
    				R  => inp_reset,                			-- 1-bit reset
    				S  => '0'  );                     			-- 1-bit set
        ADC_DA_INPUT_ctrl: IDELAYCTRL
       port map (
          RDY 		=> 	open,       -- 1-bit output: Ready output
          REFCLK 	=> 	ref_clk, -- 1-bit input: Reference clock input
          RST 		=> 	sys_reset);
       	
     	ADC_DA_INPUT_inst : IDELAYE2
       			generic map (
          			CINVCTRL_SEL 			=> "FALSE",         -- Enable dynamic clock inversion (FALSE, TRUE)
          			DELAY_SRC 				=> "IDATAIN",       -- Delay input (IDATAIN, DATAIN)
          			HIGH_PERFORMANCE_MODE 	=> "TRUE", 		-- Reduced jitter ("TRUE"), Reduced power ("FALSE")
          			IDELAY_TYPE 			=> "FIXED",         -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
          			IDELAY_VALUE 			=> 27,               -- Input delay tap setting (0-31)
          			PIPE_SEL 				=> "FALSE",         -- Select pipelined mode, FALSE, TRUE
          			REFCLK_FREQUENCY 		=> 200.0,        	-- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
          			SIGNAL_PATTERN 			=> "DATA"          	-- DATA, CLOCK input signal
       						)
       			port map (
          			DATAOUT 				=> ADC_DA_BUS(index),          -- 1-bit output: Delayed data output
          			C 						=> write_clock,                -- 1-bit input: Clock input
          			CE 						=> '1',
          			cinvctrl 				=> '0',
          			cntvaluein				=> (others=>'0'),
          			datain 					=> '0',
          			inc						=> '0',
          			ld						=> '0',
          			regrst 					=> '0',
          			ldpipeen 				=> '0',
          			IDATAIN 				=> ADC_DA_BUS_ND(index)  );      -- 1-bit input: Data input from the I/O
    
    end generate generate_DDR_A;
    
    

    时序

    create_clock -period 10.000 -name aclk -waveform {0.000 5.000} [get_ports -filter { NAME =~  "*aclk*" && DIRECTION == "IN" }]
    create_clock -period 13.468 -name ADC_CLK [get_ports {FMC_LA[17]}]
    create_clock -period 13.468 -name ADC_CLK_LAUNCH -waveform {3.367 16.835}
    # IODELAY GROUPS
    
    
    #attribute IODELAY_GROUP of ADC_DA_INPUT_inst:  label is "ADC_A_INPUT_DLY";
    #attribute IODELAY_GROUP of ADC_DA_INPUT_crtl:  label is "ADC_A_INPUT_DLY";
    
    
    set_property IODELAY_GROUP ADC_A_INPUT_DLY [get_cells -filter  {NAME =~ "*ADC_DA_INPUT_inst*"}]
    set_property IODELAY_GROUP ADC_A_INPUT_DLY [get_cells -filter  {NAME =~ "*ADC_DA_INPUT_ctrl*"}]
    #
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA[14]} {FMC_LA[29]} {FMC_LA[25]} {FMC_LA[24]} {FMC_LA[21]} {FMC_LA[22]}}]
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA[14]} {FMC_LA[29]} {FMC_LA[25]} {FMC_LA[24]} {FMC_LA[21]} {FMC_LA[22]}}]
    
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA_N[14]} {FMC_LA_N[29]} {FMC_LA_N[25]} {FMC_LA_N[24]} {FMC_LA_N[21]} {FMC_LA_N[22]}}]
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA_N[14]} {FMC_LA_N[29]} {FMC_LA_N[25]} {FMC_LA_N[24]} {FMC_LA_N[21]} {FMC_LA_N[22]}}]
    
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA[19]} {FMC_LA[15]} {FMC_LA[16]} {FMC_LA[11]} {FMC_LA[12]} {FMC_LA[7]}}]
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA[19]} {FMC_LA[15]} {FMC_LA[16]} {FMC_LA[11]} {FMC_LA[12]} {FMC_LA[7]}}]
    
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -min -network_latency_included -source_latency_included -2.767 [get_ports {{FMC_LA_N[19]} {FMC_LA_N[15]} {FMC_LA_N[16]} {FMC_LA_N[11]} {FMC_LA_N[12]} {FMC_LA_N[7]}}]
    set_input_delay -clock [get_clocks ADC_CLK_LAUNCH] -max -network_latency_included -source_latency_included -1.833 [get_ports {{FMC_LA_N[19]} {FMC_LA_N[15]} {FMC_LA_N[16]} {FMC_LA_N[11]} {FMC_LA_N[12]} {FMC_LA_N[7]}}]
    
    #create_generated_clock -name ADC_GEN_CLOCK -source [get_pins PLLE2_BASE_inst/CLKIN1] -multiply_by 1 -invert -add -master_clock [get_clocks ADC_CLK] [get_pins PLLE2_BASE_inst/CLKOUT0]
    create_generated_clock -name ADC_GEN_CLOCK -source [get_pins PLLE2_BASE_inst/CLKIN1] -multiply_by 1 [get_pins PLLE2_BASE_inst/CLKOUT0]

    I/O 放置

    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[0]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[0]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[1]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[1]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[2]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[2]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[3]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[3]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[4]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[4]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[5]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[5]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[6]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[6]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[7]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[7]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[8]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[8]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[9]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[9]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[10]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[10]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[11]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[11]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[12]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[12]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[13]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[13]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[14]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[14]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[15]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[15]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[16]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[16]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[17]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[17]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[18]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[18]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[19]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[19]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[20]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[20]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[21]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[21]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[22]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[22]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[23]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[23]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[24]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[24]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[25]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[25]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[26]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[26]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[27]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[27]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[28]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[28]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[29]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[29]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[30]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[30]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[31]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[31]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[32]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[32]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA_N[33]}]
    set_property IOSTANDARD LVDS_25 [get_ports {FMC_LA[33]}]
    
    set_property PACKAGE_PIN K18 [get_ports {FMC_LA[0]}]
    set_property PACKAGE_PIN K19 [get_ports {FMC_LA_N[0]}]
    set_property PACKAGE_PIN J20 [get_ports {FMC_LA[1]}]
    set_property PACKAGE_PIN J21 [get_ports {FMC_LA_N[1]}]
    set_property PACKAGE_PIN M18 [get_ports {FMC_LA[2]}]
    set_property PACKAGE_PIN L18 [get_ports {FMC_LA_N[2]}]
    set_property PACKAGE_PIN N18 [get_ports {FMC_LA[3]}]
    set_property PACKAGE_PIN N19 [get_ports {FMC_LA_N[3]}]
    set_property PACKAGE_PIN N20 [get_ports {FMC_LA[4]}]
    set_property PACKAGE_PIN M20 [get_ports {FMC_LA_N[4]}]
    set_property PACKAGE_PIN M21 [get_ports {FMC_LA[5]}]
    set_property PACKAGE_PIN L21 [get_ports {FMC_LA_N[5]}]
    set_property PACKAGE_PIN N22 [get_ports {FMC_LA[6]}]
    set_property PACKAGE_PIN M22 [get_ports {FMC_LA_N[6]}]
    set_property PACKAGE_PIN M13 [get_ports {FMC_LA[7]}]
    set_property PACKAGE_PIN L13 [get_ports {FMC_LA_N[7]}]
    set_property PACKAGE_PIN M15 [get_ports {FMC_LA[8]}]
    set_property PACKAGE_PIN M16 [get_ports {FMC_LA_N[8]}]
    set_property PACKAGE_PIN H20 [get_ports {FMC_LA[9]}]
    set_property PACKAGE_PIN G20 [get_ports {FMC_LA_N[9]}]
    set_property PACKAGE_PIN K21 [get_ports {FMC_LA[10]}]
    set_property PACKAGE_PIN K22 [get_ports {FMC_LA_N[10]}]
    set_property PACKAGE_PIN L14 [get_ports {FMC_LA[11]}]
    set_property PACKAGE_PIN L15 [get_ports {FMC_LA_N[11]}]
    set_property PACKAGE_PIN L19 [get_ports {FMC_LA[12]}]
    set_property PACKAGE_PIN L20 [get_ports {FMC_LA_N[12]}]
    set_property PACKAGE_PIN K17 [get_ports {FMC_LA[13]}]
    set_property PACKAGE_PIN J17 [get_ports {FMC_LA_N[13]}]
    set_property PACKAGE_PIN J22 [get_ports {FMC_LA[14]}]
    set_property PACKAGE_PIN H22 [get_ports {FMC_LA_N[14]}]
    set_property PACKAGE_PIN L16 [get_ports {FMC_LA[15]}]
    set_property PACKAGE_PIN K16 [get_ports {FMC_LA_N[15]}]
    set_property PACKAGE_PIN G17 [get_ports {FMC_LA[16]}]
    set_property PACKAGE_PIN G18 [get_ports {FMC_LA_N[16]}]
    set_property PACKAGE_PIN B17 [get_ports {FMC_LA[17]}]
    set_property PACKAGE_PIN B18 [get_ports {FMC_LA_N[17]}]
    set_property PACKAGE_PIN D17 [get_ports {FMC_LA[18]}]
    set_property PACKAGE_PIN C17 [get_ports {FMC_LA_N[18]}]
    set_property PACKAGE_PIN A18 [get_ports {FMC_LA[19]}]
    set_property PACKAGE_PIN A19 [get_ports {FMC_LA_N[19]}]
    set_property PACKAGE_PIN F19 [get_ports {FMC_LA[20]}]
    set_property PACKAGE_PIN F20 [get_ports {FMC_LA_N[20]}]
    set_property PACKAGE_PIN E19 [get_ports {FMC_LA[21]}]
    set_property PACKAGE_PIN D19 [get_ports {FMC_LA_N[21]}]
    set_property PACKAGE_PIN E21 [get_ports {FMC_LA[22]}]
    set_property PACKAGE_PIN D21 [get_ports {FMC_LA_N[22]}]
    set_property PACKAGE_PIN B21 [get_ports {FMC_LA[23]}]
    set_property PACKAGE_PIN A21 [get_ports {FMC_LA_N[23]}]
    set_property PACKAGE_PIN B15 [get_ports {FMC_LA[24]}]
    set_property PACKAGE_PIN B16 [get_ports {FMC_LA_N[24]}]
    set_property PACKAGE_PIN F16 [get_ports {FMC_LA[25]}]
    set_property PACKAGE_PIN E17 [get_ports {FMC_LA_N[25]}]
    set_property PACKAGE_PIN F18 [get_ports {FMC_LA[26]}]
    set_property PACKAGE_PIN E18 [get_ports {FMC_LA_N[26]}]
    set_property PACKAGE_PIN B20 [get_ports {FMC_LA[27]}]
    set_property PACKAGE_PIN A20 [get_ports {FMC_LA_N[27]}]
    set_property PACKAGE_PIN C13 [get_ports {FMC_LA[28]}]
    set_property PACKAGE_PIN B13 [get_ports {FMC_LA_N[28]}]
    set_property PACKAGE_PIN C14 [get_ports {FMC_LA[29]}]
    set_property PACKAGE_PIN C15 [get_ports {FMC_LA_N[29]}]
    set_property PACKAGE_PIN A13 [get_ports {FMC_LA[30]}]
    set_property PACKAGE_PIN A14 [get_ports {FMC_LA_N[30]}]
    set_property PACKAGE_PIN E13 [get_ports {FMC_LA[31]}]
    set_property PACKAGE_PIN E14 [get_ports {FMC_LA_N[31]}]
    set_property PACKAGE_PIN A15 [get_ports {FMC_LA[32]}]
    set_property PACKAGE_PIN A16 [get_ports {FMC_LA_N[32]}]
    set_property PACKAGE_PIN F13 [get_ports {FMC_LA[33]}]
    set_property PACKAGE_PIN F14 [get_ports {FMC_LA_N[33]}]
    

    我有该计时结果


    由于某种原因、保持状态真的很糟糕、但我不知道计算中是否是最小延迟误差、或者我必须放置一个实际的输入延迟元件来进行补偿。
    显然、我已经放置了一个 MMCM 来生成内部时钟、即74.5 MHz。 我将使用生成的时钟和200MHz 参考时钟馈送输入延迟元件。 RTL 可以正常工作、但我想解决继续存在的时序问题。

    e2e.ti.com/.../schematic_5F00_ti.pdf

    原理图位于该 pdf 中。
    我使用图13的公式和80MSPS 数据完成了输入延迟计算。

    当然、如果我清除约束问题就会消失、但我无法检查是否有足够的可宽延时间来正确读取数据。 波形看起来是、但我 不知道是否有足够的窗口

    但愿你能帮帮我

    谢谢

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    Alejandro

    我将了解能否让我们的固件专家来了解这一点。 您可以通过以下链接下载 TSW1418EVM 使用的示例源代码。 该板具有 XC7A100T Xilinx 器件、用于连接到我们较新的串行 LVDS ADC。 看看这是否有用。

    此致、

    Jim

     tidrive.ext.ti.com/.../90c1a88e-c9d4-45b9-aaae-b522f2c4b0c6

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    感谢 Jim、但该固件包显然仅适用于串行 LVDS ADC。 这是并行的。

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    Alejandro

    您可以在 TI 网站的 TSW14DL3200EVM 产品文件夹下找到使用并行 LVDS 数据的示例 Xilinx 固件。

    下面是在另一个 Xilinx 平台上用于并行 SDR 数据采集的 Verilog/RTL。  

     

    线[11:0] ADC_DATA_CHA;//12 CHA 的 SDR 数据位

    线[11:0] ADC_DATA_CHB;//12 SDR 数据位用于 CHB

     

    寄存器[11:0] ADC_REG_final_CHA;

    reg [11:0] ADC_REG_final_CHB;

     

    始终@μ s (POedge ADC_dclk)//使用来自 ADC 的 DCLK 作为时钟。 在 DCLK 的上升沿。

    开始

      ADC_REG_final_Cha <= ADC_DATA_CHA;

     ADC_REG_final_CHB <= ADC_DATA_CHB;

    在 ADC DCLK 的每个上升沿上结束//、将 ADC 数据引脚的状态存储到寄存器中(此处用于 CHA 和 CHB)。 进行相应修改。

     

    //始终@(negedge ADC_dclk)//这是一个 DDR 实现,因此,如果仅使用 SDR,则忽略。 存储 ADC 数据引脚在 ADC DCLK 下降沿的状态。

    //begin

    // ADC_REG_FALLING_CHA <= ADC_DATA_CHA;

    // ADC_REG_FALLING_CHB <= ADC_DATA_CHB;

    //结束//需要将上升沿数据附加到寄存器中的下降沿数据。

     

    分配 ADC_DATA_OUT_CHA = ADC_REG_final_CHA;

    分配 ADC_DATA_OUT_CHB = ADC_REG_final_CHB;

    "

    然后、您可以添加 ILA 调试内核来监视 ADC_DATA_OUT_CHA 网络以观察样本数据。

    此致、

    Jim   

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    我使用足够的基元(IDDR)来解决 DDR 部分、因此这不是问题。 (实际上、尽管在 SLAA545应用手册中使用了 Altera FPGA 的模拟 DDR 基元、但在参考设计中不使用它还是很奇怪)。

    (这是代码、从209到305)

    --------------------------------------------------------------------------	
    	generate_DDR_A : for index in 0 to 5 generate
    		IDDR_inst_A : IDDR
    			generic map (
    				DDR_CLK_EDGE => "OPPOSITE_EDGE",  			-- "OPPOSITE_EDGE", "SAME_EDGE" 
    				-- or "SAME_EDGE_PIPELINED" 
    				INIT_Q1      => '0',            			-- Initial value of Q1: '0' or '1'
    				INIT_Q2      => '0',            			-- Initial value of Q2: '0' or '1'
    				SRTYPE       => "SYNC")         			-- Set/Reset type: "SYNC" or "ASYNC" 
    			port map (
    				Q1 => ADC_DA_BUS_SDR(2*index),  			-- 1-bit output for positive edge of clock 
    				Q2 => ADC_DA_BUS_SDR(2*index+1),  			-- 1-bit output for negative edge of clock
    				C  => write_clock,              			-- 1-bit clock input
    				CE => dcm_locked_2,             			-- 1-bit clock enable input
    				D  => ADC_DA_BUS(index),        			-- 1-bit DDR data input
    				R  => inp_reset,                			-- 1-bit reset
    				S  => '0'  );                     			-- 1-bit set
        ADC_DA_INPUT_ctrl: IDELAYCTRL
        --------------------------------------------------------------------

    此外、接口是中心对齐的事实不会在代码中的任何位置进行寻址(RTL 或约束)

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    Alejandro

    我们的大多数固件都是由第三方完成的、我们的团队不再使用该第三方进行固件开发。 我已就此向您提供了尽可能多的服务。 我强烈建议您与 FPGA 供应商联系、以获得更多帮助。

    此致、

    Jim