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[参考译文] AM5728:无法从 PCIe 板内存读取数据

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Other Parts Discussed in Thread: AM5728
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https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1072509/am5728-cannot-read-data-from-pcie-board-memory

部件号:AM5728

你好。
我有基于 am5728的定制板。
在我的系统中,我有两个 PCI 桥接器和一个带有 FPGA 的自定义 PCI 板。
在 Linux 启动后,我尝试从 PCI 板读取内存并获得此结果
(我在未成功收到附件的情况下开始使用 devmem2来读取驱动程序中的内存以用于此主板
请注意,内核消息在电源重置后仅出现一次,并读取0x20200000地址):

root@am57xx-EVM:Δ T~# devmem2 0x20200000
/dev/mem 已打开。
[1036.130101] OMA_L3_NOC 44000000.OCP:L3应用程序错误:目标5 mod:1 (不可清除)
映射到地址0xb6fd1000的内存。
读取地址0x2020000 [1036.138297] OMAP_L3_NOC 44000000.OCP:L3调试错误:目标5 mod:1 (不可清除)
0 (0xb6fd1000):0xFFFFFFFF

如果我尝试从 PCI 桥读取内存,我会得到另一个答案,而不会收到内核消息:

root@am57xx-EVM:Δ T~# devmem2 0x20400000
/dev/mem 已打开。
映射到地址0xb6fba000的内存。
请在地址0x20400000 (0x6fba000)处阅读:0x860910B5

我在论坛上阅读了一些线索,但没有解决我的问题。 我决定检查错误。

从14.2.4.2.1.1.2起,随后:TRM 中的 L3_main Interconnect Protection Violation Error Identification (三级主互连保护违规错误标识) I 检查:
L3_FLAGMUX _REGERR0 [31:0] REGERROR0 (所有值均为零):

根@am57xx-EVM:~#设备内存2 0x4480350C
/dev/mem 已打开。
内存映射地址为0xb6f73000。
读取地址0x4480350C (0x6f7350c): 0x00000000
根@am57xx-EVM:~#设备2 0x4480360C
/dev/mem 已打开。
内存映射到地址0xb6fe6000。
读取地址0x4480360C (0x6fe660c):0x00000000
root@am57xx-EVM:Δ~# devmem2 0x4500020C
/dev/mem 已打开。
内存映射到地址0xb6fb3000。
读取地址0x4500020C (0x6fb320c): 0x00000000

Ctrl_core_SEC_ERR_STATUS_FUNC_1 (值为零):

root@am57xx-EVM:Δ~# devmem2 0x4A002148
/dev/mem 已打开。
映射到地址0xb6fd8000的内存。
读取地址0x4A002148 (0x6fd8148):0x00000000

L3_FLAGMUX_REGERR1 (所有值均为零):

根@am57xx-EVM:~#设备内存2 0x44803514
/dev/mem 已打开。
内存映射地址为0xb6f79000。
读取地址0x44803514 (0x6f79514):0x00000000
root@am57xx-EVM:~#设备内存2 0x44803614
/dev/mem 已打开。
内存映射地址为0xb6f37000。
读取地址0x44803614 (0x6f37614):0x00000000
root@am57xx-EVM:Δ T~# devmem2 0x45000214
/dev/mem 已打开。
映射到地址0xb6f3a000的内存。
读取地址0x45000214 (0x6f3a214):0x00000000

从14.2.4.2.1.1.3后续版本:TRM 中的 L3_main 互连标准错误标识 I 检查:
L3_TAGR_STDERRLOG_MAIN (所有值均为零):

/dev/mem opened.
Memory mapped at address 0xb6f9e000.
Read at address  0x44000148 (0xb6f9e148): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fc5000.
Read at address  0x44000248 (0xb6fc5248): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f9f000.
Read at address  0x44000348 (0xb6f9f348): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fbf000.
Read at address  0x44000548 (0xb6fbf548): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fe1000.
Read at address  0x44000648 (0xb6fe1648): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fa3000.
Read at address  0x44000748 (0xb6fa3748): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f14000.
Read at address  0x44000848 (0xb6f14848): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fc5000.
Read at address  0x44000948 (0xb6fc5948): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fd3000.
Read at address  0x44001148 (0xb6fd3148): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fc1000.
Read at address  0x44002F48 (0xb6fc1f48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f00000.
Read at address  0x44003048 (0xb6f00048): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f09000.
Read at address  0x44003148 (0xb6f09148): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f86000.
Read at address  0x44000D48 (0xb6f86d48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f6c000.
Read at address  0x44000C48 (0xb6f6cc48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fb4000.
Read at address  0x44000A48 (0xb6fb4a48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f9d000.
Read at address  0x44000B48 (0xb6f9db48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fbb000.
Read at address  0x44000E48 (0xb6fbbe48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f0c000.
Read at address  0x44000F48 (0xb6f0cf48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f68000.
Read at address  0x44001048 (0xb6f68048): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f6d000.
Read at address  0x44001248 (0xb6f6d248): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6faa000.
Read at address  0x44001348 (0xb6faa348): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f7c000.
Read at address  0x44001448 (0xb6f7c448): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f0f000.
Read at address  0x44001648 (0xb6f0f648): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f69000.
Read at address  0x44001748 (0xb6f69748): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f0b000.
Read at address  0x44001848 (0xb6f0b848): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f0a000.
Read at address  0x44001948 (0xb6f0a948): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f7d000.
Read at address  0x44001C48 (0xb6f7dc48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f05000.
Read at address  0x44001D48 (0xb6f05d48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fc9000.
Read at address  0x44001F48 (0xb6fc9f48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f68000.
Read at address  0x44002048 (0xb6f68048): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f68000.
Read at address  0x44002148 (0xb6f68148): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fd1000.
Read at address  0x44002248 (0xb6fd1248): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f56000.
Read at address  0x44002348 (0xb6f56348): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f16000.
Read at address  0x44002448 (0xb6f16448): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fcb000.
Read at address  0x44002548 (0xb6fcb548): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f0a000.
Read at address  0x44002648 (0xb6f0a648): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fb0000.
Read at address  0x44002748 (0xb6fb0748): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f09000.
Read at address  0x44002848 (0xb6f09848): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f08000.
Read at address  0x44002948 (0xb6f08948): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f1e000.
Read at address  0x44002B48 (0xb6f1eb48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f6d000.
Read at address  0x44002E48 (0xb6f6de48): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6f05000.
Read at address  0x44003748 (0xb6f05748): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fe9000.
Read at address  0x44003948 (0xb6fe9948): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6ff5000.
Read at address  0x45000148 (0xb6ff5148): 0x00000000
/dev/mem opened.
Memory mapped at address 0xb6fb4000.
Read at address  0x45000348 (0xb6fb4348): 0x00000000

L3_FLAGMUX_REGERR0 (0x4480360C 值为0x00000020)。 在出现 L3应用程序错误之前,此值为0x00000000):

根@am57xx-EVM:~#设备内存2 0x4480350C
/dev/mem 已打开。
内存映射地址为0xb6fcf000。
请在地址0x4480350C (0x6fcf50c): 0x00000000处阅读
根@am57xx-EVM:~#设备2 0x4480360C
/dev/mem 已打开。
内存映射地址为0xb6f65000。
读取地址0x4480360C (0xb6f6560c): 0x00000020
root@am57xx-EVM:Δ~# devmem2 0x4500020C
/dev/mem 已打开。
内存映射到地址0xb6fb1000。
读取地址0x4500020C (0x6fb120c):0x00000000

L3_FLAGMUX_MASK1 (0x44803610值为0x007FFDF。 在出现 L3应用程序错误之前,此值为0x007FFFFF):

root@am57xx-EVM:~#设备2 0x44803510
/dev/mem 已打开。
映射到地址0xb6f9c000的内存。
请参阅地址0x44803510 (0x6f9c510):0xFFFFFFFF
root@am57xx-EVM:~#设备内存2 0x44803610
/dev/mem 已打开。
内存映射地址为0xb6f36000。
读取地址0x44803610 (0x6f36610):0x007FFDF
root@am57xx-EVM:Δ T~# devmem2 0x45000210
/dev/mem 已打开。
映射到地址0xb6fdb000的内存。
读取地址0x45000210 (0x6fdb210):0x00000000

L3_FLAGMUX_REGERR1 (0x44803614值为0x00000020)。 在出现 L3应用程序错误之前,此值为0x00000000):

根@am57xx-EVM:~#设备内存2 0x44803514
/dev/mem 已打开。
映射到地址0xb6f49000的内存。
读取地址0x44803514 (0x6f49514):0x00000000
root@am57xx-EVM:~#设备内存2 0x44803614
/dev/mem 已打开。
内存映射地址为0xb6f26000。
请参阅地址0x44803614 (0xb6f26614):0x00000020
root@am57xx-EVM:Δ T~# devmem2 0x45000214
/dev/mem 已打开。
映射到地址0xb6fa9000的内存。
读取地址0x45000214 (0xb6fa9214):0x00000000

下一页在表14-24中。 互连标志映射我找不到0x00000020 (32)值。

出现此错误的原因是什么?
为什么我无法从 PCIe 板读取内存?
是我的原因还是 PCI borard 显影剂的原因?

请你提出建议为荷。


板载配置空间命令寄存器值为0x0546,即平均内存空间启用位已设置。

以下是我的系统的附加信息:

从 lspci:

There is pci-devices tree:
 root@am57xx-evm:~# /usr/sbin/lspci -t
-[0000:00]---00.0-[01-ff]--+-00.0-[02-11]--+-01.0-[03]--
                           |               +-04.0-[04]--
                           |               +-05.0-[05]----00.0
                           |               +-06.0-[06]--
                           |               +-07.0-[07]--
                           |               +-08.0-[08]--
                           |               \-09.0-[09-11]--+-00.0-[0a-11]--+-01.0-[0b]--
                           |                               |               +-04.0-[0c]--
                           |                               |               +-05.0-[0d]--
                           |                               |               +-06.0-[0e]--
                           |                               |               +-07.0-[0f]--
                           |                               |               +-08.0-[10]--
                           |                               |               \-09.0-[11]--
                           |                               \-00.1
                           \-00.1
 
There is pci-devices config spaces:
root@am57xx-evm:~# /usr/sbin/lspci -x
00:00.0 PCI bridge: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01)
00: 4c 10 88 88 47 05 10 00 01 00 04 06 10 00 01 00
10: 04 00 10 20 00 00 00 00 00 01 ff 00 f0 00 00 20
20: 20 20 40 20 f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a6 01 01 00

01:00.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 46 05 10 00 ba 00 04 06 10 00 81 00
10: 00 00 40 20 00 00 00 00 01 02 11 00 f1 01 00 00
20: 20 20 30 20 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a6 01 01 00

01:00.1 System peripheral: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 40 01 10 00 ba 00 80 08 10 00 80 00
10: 00 00 42 20 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 b5 10 09 86
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00

02:01.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 02 03 03 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a9 01 01 00

02:04.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 02 04 04 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a6 01 01 00

02:05.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 46 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 02 05 05 00 f1 01 00 00
20: 20 20 20 20 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a9 01 01 00

02:06.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 02 06 06 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 ad 01 01 00

02:07.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 02 07 07 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 af 01 01 00

02:08.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 02 08 08 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a6 01 01 00

02:09.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 46 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 02 09 11 00 f1 01 00 00
20: 30 20 30 20 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a9 01 01 00

05:00.0 System peripheral: Altera Corporation Device 0005 (rev 01)
00: 72 11 05 00 40 01 10 00 01 00 80 08 10 00 00 00
10: 00 00 20 20 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 72 11 05 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00

09:00.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 46 05 10 00 ba 00 04 06 10 00 81 00
10: 00 00 30 20 00 00 00 00 09 0a 11 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a9 01 01 00

09:00.1 System peripheral: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 40 01 10 00 ba 00 80 08 10 00 80 00
10: 00 00 32 20 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 b5 10 09 86
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 02 00 00

0a:01.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 0a 0b 0b 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 ad 01 01 00

0a:04.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 0a 0c 0c 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a9 01 01 00

0a:05.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 0a 0d 0d 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 ad 01 01 00

0a:06.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 0a 0e 0e 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 af 01 01 00

0a:07.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 0a 0f 0f 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a6 01 01 00

0a:08.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 0a 10 10 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 a9 01 01 00

0a:09.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba)
00: b5 10 09 86 44 05 10 00 ba 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 0a 11 11 00 f1 01 00 00
20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 ad 01 01 00


root@am57xx-evm:~# /usr/sbin/lspci -nn
00:00.0 PCI bridge [0604]: Texas Instruments Multicore DSP+ARM KeyStone II SOC [104c:8888] (rev 01)
01:00.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
01:00.1 System peripheral [0880]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
02:01.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
02:04.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
02:05.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
02:06.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
02:07.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
02:08.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
02:09.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
05:00.0 System peripheral [0880]: Altera Corporation Device [1172:0005] (rev 01)
09:00.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
09:00.1 System peripheral [0880]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
0a:01.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
0a:04.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
0a:05.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
0a:06.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
0a:07.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
0a:08.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)
0a:09.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA [10b5:8609] (rev ba)


root@am57xx-evm:~# /usr/sbin/lspci -vv
00:00.0 PCI bridge: Texas Instruments Multicore DSP+ARM KeyStone II SOC (rev 01) (prog-if 00 [Normal decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0, Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 167
        Region 0: Memory at 20100000 (64-bit, non-prefetchable) [size=1M]
        Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
        I/O behind bridge: None
        Memory behind bridge: 20200000-204fffff [size=3M]
        Prefetchable memory behind bridge: None
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ <SERR- <PERR-
        BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [50] MSI: Enable+ Count=1/1 Maskable- 64bit+
                Address: 00000000ae0f1000  Data: 0000
        Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
                DevCap: MaxPayload 256 bytes, PhantFunc 0
                        ExtTag- RBE+
                DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM L0s L1, Exit Latency L0s <512ns, L1 <64us
                        ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
                LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+
                RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-
                RootCap: CRSVisible-
                RootSta: PME ReqID 0000, PMEStatus- PMEPending-
                DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-
                         AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
                         AtomicOpsCtl: ReqEn- EgressBlck-
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [100 v2] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
                        MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
                HeaderLog: 00000000 00000000 00000000 00000000
                RootCmd: CERptEn+ NFERptEn+ FERptEn+
                RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd-
                         FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0
                ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000
        Kernel driver in use: pcieport

01:00.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba) (prog-if 00 [Normal decode])
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0, Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 168
        Region 0: Memory at 20400000 (32-bit, non-prefetchable) [size=128K]
        Bus: primary=01, secondary=02, subordinate=11, sec-latency=0
        I/O behind bridge: None
        Memory behind bridge: 20200000-203fffff [size=2M]
        Prefetchable memory behind bridge: None
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
        BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [48] MSI: Enable+ Count=1/4 Maskable+ 64bit+
                Address: 00000000ae0f1000  Data: 0001
                Masking: 00000001  Pending: 00000000
        Capabilities: [68] Express (v2) Upstream Port, MSI 00
                DevCap: MaxPayload 512 bytes, PhantFunc 0
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 0.000W
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
                        MaxPayload 128 bytes, MaxReadReq 128 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
                LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <2us
                        ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
                LnkCtl: ASPM Disabled; Disabled- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
                DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
                         AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
                         AtomicOpsCtl: EgressBlck-
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [a4] Subsystem: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA
        Capabilities: [100 v1] Device Serial Number ba-86-01-10-b5-df-0e-00
        Capabilities: [fb4 v1] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 1f, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
                        MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
                HeaderLog: 00000000 00000000 00000000 00000000
        Capabilities: [138 v1] Power Budgeting <?>
        Capabilities: [148 v1] Virtual Channel
                Caps:   LPEVC=1 RefClk=100ns PATEntryBits=4
                Arb:    Fixed+ WRR32- WRR64- WRR128-
                Ctrl:   ArbSelect=Fixed
                Status: InProgress-
                VC0:    Caps:   PATOffset=06 MaxTimeSlots=1 RejSnoopTrans-
                        Arb:    Fixed- WRR32+ WRR64- WRR128- TWRR128- WRR256-
                        Ctrl:   Enable+ ID=0 ArbSelect=WRR32 TC/VC=ff
                        Status: NegoPending- InProgress-
                        Port Arbitration Table <?>
                VC1:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
                        Arb:    Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
                        Ctrl:   Enable- ID=1 ArbSelect=Fixed TC/VC=00
                        Status: NegoPending+ InProgress-
        Capabilities: [448 v1] Vendor Specific Information: ID=0000 Rev=0 Len=0cc <?>
        Capabilities: [950 v1] Vendor Specific Information: ID=0001 Rev=0 Len=010 <?>
        Kernel driver in use: pcieport

...........
		
02:05.0 PCI bridge: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA (rev ba) (prog-if 00 [Normal decode])
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0, Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 172
        Bus: primary=02, secondary=05, subordinate=05, sec-latency=0
        I/O behind bridge: None
        Memory behind bridge: 20200000-202fffff [size=1M]
        Prefetchable memory behind bridge: None
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
        BridgeCtl: Parity+ SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [48] MSI: Enable+ Count=1/4 Maskable+ 64bit+
                Address: 00000000ae0f1000  Data: 0004
                Masking: 00000001  Pending: 00000000
        Capabilities: [68] Express (v2) Downstream Port (Slot+), MSI 00
                DevCap: MaxPayload 512 bytes, PhantFunc 0
                        ExtTag- RBE+
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
                        MaxPayload 128 bytes, MaxReadReq 128 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #5, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <2us
                        ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp-
                LnkCtl: ASPM Disabled; Disabled- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk- DLActive+ BWMgmt- ABWMgmt+
                SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
                        Slot #5, PowerLimit 25.000W; Interlock- NoCompl-
                SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
                        Control: AttnInd Off, PwrInd Off, Power- Interlock-
                SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
                        Changed: MRL- PresDet+ LinkState+
                DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported ARIFwd+
                         AtomicOpsCap: Routing-
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
                         AtomicOpsCtl: EgressBlck-
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [a4] Subsystem: PLX Technology, Inc. PEX 8609 8-lane, 8-Port PCI Express Gen 2 (5.0 GT/s) Switch with DMA
        Capabilities: [100 v1] Device Serial Number ba-86-01-10-b5-df-0e-00
        Capabilities: [fb4 v1] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 1f, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ ECRCChkEn-
                        MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
                HeaderLog: 00000000 00000000 00000000 00000000
        Capabilities: [148 v1] Virtual Channel
                Caps:   LPEVC=1 RefClk=100ns PATEntryBits=1
                Arb:    Fixed+ WRR32- WRR64- WRR128-
                Ctrl:   ArbSelect=Fixed
                Status: InProgress-
                VC0:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
                        Arb:    Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
                        Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
                        Status: NegoPending- InProgress-
                VC1:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
                        Arb:    Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256-
                        Ctrl:   Enable- ID=1 ArbSelect=Fixed TC/VC=00
                        Status: NegoPending+ InProgress-
        Capabilities: [520 v1] Access Control Services
                ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl+ DirectTrans+
                ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-
        Capabilities: [950 v1] Vendor Specific Information: ID=0001 Rev=0 Len=010 <?>
        Kernel driver in use: pcieport
		
...........
		
05:00.0 System peripheral: Altera Corporation Device 0005 (rev 01)
        Subsystem: Altera Corporation Device 0005
        Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0, Cache Line Size: 64 bytes
        Interrupt: pin A routed to IRQ 0
        Region 0: Memory at 20200000 (32-bit, non-prefetchable) [size=512K]
        Capabilities: [50] MSI: Enable- Count=1/4 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [78] Power Management version 3
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [80] Express (v2) Endpoint, MSI 00
                DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 25.000W
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM not supported
                        ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
                DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR-, OBFF Not Supported
                         AtomicOpsCap: 32bit- 64bit- 128bitCAS-
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
                         AtomicOpsCtl: ReqEn-
                LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [100 v1] Virtual Channel
                Caps:   LPEVC=0 RefClk=100ns PATEntryBits=1
                Arb:    Fixed- WRR32- WRR64- WRR128-
                Ctrl:   ArbSelect=Fixed
                Status: InProgress-
                VC0:    Caps:   PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
                        Arb:    Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
                        Ctrl:   Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
                        Status: NegoPending- InProgress-
        Capabilities: [200 v1] Vendor Specific Information: ID=1172 Rev=0 Len=044 <?>

	

内存映射:

root@am57xx-evm:~# cat /proc/iomem
20013000-2fffffff : MEM
  20100000-201fffff : 0000:00:00.0
  20200000-204fffff : PCI Bus 0000:01
    20200000-203fffff : PCI Bus 0000:02
      20200000-202fffff : PCI Bus 0000:05
        20200000-2027ffff : 0000:05:00.0
      20300000-203fffff : PCI Bus 0000:09
        20300000-2031ffff : 0000:09:00.0
        20320000-2033ffff : 0000:09:00.1
    20400000-2041ffff : 0000:01:00.0
    20420000-2043ffff : 0000:01:00.1
40300000-4037ffff : 40300000.ocmcram
40500000-405fffff : CMEM
40800000-40847fff : l2ram
40d01000-40d010ff : /ocp/mmu@40d01000
40d02000-40d020ff : /ocp/mmu@40d02000
40e00000-40e07fff : l1pram
40f00000-40f07fff : l1dram
41000000-41047fff : l2ram
41501000-415010ff : /ocp/mmu@41501000
41502000-415020ff : /ocp/mmu@41502000
41600000-41607fff : l1pram
41700000-41707fff : l1dram
43300000-433fffff : edma3_cc
44000000-44ffffff : /ocp
45000000-45000fff : /ocp
48020000-4802001f : serial
48032000-4803207f : /ocp/timer@48032000
48034000-4803407f : /ocp/timer@48034000
48036000-4803607f : /ocp/timer@48036000
4803e000-4803e07f : /ocp/timer@4803e000
48051000-480511ff : /ocp/gpio@48051000
48053000-480531ff : /ocp/gpio@48053000
48055000-480551ff : /ocp/gpio@48055000
48057000-480571ff : /ocp/gpio@48057000
48059000-480591ff : /ocp/gpio@48059000
4805b000-4805b1ff : /ocp/gpio@4805b000
4805d000-4805d1ff : /ocp/gpio@4805d000
48060000-480600ff : /ocp/i2c@48060000
48070000-480700ff : /ocp/i2c@48070000
4807c000-4807c0ff : /ocp/i2c@4807c000
48086000-4808607f : /ocp/timer@48086000
48088000-4808807f : /ocp/timer@48088000
48090000-48091fff : /ocp/rng@48090000
4809c000-4809c3ff : /ocp/mmc@4809c000
480a5000-480a509f : /ocp/des@480a5000
48422000-4842201f : serial
48440200-4844027f : /ocp/epwmss@48440000/pwm@48440200
4844a000-4844ad1b : /ocp/padconf@4844a000
48484000-48484fff : /ocp/ethernet@48484000
48485000-484850ff : /ocp/ethernet@48484000/mdio@48485000
48485200-48487fff : /ocp/ethernet@48484000
48820000-4882007f : /ocp/timer@48820000
48822000-4882207f : /ocp/timer@48822000
48824000-4882407f : /ocp/timer@48824000
48826000-4882607f : /ocp/timer@48826000
48828000-4882807f : /ocp/timer@48828000
4882a000-4882a07f : /ocp/timer@4882a000
4882c000-4882c07f : /ocp/timer@4882c000
4882e000-4882e07f : /ocp/timer@4882e000
48838000-488380ff : /ocp/rtc@48838000
48840000-488401ff : /ocp/mailbox@48840000
48842000-488421ff : /ocp/mailbox@48842000
48880000-4888ffff : /ocp/omap_dwc3_1@48880000
48890000-48897fff : /ocp/omap_dwc3_1@48880000/usb@48890000
  48890000-48897fff : /ocp/omap_dwc3_1@48880000/usb@48890000
4889c100-488a6fff : /ocp/omap_dwc3_1@48880000/usb@48890000
488c0000-488cffff : /ocp/omap_dwc3_2@488c0000
488d0000-488d7fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
  488d0000-488d7fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
488dc100-488e6fff : /ocp/omap_dwc3_2@488c0000/usb@488d0000
489d0700-489d077f : sc
489d5700-489d5717 : csc
4a0021e0-4a0021eb : /ocp/bandgap@4a0021e0
4a00232c-4a002337 : /ocp/bandgap@4a0021e0
4a002380-4a0023ab : /ocp/bandgap@4a0021e0
4a0023c0-4a0023fb : /ocp/bandgap@4a0021e0
4a00246c-4a00246f : ldo-address
4a002470-4a002473 : ldo-address
4a002554-4a002557 : gmii-sel
4a002564-4a00256b : /ocp/bandgap@4a0021e0
4a002574-4a0025c3 : /ocp/bandgap@4a0021e0
4a002b78-4a002c73 : /ocp/l4@4a000000/scm@2000/dma-router@b78
4a002c78-4a002cf3 : /ocp/l4@4a000000/scm@2000/dma-router@c78
4a003400-4a003867 : pinctrl-single
4a056000-4a056fff : omap_dma_system.0
  4a056000-4a056fff : /ocp/dma-controller@4a056000
4a080000-4a08001f : /ocp/ocp2scp@4a080000
4a084000-4a0843ff : /ocp/ocp2scp@4a080000/phy@4a084000
4a084c00-4a084c3f : pll_ctrl
4a085000-4a0853ff : /ocp/ocp2scp@4a080000/phy@4a085000
4a090000-4a09001f : /ocp/ocp2scp@4a090000
4a094000-4a09407f : phy_rx
4a094400-4a094463 : phy_tx
4a096800-4a09683f : pll_ctrl
4a140000-4a1410ff : /ocp/sata@4a141100
4ae07ddc-4ae07ddf : setup-address
4ae07de0-4ae07de3 : control-address
4ae07de4-4ae07de7 : setup-address
4ae07de8-4ae07deb : control-address
4ae07e20-4ae07e23 : control-address
4ae07e24-4ae07e27 : control-address
4ae07e30-4ae07e33 : setup-address
4ae07e34-4ae07e37 : setup-address
4ae0c154-4ae0c157 : ldo-address
4ae0c158-4ae0c15b : ldo-address
4ae10000-4ae101ff : /ocp/gpio@4ae10000
4ae14000-4ae1407f : /ocp/wdt@4ae14000
4ae20000-4ae2007f : /ocp/timer@4ae20000
4b101000-4b1012ff : /ocp/sham@53100000
4b220000-4b221fff : intc
4b222000-4b2223ff : control
4b222400-4b2224ff : debug
4b224000-4b2243ff : control
4b224400-4b2244ff : debug
4b234000-4b236fff : iram
4b238000-4b23afff : iram
4b2a0000-4b2a1fff : intc
4b2a2000-4b2a23ff : control
4b2a2400-4b2a24ff : debug
4b2a4000-4b2a43ff : control
4b2a4400-4b2a44ff : debug
4b2b4000-4b2b6fff : iram
4b2b8000-4b2bafff : iram
4b500000-4b50009f : /ocp/aes@4b500000
4b700000-4b70009f : /ocp/aes@4b700000
55020000-5502ffff : l2ram
55082000-550820ff : /ocp/mmu@55082000
58000000-5800007f : dss
58001000-58001fff : /ocp/dss@58000000/dispc@58001000
58004054-58004057 : pll1_clkctrl
58004300-5800431f : pll1
58009054-58009057 : pll2_clkctrl
58009300-5800931f : pll2
58040000-580401ff : wp
58040200-5804027f : pll
58040300-5804037f : phy
58060000-58078fff : core
58820000-5882ffff : l2ram
58882000-588820ff : /ocp/mmu@58882000
80000000-9fffffff : System RAM
  80008000-80dfffff : Kernel code
  81000000-8109ebdf : Kernel data
a0000000-abffffff : CMEM
ac000000-ffcfffff : System RAM

我的引导日志:

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.79-gbde58ab01e (khrenkov@khrenkov-sitar) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #6 SMP PREEMPT Thu Dec 23 12:04:11 +07 2021
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt: Machine model: TI AM5728 EVM
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000fe400000
[    0.000000] OMAP4: Map 0x00000000ffd00000 to fe600000 for dram barrier
[    0.000000] On node 0 totalpages: 474368
[    0.000000] free_area_init_node: node 0, pgdat c1053d80, node_mem_map eeda2000
[    0.000000]   DMA zone: 1728 pages used for memmap
[    0.000000]   DMA zone: 0 pages reserved
[    0.000000]   DMA zone: 147456 pages, LIFO batch:31
[    0.000000]   HighMem zone: 326912 pages, LIFO batch:31
[    0.000000] DRA752 ES2.0
[    0.000000] percpu: Embedded 15 pages/cpu @eed2a000 s31372 r8192 d21876 u61440
[    0.000000] pcpu-alloc: s31372 r8192 d21876 u61440 alloc=15*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 472640
[    0.000000] Kernel command line: console=ttyO2,115200n8 root=/dev/nfs nfsroot=192.168.9.168:/home/khrenkov/Sitara/SDK/customNFS,nolock,v3,tcp,rsize=4096,wsize=4096 rw ip=dhcp
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1675580K/1897472K available (8192K kernel code, 347K rwdata, 2564K rodata, 2048K init, 282K bss, 33476K reserved, 188416K cma-reserved, 1283072K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0a00000   (10208 kB)
[    0.000000]       .init : 0xc0e00000 - 0xc1000000   (2048 kB)
[    0.000000]       .data : 0xc1000000 - 0xc1056e98   ( 348 kB)
[    0.000000]        .bss : 0xc1058000 - 0xc109ebe0   ( 283 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Tasks RCU enabled.
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000004] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000016] Switching to timer-based delay loop, resolution 162ns
[    0.000362] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000371] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000894] Console: colour dummy device 80x30
[    0.000912] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
[    0.000919] This ensures that you still see kernel messages. Please
[    0.000926] update your kernel commandline.
[    0.000948] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.000962] pid_max: default: 32768 minimum: 301
[    0.001081] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001095] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001627] CPU: Testing write buffer coherency: ok
[    0.001664] CPU0: Spectre v2: using ICIALLU workaround
[    0.001859] /cpus/cpu@0 missing clock-frequency property
[    0.001879] /cpus/cpu@1 missing clock-frequency property
[    0.001890] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.039846] Setting up static identity map for 0x80200000 - 0x80200060
[    0.059859] Hierarchical SRCU implementation.
[    0.080045] EFI services will not be available.
[    0.099913] smp: Bringing up secondary CPUs ...
[    0.170289] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.170294] CPU1: Spectre v2: using ICIALLU workaround
[    0.170395] smp: Brought up 1 node, 2 CPUs
[    0.170406] SMP: Total of 2 processors activated (24.59 BogoMIPS).
[    0.170414] CPU: All CPU(s) started in HYP mode.
[    0.170421] CPU: Virtualization extensions available.
[    0.170960] devtmpfs: initialized
[    0.191448] random: get_random_u32 called from bucket_table_alloc+0x108/0x230 with crng_init=0
[    0.191701] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.191897] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.191912] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.195659] pinctrl core: initialized pinctrl subsystem
[    0.196118] DMI not present or invalid.
[    0.196371] NET: Registered protocol family 16
[    0.197415] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.198355] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.307851] omap_hwmod: dcan1: _wait_target_disable failed
[    0.419754] cpuidle: using governor ladder
[    0.419786] cpuidle: using governor menu
[    0.428244] gpio gpiochip0: (gpio): added GPIO chardev (254:0)
[    0.428313] gpiochip_setup_dev: registered GPIOs 0 to 31 on device: gpiochip0 (gpio)
[    0.428373] OMAP GPIO hardware version 0.1
[    0.429011] gpio gpiochip1: (gpio): added GPIO chardev (254:1)
[    0.429078] gpiochip_setup_dev: registered GPIOs 32 to 63 on device: gpiochip1 (gpio)
[    0.429748] gpio gpiochip2: (gpio): added GPIO chardev (254:2)
[    0.429814] gpiochip_setup_dev: registered GPIOs 64 to 95 on device: gpiochip2 (gpio)
[    0.430524] gpio gpiochip3: (gpio): added GPIO chardev (254:3)
[    0.430594] gpiochip_setup_dev: registered GPIOs 96 to 127 on device: gpiochip3 (gpio)
[    0.431259] gpio gpiochip4: (gpio): added GPIO chardev (254:4)
[    0.431325] gpiochip_setup_dev: registered GPIOs 128 to 159 on device: gpiochip4 (gpio)
[    0.432000] gpio gpiochip5: (gpio): added GPIO chardev (254:5)
[    0.432065] gpiochip_setup_dev: registered GPIOs 160 to 191 on device: gpiochip5 (gpio)
[    0.432717] gpio gpiochip6: (gpio): added GPIO chardev (254:6)
[    0.432784] gpiochip_setup_dev: registered GPIOs 192 to 223 on device: gpiochip6 (gpio)
[    0.433460] gpio gpiochip7: (gpio): added GPIO chardev (254:7)
[    0.433525] gpiochip_setup_dev: registered GPIOs 224 to 255 on device: gpiochip7 (gpio)
[    0.455805] No ATAGs?
[    0.455879] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.455893] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.456284] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.456295] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.456834] OMAP DMA hardware revision 0.0
[    0.466750] edma 43300000.edma: memcpy is disabled
[    0.469983] edma 43300000.edma: TI EDMA DMA engine driver
[    0.476801] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.477175] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-mmcwl[0]' - status (0)
[    0.477430] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-com_3v6[0]'
[    0.477840] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-main_12v0[0]'
[    0.478069] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-evm_5v0[0]'
[    0.478119] evm_5v0: supplied by main_12v0
[    0.478373] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-vdd_3v3[0]'
[    0.478521] com_3v6: supplied by evm_5v0
[    0.478644] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-aic_dvdd[0]'
[    0.478694] aic_dvdd_fixed: supplied by vdd_3v3
[    0.478932] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-vtt[0]' - status (0)
[    0.481400] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.481593] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.481831] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.482078] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.482421] omap-iommu 41501000.mmu: 41501000.mmu registered
[    0.482627] omap-iommu 41502000.mmu: 41502000.mmu registered
[    0.482888] iommu: Adding device 58820000.ipu to group 1
[    0.482976] iommu: Adding device 55020000.ipu to group 2
[    0.483134] iommu: Adding device 40800000.dsp to group 0
[    0.483393] iommu: Adding device 41000000.dsp to group 3
[    0.485650] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[    0.486151] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz
[    0.486636] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
[    0.486804] media: Linux media interface: v0.10
[    0.486841] Linux video capture interface: v2.00
[    0.486918] pps_core: LinuxPPS API ver. 1 registered
[    0.486927] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.486947] PTP clock support registered
[    0.486975] EDAC MC: Ver: 3.0.0
[    0.487223] dmi: Firmware registration failed.
[    0.487611] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    0.487881] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[    0.488201] Advanced Linux Sound Architecture Driver Initialized.
[    0.488908] clocksource: Switched to clocksource arch_sys_counter
[    0.496604] NET: Registered protocol family 2
[    0.497116] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.497180] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.497306] TCP: Hash tables configured (established 8192 bind 8192)
[    0.497374] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.497407] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.497533] NET: Registered protocol family 1
[    0.497818] RPC: Registered named UNIX socket transport module.
[    0.497827] RPC: Registered udp transport module.
[    0.497835] RPC: Registered tcp transport module.
[    0.497843] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.497855] PCI: CLS 0 bytes, default 64
[    0.498748] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    0.498966] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[    0.499951] workingset: timestamp_bits=14 max_order=19 bucket_order=5
[    0.504174] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.504685] NFS: Registering the id_resolver key type
[    0.504708] Key type id_resolver registered
[    0.504717] Key type id_legacy registered
[    0.504754] ntfs: driver 2.1.32 [Flags: R/O].
[    0.506074] bounce: pool size: 64 pages
[    0.506118] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.506129] io scheduler noop registered
[    0.506138] io scheduler deadline registered
[    0.506238] io scheduler cfq registered (default)
[    0.506247] io scheduler mq-deadline registered
[    0.506256] io scheduler kyber registered
[    0.510548] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[    0.513737] dra7-pcie 51000000.pcie: Linked as a consumer to phy-4a094000.pciephy.1
[    0.513896] dra7-pcie 51000000.pcie: GPIO lookup for consumer (null)
[    0.513908] dra7-pcie 51000000.pcie: using device tree for GPIO lookup
[    0.513943] of_get_named_gpiod_flags: parsed 'gpios' property of node '/ocp/axi@0/pcie@51000000[0]' - status (0)
[    0.514106] OF: PCI: host bridge /ocp/axi@0/pcie@51000000 ranges:
[    0.514140] OF: PCI:    IO 0x20003000..0x20012fff -> 0x00000000
[    0.514162] OF: PCI:   MEM 0x20013000..0x2fffffff -> 0x20013000
[    0.614247] dra7-pcie 51000000.pcie: link up
[    0.614384] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
[    0.614397] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.614408] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    0.614418] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[    0.614452] pci 0000:00:00.0: [104c:8888] type 01 class 0x060400
[    0.614485] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit]
[    0.614545] pci 0000:00:00.0: supports D1
[    0.614555] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    0.614738] PCI: bus0: Fast back to back transfers disabled
[    0.614890] pci 0000:01:00.0: [10b5:8609] type 01 class 0x060400
[    0.615034] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[    0.615476] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
[    0.615750] pci 0000:01:00.1: [10b5:8609] type 00 class 0x088000
[    0.615866] pci 0000:01:00.1: reg 0x10: [mem 0x00000000-0x0001ffff]
[    0.616061] pci 0000:01:00.1: enabling Extended Tags
[    0.639070] PCI: bus1: Fast back to back transfers disabled
[    0.639089] pci 0000:01:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.639386] pci 0000:02:01.0: [10b5:8609] type 01 class 0x060400
[    0.639930] pci 0000:02:01.0: PME# supported from D0 D3hot D3cold
[    0.640224] pci 0000:02:04.0: [10b5:8609] type 01 class 0x060400
[    0.640768] pci 0000:02:04.0: PME# supported from D0 D3hot D3cold
[    0.641053] pci 0000:02:05.0: [10b5:8609] type 01 class 0x060400
[    0.641596] pci 0000:02:05.0: PME# supported from D0 D3hot D3cold
[    0.641885] pci 0000:02:06.0: [10b5:8609] type 01 class 0x060400
[    0.642429] pci 0000:02:06.0: PME# supported from D0 D3hot D3cold
[    0.642724] pci 0000:02:07.0: [10b5:8609] type 01 class 0x060400
[    0.643267] pci 0000:02:07.0: PME# supported from D0 D3hot D3cold
[    0.643568] pci 0000:02:08.0: [10b5:8609] type 01 class 0x060400
[    0.644113] pci 0000:02:08.0: PME# supported from D0 D3hot D3cold
[    0.644419] pci 0000:02:09.0: [10b5:8609] type 01 class 0x060400
[    0.644964] pci 0000:02:09.0: PME# supported from D0 D3hot D3cold
[    0.645551] PCI: bus2: Fast back to back transfers disabled
[    0.645569] pci 0000:02:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.645606] pci 0000:02:04.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.645642] pci 0000:02:05.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.645678] pci 0000:02:06.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.645714] pci 0000:02:07.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.645750] pci 0000:02:08.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.645785] pci 0000:02:09.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.646014] PCI: bus3: Fast back to back transfers enabled
[    0.646027] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
[    0.646245] PCI: bus4: Fast back to back transfers enabled
[    0.646257] pci_bus 0000:04: busn_res: [bus 04-ff] end is updated to 04
[    0.646549] pci 0000:05:00.0: [1172:0005] type 00 class 0x088000
[    0.646687] pci 0000:05:00.0: reg 0x10: [mem 0x00000000-0x0007ffff]
[    0.647519] PCI: bus5: Fast back to back transfers disabled
[    0.647532] pci_bus 0000:05: busn_res: [bus 05-ff] end is updated to 05
[    0.647752] PCI: bus6: Fast back to back transfers enabled
[    0.647764] pci_bus 0000:06: busn_res: [bus 06-ff] end is updated to 06
[    0.647986] PCI: bus7: Fast back to back transfers enabled
[    0.647998] pci_bus 0000:07: busn_res: [bus 07-ff] end is updated to 07
[    0.648220] PCI: bus8: Fast back to back transfers enabled
[    0.648232] pci_bus 0000:08: busn_res: [bus 08-ff] end is updated to 08
[    0.648510] pci 0000:09:00.0: [10b5:8609] type 01 class 0x060400
[    0.648660] pci 0000:09:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[    0.649158] pci 0000:09:00.0: PME# supported from D0 D3hot D3cold
[    0.649496] pci 0000:09:00.1: [10b5:8609] type 00 class 0x088000
[    0.649617] pci 0000:09:00.1: reg 0x10: [mem 0x00000000-0x0001ffff]
[    0.649827] pci 0000:09:00.1: enabling Extended Tags
[    0.650618] PCI: bus9: Fast back to back transfers disabled
[    0.650635] pci 0000:09:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.650944] pci 0000:0a:01.0: [10b5:8609] type 01 class 0x060400
[    0.651525] pci 0000:0a:01.0: PME# supported from D0 D3hot D3cold
[    0.651827] pci 0000:0a:04.0: [10b5:8609] type 01 class 0x060400
[    0.652405] pci 0000:0a:04.0: PME# supported from D0 D3hot D3cold
[    0.652701] pci 0000:0a:05.0: [10b5:8609] type 01 class 0x060400
[    0.653283] pci 0000:0a:05.0: PME# supported from D0 D3hot D3cold
[    0.653585] pci 0000:0a:06.0: [10b5:8609] type 01 class 0x060400
[    0.654164] pci 0000:0a:06.0: PME# supported from D0 D3hot D3cold
[    0.654471] pci 0000:0a:07.0: [10b5:8609] type 01 class 0x060400
[    0.655052] pci 0000:0a:07.0: PME# supported from D0 D3hot D3cold
[    0.655362] pci 0000:0a:08.0: [10b5:8609] type 01 class 0x060400
[    0.655940] pci 0000:0a:08.0: PME# supported from D0 D3hot D3cold
[    0.656258] pci 0000:0a:09.0: [10b5:8609] type 01 class 0x060400
[    0.656838] pci 0000:0a:09.0: PME# supported from D0 D3hot D3cold
[    0.657451] PCI: bus10: Fast back to back transfers disabled
[    0.657470] pci 0000:0a:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.657508] pci 0000:0a:04.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.657545] pci 0000:0a:05.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.657583] pci 0000:0a:06.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.657619] pci 0000:0a:07.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.657656] pci 0000:0a:08.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.657692] pci 0000:0a:09.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    0.657933] PCI: bus11: Fast back to back transfers enabled
[    0.657945] pci_bus 0000:0b: busn_res: [bus 0b-ff] end is updated to 0b
[    0.658182] PCI: bus12: Fast back to back transfers enabled
[    0.658194] pci_bus 0000:0c: busn_res: [bus 0c-ff] end is updated to 0c
[    0.658425] PCI: bus13: Fast back to back transfers enabled
[    0.658436] pci_bus 0000:0d: busn_res: [bus 0d-ff] end is updated to 0d
[    0.658667] PCI: bus14: Fast back to back transfers enabled
[    0.658678] pci_bus 0000:0e: busn_res: [bus 0e-ff] end is updated to 0e
[    0.658933] PCI: bus15: Fast back to back transfers enabled
[    0.658945] pci_bus 0000:0f: busn_res: [bus 0f-ff] end is updated to 0f
[    0.659178] PCI: bus16: Fast back to back transfers enabled
[    0.659190] pci_bus 0000:10: busn_res: [bus 10-ff] end is updated to 10
[    0.659422] PCI: bus17: Fast back to back transfers enabled
[    0.659434] pci_bus 0000:11: busn_res: [bus 11-ff] end is updated to 11
[    0.659457] pci_bus 0000:0a: busn_res: [bus 0a-ff] end is updated to 11
[    0.659478] pci_bus 0000:09: busn_res: [bus 09-ff] end is updated to 11
[    0.659500] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 11
[    0.660088] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff 64bit]
[    0.660107] pci 0000:00:00.0: BAR 8: assigned [mem 0x20200000-0x204fffff]
[    0.660122] pci 0000:01:00.0: BAR 8: assigned [mem 0x20200000-0x203fffff]
[    0.660134] pci 0000:01:00.0: BAR 0: assigned [mem 0x20400000-0x2041ffff]
[    0.660156] pci 0000:01:00.1: BAR 0: assigned [mem 0x20420000-0x2043ffff]
[    0.660181] pci 0000:02:05.0: BAR 8: assigned [mem 0x20200000-0x202fffff]
[    0.660192] pci 0000:02:09.0: BAR 8: assigned [mem 0x20300000-0x203fffff]
[    0.660203] pci 0000:02:01.0: PCI bridge to [bus 03]
[    0.660258] pci 0000:02:04.0: PCI bridge to [bus 04]
[    0.660314] pci 0000:05:00.0: BAR 0: assigned [mem 0x20200000-0x2027ffff]
[    0.660336] pci 0000:02:05.0: PCI bridge to [bus 05]
[    0.660361] pci 0000:02:05.0:   bridge window [mem 0x20200000-0x202fffff]
[    0.660400] pci 0000:02:06.0: PCI bridge to [bus 06]
[    0.660453] pci 0000:02:07.0: PCI bridge to [bus 07]
[    0.660506] pci 0000:02:08.0: PCI bridge to [bus 08]
[    0.660562] pci 0000:09:00.0: BAR 0: assigned [mem 0x20300000-0x2031ffff]
[    0.660583] pci 0000:09:00.1: BAR 0: assigned [mem 0x20320000-0x2033ffff]
[    0.660606] pci 0000:0a:01.0: PCI bridge to [bus 0b]
[    0.660659] pci 0000:0a:04.0: PCI bridge to [bus 0c]
[    0.660712] pci 0000:0a:05.0: PCI bridge to [bus 0d]
[    0.660765] pci 0000:0a:06.0: PCI bridge to [bus 0e]
[    0.660818] pci 0000:0a:07.0: PCI bridge to [bus 0f]
[    0.660871] pci 0000:0a:08.0: PCI bridge to [bus 10]
[    0.660924] pci 0000:0a:09.0: PCI bridge to [bus 11]
[    0.660977] pci 0000:09:00.0: PCI bridge to [bus 0a-11]
[    0.661030] pci 0000:02:09.0: PCI bridge to [bus 09-11]
[    0.661054] pci 0000:02:09.0:   bridge window [mem 0x20300000-0x203fffff]
[    0.661092] pci 0000:01:00.0: PCI bridge to [bus 02-11]
[    0.661117] pci 0000:01:00.0:   bridge window [mem 0x20200000-0x203fffff]
[    0.661155] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    0.661167] pci 0000:00:00.0:   bridge window [mem 0x20200000-0x204fffff]
[    0.661497] pcieport 0000:00:00.0: Signaling PME with IRQ 167
[    0.661858] pcieport 0000:00:00.0: AER enabled with IRQ 167
[    0.662044] pcieport 0000:01:00.0: enabling device (0140 -> 0142)
[    0.665361] pcieport 0000:02:05.0: enabling device (0140 -> 0142)
[    0.669796] pcieport 0000:02:09.0: enabling device (0140 -> 0142)
[    0.670922] pcieport 0000:09:00.0: enabling device (0140 -> 0142)
[    0.680573] pwm-backlight backlight: GPIO lookup for consumer enable
[    0.680585] pwm-backlight backlight: using device tree for GPIO lookup
[    0.680598] of_get_named_gpiod_flags: can't parse 'enable-gpios' property of node '/backlight[0]'
[    0.680610] of_get_named_gpiod_flags: can't parse 'enable-gpio' property of node '/backlight[0]'
[    0.680619] pwm-backlight backlight: using lookup tables for GPIO lookup
[    0.680629] pwm-backlight backlight: lookup for GPIO enable failed
[    0.680651] pwm-backlight backlight: backlight supply power not found, using dummy regulator
[    0.725461] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    0.728182] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 45, base_baud = 3000000) is a 8250
[    2.821555] console [ttyS2] enabled
[    2.825883] 48422000.serial: ttyS7 at MMIO 0x48422000 (irq = 46, base_baud = 3000000) is a 8250
[    2.836512] omap_rng 48090000.rng: Random Number Generator ver. 20
[    2.843232] omapdss_dss 58000000.dss: 58000000.dss supply vdda_video not found, using dummy regulator
[    2.852724] DSS: OMAP DSS rev 6.1
[    2.857681] omapdss_dss 58000000.dss: bound 58001000.dispc (ops dispc_component_ops)
[    2.866106] omapdss_dss 58000000.dss: bound 58040000.encoder (ops hdmi5_component_ops)
[    2.875092] tpd12s015 encoder: GPIO lookup for consumer (null)
[    2.880975] tpd12s015 encoder: using device tree for GPIO lookup
[    2.887037] of_get_named_gpiod_flags: parsed 'gpios' property of node '/encoder[0]' - status (0)
[    2.895886] tpd12s015 encoder: GPIO lookup for consumer (null)
[    2.901762] tpd12s015 encoder: using device tree for GPIO lookup
[    2.907829] of_get_named_gpiod_flags: parsed 'gpios' property of node '/encoder[1]' - status (0)
[    2.916674] tpd12s015 encoder: GPIO lookup for consumer (null)
[    2.922549] tpd12s015 encoder: using device tree for GPIO lookup
[    2.928628] of_get_named_gpiod_flags: parsed 'gpios' property of node '/encoder[2]' - status (0)
[    2.938296] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[    2.957139] brd: module loaded
[    2.965658] loop: module loaded
[    2.971734] mdio_bus fixed-0: GPIO lookup for consumer reset
[    2.977420] mdio_bus fixed-0: using lookup tables for GPIO lookup
[    2.983566] mdio_bus fixed-0: lookup for GPIO reset failed
[    2.989126] libphy: Fixed MDIO Bus: probed
[    2.995824] mdio_bus 48485000.mdio: GPIO lookup for consumer reset
[    3.002059] mdio_bus 48485000.mdio: using device tree for GPIO lookup
[    3.008535] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    3.019650] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    3.030670] mdio_bus 48485000.mdio: using lookup tables for GPIO lookup
[    3.037315] mdio_bus 48485000.mdio: lookup for GPIO reset failed
[    3.098938] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[    3.106632] libphy: 48485000.mdio: probed
[    3.115804] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver Micrel KSZ9031 Gigabit PHY
[    3.125548] davinci_mdio 48485000.mdio: phy[2]: device 48485000.mdio:02, driver Micrel KSZ9031 Gigabit PHY
[    3.135856] cpsw 48484000.ethernet: Detected MACID = b0:7e:11:52:23:5f
[    3.142491] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[    3.148873] cpsw 48484000.ethernet: ALE Table size 1024
[    3.154172] cpsw 48484000.ethernet: device node lookup for pps timer failed
[    3.161220] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[    3.169118] cpsw 48484000.ethernet: cpsw: Detected MACID = b0:7e:11:52:23:5f
[    3.177313] i2c /dev entries driver
[    3.181723] IR NEC protocol handler initialized
[    3.186276] IR RC5(x/sz) protocol handler initialized
[    3.191374] IR RC6 protocol handler initialized
[    3.195925] IR JVC protocol handler initialized
[    3.200492] IR Sony protocol handler initialized
[    3.205129] IR SANYO protocol handler initialized
[    3.209992] IR Sharp protocol handler initialized
[    3.214715] IR MCE Keyboard/mouse protocol handler initialized
[    3.220589] IR XMP protocol handler initialized
[    3.249005] tmp102 0-0048: error reading config register
[    3.254471] tmp102: probe of 0-0048 failed with error -121
[    3.262882] sdhci: Secure Digital Host Controller Interface driver
[    3.269116] sdhci: Copyright(c) Pierre Ossman
[    3.274019] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.280757] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    3.286794] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.293386] of_get_named_gpiod_flags: can't parse 'cd-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.302581] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.311685] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.318418] sdhci-omap 4809c000.mmc: lookup for GPIO cd failed
[    3.324295] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    3.330341] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.336899] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.346089] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.355187] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.361933] sdhci-omap 4809c000.mmc: lookup for GPIO wp failed
[    3.367944] sdhci-omap 4809c000.mmc: 4809c000.mmc supply vqmmc not found, using dummy regulator
[    3.377023] sdhci-omap 4809c000.mmc: no pinctrl state for hs200_1_8v mode
[    3.438964] mmc0: SDHCI controller on 4809c000.mmc [4809c000.mmc] using ADMA
[    3.447634] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led0[0]' - status (0)
[    3.458707] no flags found for gpios
[    3.462442] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led1[0]' - status (0)
[    3.471553] no flags found for gpios
[    3.475331] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led2[0]' - status (0)
[    3.484440] no flags found for gpios
[    3.488232] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led3[0]' - status (0)
[    3.497284] no flags found for gpios
[    3.502027] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led4[0]' - status (0)
[    3.513093] no flags found for gpios
[    3.516804] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led5[0]' - status (0)
[    3.525854] no flags found for gpios
[    3.529962] ledtrig-cpu: registered to indicate activity on CPUs
[    3.539790] NET: Registered protocol family 10
[    3.545078] Segment Routing with IPv6
[    3.548808] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    3.555218] NET: Registered protocol family 17
[    3.559910] Key type dns_resolver registered
[    3.564346] omap_voltage_late_init: Voltage driver support not added
[    3.570782] Power Management for TI OMAP4+ devices.
[    3.576985] Registering SWP/SWPB emulation handler
[    3.595129] dmm 4e000000.dmm: workaround for errata i878 in use
[    3.602726] dmm 4e000000.dmm: initialized all PAT entries
[    3.608585] omapdss_hdmi5 58040000.encoder: 58040000.encoder supply vdda not found, using dummy regulator
[    3.619855] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    3.626500] [drm] No driver support for vblank timestamp query.
[    3.632514] [drm] Cannot find any crtc or sizes
[    3.638141] [drm] Initialized omapdrm 1.0.0 20110917 for omapdrm.0 on minor 0
[    3.646404] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER5[0]' - status (0)
[    3.656080] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER4[0]' - status (0)
[    3.665721] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER3[0]' - status (0)
[    3.675366] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER2[0]' - status (0)
[    3.685009] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER1[0]' - status (0)
[    3.694751] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[    3.702396] hctosys: unable to open rtc device (rtc0)
[    3.708625] net eth0: initializing cpsw version 1.15 (0)
[    3.716128] mmc0: host does not support reading read-only switch, assuming write-enable
[    3.726127] mmc0: new high speed SDHC card at address 0001
[    3.731969] mmcblk0: mmc0:0001 SD32G 29.1 GiB
[    3.737351]  mmcblk0: p1 p2
[    3.839706] Micrel KSZ9031 Gigabit PHY 48485000.mdio:00: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:00, irq=POLL)
[    3.860333] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[    3.866731] net eth1: initializing cpsw version 1.15 (0)
[    3.989385] Micrel KSZ9031 Gigabit PHY 48485000.mdio:02: attached PHY driver [Micrel KSZ9031 Gigabit PHY] (mii_bus:phy_addr=48485000.mdio:02, irq=POLL)
[    4.008209] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[    4.648955] [drm] Cannot find any crtc or sizes
[    8.177597] cpsw 48484000.ethernet eth1: Link is Up - 1Gbps/Full - flow control rx/tx
[    8.185508] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
[    8.208931] Sending DHCP requests ., OK
[    8.252813] IP-Config: Got DHCP answer from 192.168.8.1, my address is 192.168.8.167
[    8.260629] IP-Config: Complete:
[    8.263876]      device=eth1, hwaddr=b0:7e:11:52:23:5f, ipaddr=192.168.8.167, mask=255.255.252.0, gw=192.168.8.17
[    8.274207]      host=192.168.8.167, domain=tetz, nis-domain=(none)
[    8.281030]      bootserver=0.0.0.0, rootserver=192.168.9.168, rootpath=     nameserver0=192.168.8.1
[    8.296513] vmmcwl_fixed: disabling
[    8.300049] aic_dvdd_fixed: disabling
[    8.303735] ALSA device list:
[    8.306716]   No soundcards found.
[    8.338962] VFS: Mounted root (nfs filesystem) on device 0:15.
[    8.346076] devtmpfs: mounted
[    8.350327] Freeing unused kernel memory: 2048K
[    8.374241] random: fast init done
[    8.816851] systemd[1]: System time before build time, advancing clock.
[    8.884912] systemd[1]: systemd 234 running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR +SMACK +SYSVINIT +UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN default-hierarchy=hybrid)
[    8.906249] systemd[1]: Detected architecture arm.

Welcome to Arago 2018.10!

[    8.951903] systemd[1]: Set hostname to <am57xx-evm>.
[   10.093335] random: systemd: uninitialized urandom read (16 bytes read)
[   10.138311] systemd[1]: Listening on Process Core Dump Socket.
[  OK  ] Listening on Process Core Dump Socket.
[   10.169042] random: systemd: uninitialized urandom read (16 bytes read)
[   10.175722] systemd[1]: Reached target Remote File Systems.
[  OK  ] Reached target Remote File Systems.
[   10.209009] random: systemd: uninitialized urandom read (16 bytes read)
[   10.217478] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[   10.322255] random: crng init done
[   10.334095] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Started Forward Password Requests to Wall Directory Watch.
[   10.369976] systemd[1]: Created slice System Slice.
[  OK  ] Created slice System Slice.
[   10.409093] systemd[1]: Reached target Slices.
[  OK  ] Reached target Slices.
[   10.441877] systemd[1]: Mounting POSIX Message Queue File System...
         Mounting POSIX Message Queue File System...
[  OK  ] Listening on Journal Socket (/dev/log).
[  OK  ] Listening on udev Control Socket.
[  OK  ] Listening on Network Service Netlink Socket.
[  OK  ] Listening on udev Kernel Socket.
[  OK  ] Reached target Swap.
         Mounting Temporary Directory (/tmp)...
[  OK  ] Created slice system-getty.slice.
[  OK  ] Listening on Journal Socket.
         Starting Remount Root and Kernel File Systems...
         Starting Create list of required st…ce nodes for the current kernel...
         Starting Load Kernel Modules...
[  OK  ] Listening on /dev/initctl Compatibility Named Pipe.
[  OK  ] Created slice system-serial\x2dgetty.slice.
         Mounting Kernel Debug File System...
[   10.927142] cmemk: loading out-of-tree module taints kernel.
[   10.933854] CMEMK module: reference Linux version 4.14.79
[   10.940136] allocated heap buffer 0x40500000 of size 0x100000
[   10.946066] cmemk initialized
[  OK  ] Started Dispatch Password Requests to Console[   10.964817] cryptodev: driver 1.9 loaded.
 Directory Watch.
[  OK  ] Reached target Paths.
[  OK  ] Listening on Syslog Socket.
         Starting Journal Service...
[  OK  ] Mounted Kernel Debug File System.
[  OK  ] Mounted POSIX Message Queue File System.
[  OK  ] Mounted Temporary Directory (/tmp).
[  OK  ] Started Remount Root and Kernel File Systems.
[  OK  ] Started Create list of required sta…vice nodes for the current kernel.
[  OK  ] Started Load Kernel Modules.
         Starting Apply Kernel Variables...
         Mounting Kernel Configuration File System...
         Starting Create Static Device Nodes in /dev...
         Starting udev Coldplug all Devices...
[  OK  ] Mounted Kernel Configuration File System.
[  OK  ] Started Journal Service.
[  OK  ] Started Apply Kernel Variables.
         Starting Flush Journal to Persistent Storage...
[   11.595669] systemd-journald[85]: Received request to flush runtime journal from PID 1
[  OK  ] Started Create Static Device Nodes in /dev.
         Starting udev Kernel Device Manager...
[  OK  ] Reached target Local File Systems (Pre).
         Mounting /media/ram...
         Mounting /var/volatile...
[  OK  ] Mounted /var/volatile.
[  OK  ] Mounted /media/ram.
[  OK  ] Started Flush Journal to Persistent Storage.
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems.
         Starting Create Volatile Files and Directories...
[  OK  ] Started Load/Save Random Seed.
[  OK  ] Started udev Kernel Device Manager.
[  OK  ] Started Create Volatile Files and Directories.
         Starting Update UTMP about System Boot/Shutdown...
         Starting Network Time Synchronization...
[  OK  ] Started Update UTMP about System Boot/Shutdown.
[  OK  ] Started Network Time Synchronization.
[  OK  ] Reached target System Time Synchronized.
[   12.560835] omap-rproc 58820000.ipu: assigned reserved memory node ipu1-memory@9d000000
[  OK  ] Started udev Coldplug all Devices.
[   12.605843] remoteproc remoteproc0: 58820000.ipu is available
[  OK  ] Reached target System Initialization.
[   12.637577] omap-rproc 55020000.ipu: assigned reserved memory node ipu2-memory@95800000
[   12.654757] remoteproc remoteproc1: 55020000.ipu is available
[   12.671388] omap-rproc 40800000.dsp: assigned reserved memory node dsp1-memory@99000000
[   12.707444] remoteproc remoteproc2: 40800000.dsp is available
[   12.730586] omap-rproc 41000000.dsp: assigned reserved memory node dsp2-memory@9f000000
[   12.741730] remoteproc remoteproc3: 41000000.dsp is available
[  OK  ] Listening on dropbear.socket.
[  OK  ] Listening on D-Bus System Message Bus Socket.
         Starting Network Service...
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Started Daily rotation of log files.
[  OK  ] Reached target Timers.
[  OK  ] Listening on RPCbind Server Activation Socket.
[  OK  ] Reached target Sockets.
[  OK  ] Reached target Basic System.
         Starting TI MultiCore Tools Daemon...
         Starting System Logging Service...
[  OK  ] Started strongSwan IPsec IKEv1/IKEv2 daemon using ipsec.conf.
[   14.402230] remoteproc remoteproc1: powering up 55020000.ipu
[   14.408362] remoteproc remoteproc1: Booting fw image dra7-ipu2-fw.xem4, size 4828304
         [   14.431040] omap-iommu 55082000.mmu: 55082000.mmu: version 2.1
Starting TI IPC Daemon...
         Starting uim-sysfs.service...
         Starting Print notice about GPLv3 packages...
[  OK  ] Started D-Bus System Message Bus.
[   14.575401] virtio_rpmsg_bus virtio0: rpmsg host is online
[   14.579295] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x32
[   14.579438] virtio_rpmsg_bus virtio0: creating channel rpmsg-client-sample addr 0x33
[   14.579567] virtio_rpmsg_bus virtio0: creating channel rpmsg-omx addr 0x3c
[   14.579672] virtio_rpmsg_bus virtio0: creating channel rpmsg-rpc addr 0x65
[   14.619395] remoteproc remoteproc1: registered virtio0 (type 7)
[   14.628019] remoteproc remoteproc1: remote processor 55020000.ipu is now up
[   15.015884] remoteproc remoteproc0: powering up 58820000.ipu
[   15.021989] remoteproc remoteproc0: Booting fw image dra7-ipu1-fw.xem4, size 6732532
[   15.039061] omap-iommu 58882000.mmu: 58882000.mmu: version 2.1
[   15.057202] of_get_named_gpiod_flags: can't parse 'gpio-reset' property of node '/ocp/i2c@48070000/tlv320aic3104@18[0]'
[   15.093472] virtio_rpmsg_bus virtio1: rpmsg host is online
[   15.111784] remoteproc remoteproc0: registered virtio1 (type 7)
[   15.124567] remoteproc remoteproc0: remote processor 58820000.ipu is now up
[   15.220433] virtio_rpmsg_bus virtio1: creating channel rpmsg-proto addr 0x3d
[   15.236743] pixcir_ts 4-005c: GPIO lookup for consumer attb
[   15.236749] pixcir_ts 4-005c: using device tree for GPIO lookup
[   15.236825] of_get_named_gpiod_flags: can't parse 'attb-gpios' property of node '/ocp/i2c@4807c000/pixcir_ts@5c[0]'
[   15.237035] of_get_named_gpiod_flags: parsed 'attb-gpio' property of node '/ocp/i2c@4807c000/pixcir_ts@5c[0]' - status (0)
[   15.237051] pixcir_ts 4-005c: GPIO lookup for consumer reset
[   15.237057] pixcir_ts 4-005c: using device tree for GPIO lookup
[   15.237065] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/i2c@4807c000/pixcir_ts@5c[0]'
[   15.237091] of_get_named_gpiod_flags: parsed 'reset-gpio' property of node '/ocp/i2c@4807c000/pixcir_ts@5c[0]' - status (0)
[   15.237202] pixcir_ts 4-005c: GPIO lookup for consumer wake
[   15.237208] pixcir_ts 4-005c: using device tree for GPIO lookup
[   15.237285] of_get_named_gpiod_flags: can't parse 'wake-gpios' property of node '/ocp/i2c@4807c000/pixcir_ts@5c[0]'
[   15.237292] of_get_named_gpiod_flags: can't parse 'wake-gpio' property of node '/ocp/i2c@4807c000/pixcir_ts@5c[0]'
[   15.237297] pixcir_ts 4-005c: using lookup tables for GPIO lookup
[   15.237304] pixcir_ts 4-005c: lookup for GPIO wake failed
[   15.240651] pixcir_ts 4-005c: GPIO lookup for consumer enable
[   15.240734] pixcir_ts 4-005c: using device tree for GPIO lookup
[   15.240744] of_get_named_gpiod_flags: can't parse 'enable-gpios' property of node '/ocp/i2c@4807c000/pixcir_ts@5c[0]'
[   15.240751] of_get_named_gpiod_flags: can't parse 'enable-gpio' property of node '/ocp/i2c@4807c000/pixcir_ts@5c[0]'
[   15.240757] pixcir_ts 4-005c: using lookup tables for GPIO lookup
[   15.240763] pixcir_ts 4-005c: lookup for GPIO enable failed
[   15.406350] pixcir_ts 4-005c: pixcir_set_power_mode: can't read reg 0x33 : -121
[   15.406356] pixcir_ts 4-005c: Failed to set IDLE mode
[   15.417119] pixcir_ts: probe of 4-005c failed with error -121
[   15.850247] omap-des 480a5000.des: OMAP DES hw accel rev: 2.2
[   15.857996] omap-des 480a5000.des: will run requests pump with realtime priority
[   15.929156] omap_i2c 48060000.i2c: controller timed out
[   15.965021] rtc-ds1307 2-006f: read error -110
[   16.031512] rtc-ds1307: probe of 2-006f failed with error -110
[   16.273789] omap_rtc 48838000.rtc: char device (253:2)
[   16.286380] omap_rtc 48838000.rtc: registered as rtc2
[   16.787955] vpe 489d0000.vpe: loading firmware vpdma-1b8.bin
[   16.869415] vpe 489d0000.vpe: Device registered as /dev/video0
[   16.927266] SCSI subsystem initialized
[   17.097760] libata version 3.00 loaded.
[   17.399195] ahci 4a140000.sata: SSS flag set, parallel bus scan disabled
[   17.407879] ahci 4a140000.sata: AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl platform mode
[   17.439167] ahci 4a140000.sata: flags: 64bit ncq sntf stag pm led clo only pmp pio slum part ccc apst
[   17.490444] scsi host0: ahci
[   17.495305] ata1: SATA max UDMA/133 mmio [mem 0x4a140000-0x4a1410ff] port 0x100 irq 80
[   17.738473] omap-sham 4b101000.sham: hw accel on OMAP rev 4.3
[   17.817947] omap-aes 4b500000.aes: OMAP AES hw accel rev: 3.3
[   17.831763] omap-aes 4b500000.aes: will run requests pump with realtime priority
[   17.839326] ata1: SATA link down (SStatus 0 SControl 300)
[   17.908329] omap-aes 4b700000.aes: OMAP AES hw accel rev: 3.3
[   17.918682] omap-aes 4b700000.aes: will run requests pump with realtime priority
[   17.951477] omap_wdt: OMAP Watchdog Timer Rev 0x01: initial timeout 60 sec
[  OK  ] Started Hardware RNG Entropy Gatherer Daemon.
[  OK  ] Reached target Containers.
         Starting Login Service...
[  OK  ] Started Periodic Command Scheduler.
[  OK  ] Started Job spooling tools.
         Starting RPC Bind Service...
[  OK  ] Started System Logging Service.
[  OK  ] Started TI MultiCore Tools Daemon.
[  OK  ] Started TI IPC Daemon.
[   18.481573] remoteproc remoteproc2: powering up 40800000.dsp
[   18.488783] remoteproc remoteproc2: Booting fw image dra7-dsp1-fw.xe66, size 20559272
[  OK  ] Found device /dev/ttyS2.
[   18.573977] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[   18.579895] omap-iommu 40d01000.mmu: 40d01000.mmu: version 3.0
[   18.585913] omap-iommu 40d02000.mmu: 40d02000.mmu: version 3.0
[   18.708261] remoteproc remoteproc3: powering up 41000000.dsp
[   18.717802] remoteproc remoteproc3: Booting fw image dra7-dsp2-fw.xe66, size 20559272
[   18.775007] omap_hwmod: mmu0_dsp2: _wait_target_disable failed
[   18.780909] omap-iommu 41501000.mmu: 41501000.mmu: version 3.0
[   18.786876] omap-iommu 41502000.mmu: 41502000.mmu: version 3.0
[  OK  ] Started RPC Bind Service.
[  OK  ] Started Network Service.
[   18.883122] virtio_rpmsg_bus virtio2: rpmsg host is online
[   18.883221] virtio_rpmsg_bus virtio2: creating channel rpmsg-proto addr 0x3d
[   18.945979] remoteproc remoteproc2: registered virtio2 (type 7)
[   18.973770] remoteproc remoteproc2: remote processor 40800000.dsp is now up
[   19.004860] NET: Registered protocol family 15
[   19.010201] omap-hdmi-audio omap-hdmi-audio.0.auto: snd-soc-dummy-dai <-> 58040000.encoder mapping ok
[   19.045282] omap-hdmi-audio omap-hdmi-audio.0.auto: ASoC: no DMI vendor name!
[   19.073088] virtio_rpmsg_bus virtio3: rpmsg host is online
[   19.073143] remoteproc remoteproc3: registered virtio3 (type 7)
[   19.073150] remoteproc remoteproc3: remote processor 41000000.dsp is now up
[   19.073179] virtio_rpmsg_bus virtio3: creating channel rpmsg-proto addr 0x3d
[   19.362776] EXT4-fs (mmcblk0p2): mounting ext3 file system using the ext4 subsystem
[   19.449813] FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
[   19.546356] EXT4-fs (mmcblk0p2): recovery complete
[   19.551358] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[   19.828376] Initializing XFRM netlink socket
[  OK  ] Created slice system-systemd\x2dbacklight.slice.
         Starting Load/Save Screen Backlight…ightness of backlight:backlight...
[  OK  ] Reached target Network.
         Starting Simple Network Management Protocol (SNMP) Daemon....
         Starting Enable and configure wl18xx bluetooth stack...
         Starting Permit User Sessions...
         Starting Network Name Resolution...
[  OK  ] Started Load/Save Screen Backlight Brightness of backlight:backlight.
[  OK  ] Started Permit User Sessions.
[  OK  ] Started Login Service.
[  OK  ] Started Network Name Resolution.
[  OK  ] Started uim-sysfs.service.
[  OK  ] Started Simple Network Management Protocol (SNMP) Daemon..
[   21.528394] pruss 4b200000.pruss: creating PRU cores and other child platform devices
[   21.545039] pruss 4b280000.pruss: creating PRU cores and other child platform devices
[   21.617355] NET: Registered protocol family 44
[   21.632849] rpmsg_rpc virtio0.rpmsg-rpc.-1.101: probing service rpc_example_1 with src 1024 dst 101
[   21.670428] rpmsg_rpc virtio0.rpmsg-rpc.-1.101: published functions = 8
[   21.758160] remoteproc remoteproc4: 4b234000.pru is available
[   21.772778] usbcore: registered new interface driver usbfs
[   21.774636] usbcore: registered new interface driver hub
[   21.775186] usbcore: registered new device driver usb
[   21.795796] pru-rproc 4b234000.pru: PRU rproc node /ocp/pruss_soc_bus@4b226004/pruss@0/pru@34000 probed successfully
[   21.814654] remoteproc remoteproc5: 4b238000.pru is available
[   21.821962] pru-rproc 4b238000.pru: PRU rproc node /ocp/pruss_soc_bus@4b226004/pruss@0/pru@38000 probed successfully
[   21.848469] remoteproc remoteproc6: 4b2b4000.pru is available
[   21.855204] pru-rproc 4b2b4000.pru: PRU rproc node /ocp/pruss_soc_bus@4b2a6004/pruss@0/pru@34000 probed successfully
[   21.867637] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[   21.867665] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 1
[   21.873784] xhci-hcd xhci-hcd.1.auto: hcc params 0x0220f04c hci version 0x100 quirks 0x02010010
[   21.873843] xhci-hcd xhci-hcd.1.auto: irq 198, io mem 0x48890000
[   21.880092] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[   21.880100] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   21.880106] usb usb1: Product: xHCI Host Controller
[   21.880111] usb usb1: Manufacturer: Linux 4.14.79-gbde58ab01e xhci-hcd
[   21.880116] usb usb1: SerialNumber: xhci-hcd.1.auto
[   21.885845] hub 1-0:1.0: USB hub found
[   21.886893] hub 1-0:1.0: 1 port detected
[   21.893858] xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
[   21.893876] xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 2
[   21.893890] xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0  SuperSpeed
[   21.894519] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   21.894696] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
[   21.894703] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   21.894709] usb usb2: Product: xHCI Host Controller
[   21.894714] usb usb2: Manufacturer: Linux 4.14.79-gbde58ab01e xhci-hcd
[   21.894719] usb usb2: SerialNumber: xhci-hcd.1.auto
[   21.895648] hub 2-0:1.0: USB hub found
[   21.895682] hub 2-0:1.0: 1 port detected
[   21.896232] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller
[   21.896257] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 3
[   21.909392] xhci-hcd xhci-hcd.2.auto: hcc params 0x0220f04c hci version 0x100 quirks 0x02010010
[   21.909450] xhci-hcd xhci-hcd.2.auto: irq 199, io mem 0x488d0000
[   21.909693] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002
[   21.909701] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   21.909707] usb usb3: Product: xHCI Host Controller
[   21.909712] usb usb3: Manufacturer: Linux 4.14.79-gbde58ab01e xhci-hcd
[   21.909718] usb usb3: SerialNumber: xhci-hcd.2.auto
[   21.910262] hub 3-0:1.0: USB hub found
[   21.910307] hub 3-0:1.0: 1 port detected
[   21.910699] xhci-hcd xhci-hcd.2.auto: xHCI Host Controller
[   21.910716] xhci-hcd xhci-hcd.2.auto: new USB bus registered, assigned bus number 4
[   21.910728] xhci-hcd xhci-hcd.2.auto: Host supports USB 3.0  SuperSpeed
[   21.911570] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM.
[   21.911743] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003
[   21.911749] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[   21.911754] usb usb4: Product: xHCI Host Controller
[   21.911760] usb usb4: Manufacturer: Linux 4.14.79-gbde58ab01e xhci-hcd
[   21.911765] usb usb4: SerialNumber: xhci-hcd.2.auto
[   21.912283] hub 4-0:1.0: USB hub found
[   21.912325] hub 4-0:1.0: 1 port detected
[  OK  ] Started Enable and configure wl18xx bluetooth[   22.196889] remoteproc remoteproc7: 4b2b8000.pru is available
 stack.
[   22.209701] pru-rproc 4b2b8000.pru: PRU rproc node /ocp/pruss_soc_bus@4b2a6004/pruss@0/pru@38000 probed successfully
[   22.278974] usb 3-1: new high-speed USB device number 2 using xhci-hcd
[   22.469116] usb 3-1: New USB device found, idVendor=0424, idProduct=2514
[   22.476302] usb 3-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[   22.487660] hub 3-1:1.0: USB hub found
[   22.492900] hub 3-1:1.0: 4 ports detected
[   22.848956] usb 3-1.3: new high-speed USB device number 3 using xhci-hcd
[   22.999116] usb 3-1.3: New USB device found, idVendor=0424, idProduct=2514
[   23.006277] usb 3-1.3: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[   23.031090] hub 3-1.3:1.0: USB hub found
[   23.035311] hub 3-1.3:1.0: 4 ports detected
[   23.418942] usb 3-1.3.4: new high-speed USB device number 4 using xhci-hcd
[   23.559228] usb 3-1.3.4: New USB device found, idVendor=0424, idProduct=2514
[   23.566316] usb 3-1.3.4: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[   23.606984] hub 3-1.3.4:1.0: USB hub found
[   23.611721] hub 3-1.3.4:1.0: 4 ports detected
[   23.958956] usb 3-1.3.4.2: new full-speed USB device number 5 using xhci-hcd
[   24.090637] usb 3-1.3.4.2: New USB device found, idVendor=0483, idProduct=572a
[   24.098350] usb 3-1.3.4.2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[   24.107194] usb 3-1.3.4.2: Product: Composite MSC + CDC
[   24.113207] usb 3-1.3.4.2: Manufacturer: STMicroelectronics
[   24.119219] usb 3-1.3.4.2: SerialNumber: 1111101010
[   24.249814] usb 3-1.3.4.4: new high-speed USB device number 6 using xhci-hcd
[   24.293264] cdc_acm 3-1.3.4.2:1.0: ttyACM0: USB ACM device
[   24.302528] usbcore: registered new interface driver cdc_acm
[   24.308557] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters
[   24.379120] usb 3-1.3.4.4: New USB device found, idVendor=0424, idProduct=2514
[   24.386835] usb 3-1.3.4.4: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[   24.407414] hub 3-1.3.4.4:1.0: USB hub found
[   24.412277] hub 3-1.3.4.4:1.0: 4 ports detected
[   24.759003] usb 3-1.3.4.4.1: new full-speed USB device number 7 using xhci-hcd
[   24.890804] usb 3-1.3.4.4.1: New USB device found, idVendor=0483, idProduct=572a
[   24.898252] usb 3-1.3.4.4.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[   24.906353] usb 3-1.3.4.4.1: Product: Composite Device MSC + CDC
[   24.912514] usb 3-1.3.4.4.1: Manufacturer: STMicroelectronics
[   24.918368] usb 3-1.3.4.4.1: SerialNumber: 1111
[   24.952720] cdc_acm 3-1.3.4.4.1:1.1: ttyACM1: USB ACM device
[   25.058971] usb 3-1.3.4.4.4: new high-speed USB device number 8 using xhci-hcd
[   25.145153] usb-storage 3-1.3.4.4.1:1.0: USB Mass Storage device detected
[   25.154728] scsi host1: usb-storage 3-1.3.4.4.1:1.0
[   25.163301] usbcore: registered new interface driver usb-storage
[   25.189204] usb 3-1.3.4.4.4: New USB device found, idVendor=0424, idProduct=2514
[   25.197113] usb 3-1.3.4.4.4: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[   25.239294] hub 3-1.3.4.4.4:1.0: USB hub found
[   25.244197] hub 3-1.3.4.4.4:1.0: 4 ports detected
[   26.169503] scsi 1:0:0:0: Direct-Access     STM      Product          0.01 PQ: 0 ANSI: 2
[   26.209827] sd 1:0:0:0: [sda] 1024 4096-byte logical blocks: (4.19 MB/4.00 MiB)
[   26.218068] sd 1:0:0:0: [sda] Write Protect is off
[   26.223694] sd 1:0:0:0: [sda] Mode Sense: 22 00 00 00
[   26.229823] sd 1:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[   26.252772]  sda: sda1
[   26.257563] sd 1:0:0:0: [sda] Attached SCSI removable disk
[   27.470473] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
***************************************************************
***************************************************************
NOTICE: This file system contains the following GPLv3 packages:
        autoconf
        bash-dev
        bash
        binutils-dev
        binutils
        bison-dev
        bison
        cifs-utils
        cpio
        cpp-symlinks
        cpp
        dosfstools
        elfutils-dev
        elfutils
        g++-symlinks
        g++
        gawk
        gcc-symlinks
        gcc
        gdb
        gdbc6x
        gdbserver
        gettext
        gzip
        hidapi
        libasm1
        libdw1
        libelf1
        libgdbm-compat4
        libgdbm-dev
        libgdbm4
        libgettextlib
        libgettextsrc
        libgmp10
        libidn11
        libmpc3
        libmpfr4
        libreadline-dev
        libreadline7
        libunistring2
        m4-dev
        m4
        make
        mc
        nano
        nettle
        parted
        python3-pycairo
        rsyslog
        which

If you do not wish to distribute GPLv3 components please remove
the above packages prior to distribution.  This can be done using
the opkg remove command.  i.e.:
    opkg remove <package>
Where <package> is the name printed in the list above

NOTE: If the package is a dependency of another package you
      will be notified of the dependent packages.  You should
      use the --force-removal-of-dependent-packages option to
      also remove the dependent packages as well
***************************************************************
***************************************************************
[  OK  ] Started Print notice about GPLv3 packages.
[  OK  ] Reached target Sound Card.
         Starting rc.pvr.service...
[  OK  ] Listening on Load/Save RF Kill Switch Status /dev/rfkill Watch.
[  OK  ] Reached target Host and Network Name Lookups.
[  OK  ] Started NFS status monitor for NFSv2/3 locking..
[  OK  ] Started Serial Getty on ttyS2.
[  OK  ] Started Getty on tty1.
[  OK  ] Reached target Login Prompts.
         Starting Synchronize System and HW clocks...
[FAILED] Failed to start Synchronize System and HW clocks.
See 'systemctl status sync-clocks.service' for details.
[   29.296319] omap_hwmod: mmu0_dsp1: _wait_target_disable failed
[   29.309377] omap_hwmod: mmu0_dsp2: _wait_target_disable failed
[  OK  ] Started rc.pvr.service.
         Starting telnetd.service...
[  OK  ] Started telnetd.service.
         Starting thttpd.service...
[  OK  ] Started thttpd.service.
         Starting rng-tools.service...
[  OK  ] Started rng-tools.service.
         Starting gdbserverproxy.service...

 _____                    _____           _         _
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_|
              |___|                    |___|

Arago Project http://arago-project.org am57xx-evm ttyS2

Arago 2018.10 am57xx-evm ttyS2

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    我忘记附加 DTS 文件。

    /dts-v1/;
    
    / {
    	#address-cells = <0x2>;
    	#size-cells = <0x2>;
    	compatible = "ti,am5728-evm", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
    	interrupt-parent = <0x1>;
    	model = "TI AM5728 EVM";
    
    	fixedregulator-mmcwl {
    		phandle = <0x247>;
    		enable-active-high;
    		gpio = <0x19e 0x8 0x0>;
    		regulator-max-microvolt = <0x1b7740>;
    		regulator-min-microvolt = <0x1b7740>;
    		regulator-name = "vmmcwl_fixed";
    		compatible = "regulator-fixed";
    	};
    
    	fixedregulator-com_3v6 {
    		phandle = <0x246>;
    		regulator-boot-on;
    		regulator-always-on;
    		vin-supply = <0x23f>;
    		regulator-max-microvolt = <0x36ee80>;
    		regulator-min-microvolt = <0x36ee80>;
    		regulator-name = "com_3v6";
    		compatible = "regulator-fixed";
    	};
    
    	backlight {
    		phandle = <0x248>;
    		pwms = <0x213 0x0 0xc350 0x0>;
    		default-brightness-level = <0x8>;
    		brightness-levels = <0x0 0xf3 0xf5 0xf7 0xf9 0xfb 0xfc 0xfd 0xff>;
    		compatible = "pwm-backlight";
    	};
    
    	gpio_keys {
    		autorepeat;
    		#size-cells = <0x0>;
    		#address-cells = <0x1>;
    		compatible = "gpio-keys";
    
    		USER5 {
    			linux,code = <0x66>;
    			label = "Home";
    			gpios = <0xaf 0x14 0x1>;
    		};
    
    		USER4 {
    			linux,code = <0x6a>;
    			label = "Right";
    			gpios = <0xaf 0x18 0x1>;
    		};
    
    		USER3 {
    			linux,code = <0x69>;
    			label = "Left";
    			gpios = <0xaf 0x1c 0x1>;
    		};
    
    		USER2 {
    			linux,code = <0x6c>;
    			label = "Down";
    			gpios = <0xaf 0x19 0x1>;
    		};
    
    		USER1 {
    			linux,code = <0x67>;
    			label = "Up";
    			gpios = <0xaf 0x17 0x1>;
    		};
    	};
    
    	chosen {
    		stdout-path = "/ocp/serial@48020000";
    	};
    
    	aliases {
    		i2c0 = "/ocp/i2c@48070000";
    		i2c1 = "/ocp/i2c@48072000";
    		i2c2 = "/ocp/i2c@48060000";
    		i2c3 = "/ocp/i2c@4807a000";
    		i2c4 = "/ocp/i2c@4807c000";
    		serial0 = "/ocp/serial@4806a000";
    		serial1 = "/ocp/serial@4806c000";
    		serial2 = "/ocp/serial@48020000";
    		serial3 = "/ocp/serial@4806e000";
    		serial4 = "/ocp/serial@48066000";
    		serial5 = "/ocp/serial@48068000";
    		serial6 = "/ocp/serial@48420000";
    		serial7 = "/ocp/serial@48422000";
    		serial8 = "/ocp/serial@48424000";
    		serial9 = "/ocp/serial@4ae2b000";
    		ethernet0 = "/ocp/ethernet@48484000/slave@48480200";
    		ethernet1 = "/ocp/ethernet@48484000/slave@48480300";
    		d_can0 = "/ocp/can@4ae3c000";
    		d_can1 = "/ocp/can@48480000";
    		spi0 = "/ocp/qspi@4b300000";
    		rproc0 = "/ocp/ipu@58820000";
    		rproc1 = "/ocp/ipu@55020000";
    		rproc2 = "/ocp/dsp@40800000";
    		rproc3 = "/ocp/dsp@41000000";
    		rtc0 = "/ocp/i2c@48060000/rtc@6f";
    		rtc1 = "/ocp/i2c@48070000/tps659038@58/tps659038_rtc";
    		rtc2 = "/ocp/rtc@48838000";
    		display0 = "/connector";
    		sound1 = "/ocp/dss@58000000/encoder@58060000";
    	};
    
    	timer {
    		compatible = "arm,armv7-timer";
    		interrupts = <0x1 0xd 0x308 0x1 0xe 0x308 0x1 0xb 0x308 0x1 0xa 0x308>;
    		interrupt-parent = <0x2>;
    	};
    
    	interrupt-controller@48211000 {
    		compatible = "arm,cortex-a15-gic";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x0 0x48211000 0x0 0x1000 0x0 0x48212000 0x0 0x2000 0x0 0x48214000 0x0 0x2000 0x0 0x48216000 0x0 0x2000>;
    		interrupts = <0x1 0x9 0x304>;
    		interrupt-parent = <0x2>;
    		phandle = <0x2>;
    	};
    
    	interrupt-controller@48281000 {
    		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
    		interrupt-controller;
    		#interrupt-cells = <0x3>;
    		reg = <0x0 0x48281000 0x0 0x1000>;
    		interrupt-parent = <0x2>;
    		phandle = <0x8>;
    	};
    
    	cpus {
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    
    		cpu@0 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a15";
    			reg = <0x0>;
    			operating-points-v2 = <0x3>;
    			clocks = <0x4>;
    			clock-names = "cpu";
    			clock-latency = <0x493e0>;
    			cooling-min-level = <0x0>;
    			cooling-max-level = <0x2>;
    			#cooling-cells = <0x2>;
    			vbb-supply = <0x5>;
    			vdd-supply = <0x6>;
    			voltage-tolerance = <0x1>;
    			phandle = <0x11d>;
    		};
    
    		cpu@1 {
    			device_type = "cpu";
    			compatible = "arm,cortex-a15";
    			reg = <0x1>;
    			operating-points-v2 = <0x3>;
    		};
    	};
    
    	opp-table {
    		compatible = "operating-points-v2-ti-cpu";
    		syscon = <0x7>;
    		opp-shared;
    		phandle = <0x3>;
    
    		opp_nom-1000000000 {
    			opp-hz = <0x0 0x3b9aca00>;
    			opp-microvolt = <0x102ca0 0xcf850 0x118c30 0x102ca0 0xcf850 0x118c30>;
    			opp-supported-hw = <0xff 0x1>;
    			opp-suspend;
    		};
    
    		opp_od-1176000000 {
    			opp-hz = <0x0 0x46185600>;
    			opp-microvolt = <0x11b340 0xd8108 0x11b340 0x11b340 0xd8108 0x11b340>;
    			opp-supported-hw = <0xff 0x2>;
    		};
    
    		opp_high@1500000000 {
    			opp-hz = <0x0 0x59682f00>;
    			opp-microvolt = <0x127690 0xe7ef0 0x1312d0 0x127690 0xe7ef0 0x1312d0>;
    			opp-supported-hw = <0xff 0x4>;
    		};
    	};
    
    	soc {
    		compatible = "ti,omap-infra";
    
    		mpu {
    			compatible = "ti,omap5-mpu";
    			ti,hwmods = "mpu";
    		};
    	};
    
    	ocp {
    		compatible = "ti,dra7-l3-noc", "simple-bus";
    		#address-cells = <0x1>;
    		#size-cells = <0x1>;
    		ranges = <0x0 0x0 0x0 0xc0000000>;
    		ti,hwmods = "l3_main_1", "l3_main_2";
    		reg = <0x0 0x44000000 0x0 0x1000000 0x0 0x45000000 0x0 0x1000>;
    		interrupts-extended = <0x1 0x0 0x4 0x4 0x8 0x0 0xa 0x4>;
    
    		l4@4a000000 {
    			compatible = "ti,dra7-l4-cfg", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4a000000 0x22c000>;
    			phandle = <0x12e>;
    
    			scm@2000 {
    				compatible = "ti,dra7-scm-core", "simple-bus";
    				reg = <0x2000 0x2000>;
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges = <0x0 0x2000 0x2000>;
    				phandle = <0x12f>;
    
    				scm_conf@0 {
    					compatible = "syscon", "simple-bus";
    					reg = <0x0 0x1400>;
    					#address-cells = <0x1>;
    					#size-cells = <0x1>;
    					ranges = <0x0 0x0 0x1400>;
    					phandle = <0x9>;
    
    					pbias_regulator@e00 {
    						compatible = "ti,pbias-dra7", "ti,pbias-omap";
    						reg = <0xe00 0x4>;
    						syscon = <0x9>;
    						phandle = <0x130>;
    
    						pbias_mmc_omap5 {
    							regulator-name = "pbias_mmc_omap5";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x325aa0>;
    							phandle = <0xd1>;
    						};
    					};
    
    					clocks {
    						#address-cells = <0x1>;
    						#size-cells = <0x0>;
    						phandle = <0x131>;
    
    						dss_deshdcp_clk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xa>;
    							ti,bit-shift = <0x0>;
    							reg = <0x558>;
    							phandle = <0x132>;
    						};
    
    						ehrpwm0_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xb>;
    							ti,bit-shift = <0x14>;
    							reg = <0x558>;
    							phandle = <0x111>;
    						};
    
    						ehrpwm1_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xb>;
    							ti,bit-shift = <0x15>;
    							reg = <0x558>;
    							phandle = <0x112>;
    						};
    
    						ehrpwm2_tbclk@558 {
    							#clock-cells = <0x0>;
    							compatible = "ti,gate-clock";
    							clocks = <0xb>;
    							ti,bit-shift = <0x16>;
    							reg = <0x558>;
    							phandle = <0x113>;
    						};
    
    						sys_32k_ck {
    							#clock-cells = <0x0>;
    							compatible = "ti,mux-clock";
    							clocks = <0xc 0xd 0xd 0xd>;
    							ti,bit-shift = <0x8>;
    							reg = <0x6c4>;
    							phandle = <0x51>;
    						};
    					};
    				};
    
    				pinmux@1400 {
    					compatible = "ti,dra7-padconf", "pinctrl-single";
    					reg = <0x1400 0x468>;
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					#pinctrl-cells = <0x1>;
    					#interrupt-cells = <0x1>;
    					interrupt-controller;
    					pinctrl-single,register-width = <0x20>;
    					pinctrl-single,function-mask = <0x3fffffff>;
    					phandle = <0xb5>;
    
    					mmc1_pins_default {
    						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
    						phandle = <0xd2>;
    					};
    
    					mmc1_pins_default_no_clk_pu {
    						pinctrl-single,pins = <0x354 0x40000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
    						phandle = <0x133>;
    					};
    
    					mmc1_pins_sdr12 {
    						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
    						phandle = <0xd4>;
    					};
    
    					mmc1_pins_hs {
    						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
    						phandle = <0xd3>;
    					};
    
    					mmc1_pins_sdr25 {
    						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
    						phandle = <0xd5>;
    					};
    
    					mmc1_pins_sdr50 {
    						pinctrl-single,pins = <0x354 0x601a0 0x358 0x601a0 0x35c 0x601a0 0x360 0x601a0 0x364 0x601a0 0x368 0x601a0>;
    						phandle = <0xd6>;
    					};
    
    					mmc1_pins_ddr50 {
    						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
    						phandle = <0xd7>;
    					};
    
    					mmc1_pins_sdr104 {
    						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
    						phandle = <0xd9>;
    					};
    
    					mmc2_pins_default {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    						phandle = <0xdb>;
    					};
    
    					mmc2_pins_hs {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    						phandle = <0xdc>;
    					};
    
    					mmc2_pins_ddr_3_3v_rev11 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    						phandle = <0x134>;
    					};
    
    					mmc2_pins_ddr_1_8v_rev11 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    						phandle = <0x135>;
    					};
    
    					mmc2_pins_ddr_rev20 {
    						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
    						phandle = <0xdd>;
    					};
    
    					mmc2_pins_hs200 {
    						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
    						phandle = <0x136>;
    					};
    
    					mmc4_pins_default {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    						phandle = <0x137>;
    					};
    
    					mmc4_pins_hs {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    						phandle = <0x138>;
    					};
    
    					mmc3_pins_default {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    						phandle = <0x139>;
    					};
    
    					mmc3_pins_hs {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    						phandle = <0x13a>;
    					};
    
    					mmc3_pins_sdr12 {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    						phandle = <0x13b>;
    					};
    
    					mmc3_pins_sdr25 {
    						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
    						phandle = <0x13c>;
    					};
    
    					mmc3_pins_sdr50 {
    						pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
    						phandle = <0x13d>;
    					};
    
    					mmc4_pins_sdr12 {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    						phandle = <0x13e>;
    					};
    
    					mmc4_pins_sdr25 {
    						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
    						phandle = <0x13f>;
    					};
    				};
    
    				scm_conf@1c04 {
    					compatible = "syscon";
    					reg = <0x1c04 0x20>;
    					#syscon-cells = <0x2>;
    					phandle = <0xae>;
    				};
    
    				scm_conf@1c24 {
    					compatible = "syscon";
    					reg = <0x1c24 0x24>;
    					phandle = <0xac>;
    				};
    
    				dma-router@b78 {
    					compatible = "ti,dra7-dma-crossbar";
    					reg = <0xb78 0xfc>;
    					#dma-cells = <0x1>;
    					dma-requests = <0xcd>;
    					ti,dma-safe-map = <0x0>;
    					dma-masters = <0xe>;
    					phandle = <0xb4>;
    				};
    
    				dma-router@c78 {
    					compatible = "ti,dra7-dma-crossbar";
    					reg = <0xc78 0x7c>;
    					#dma-cells = <0x2>;
    					dma-requests = <0xcc>;
    					ti,dma-safe-map = <0x0>;
    					dma-masters = <0xf>;
    					phandle = <0xf3>;
    				};
    			};
    
    			cm_core_aon@5000 {
    				compatible = "ti,dra7-cm-core-aon";
    				reg = <0x5000 0x2000>;
    				phandle = <0x140>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					phandle = <0x141>;
    
    					atl_clkin0_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10>;
    						phandle = <0x44>;
    					};
    
    					atl_clkin1_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10>;
    						phandle = <0x43>;
    					};
    
    					atl_clkin2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10>;
    						phandle = <0x42>;
    					};
    
    					atl_clkin3_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-atl-clock";
    						clocks = <0x10>;
    						phandle = <0x41>;
    					};
    
    					hdmi_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x30>;
    					};
    
    					mlb_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0xa8>;
    					};
    
    					mlbp_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0xa9>;
    					};
    
    					pciesref_acs_clk_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x5f5e100>;
    						phandle = <0x5b>;
    					};
    
    					ref_clkin0_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x46>;
    					};
    
    					ref_clkin1_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x47>;
    					};
    
    					ref_clkin2_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x48>;
    					};
    
    					ref_clkin3_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x49>;
    					};
    
    					rmii_clk_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x72>;
    					};
    
    					sdvenc_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x142>;
    					};
    
    					secure_32k_clk_src_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0x92>;
    					};
    
    					sys_clk32_crystal_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x8000>;
    						phandle = <0xc>;
    					};
    
    					sys_clk32_pseudo_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x11>;
    						clock-mult = <0x1>;
    						clock-div = <0x262>;
    						phandle = <0xd>;
    					};
    
    					virt_12000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0xb71b00>;
    						phandle = <0x82>;
    					};
    
    					virt_13000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0xc65d40>;
    						phandle = <0x143>;
    					};
    
    					virt_16800000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1005900>;
    						phandle = <0x84>;
    					};
    
    					virt_19200000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x124f800>;
    						phandle = <0x85>;
    					};
    
    					virt_20000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1312d00>;
    						phandle = <0x83>;
    					};
    
    					virt_26000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x18cba80>;
    						phandle = <0x86>;
    					};
    
    					virt_27000000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x19bfcc0>;
    						phandle = <0x87>;
    					};
    
    					virt_38400000_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x249f000>;
    						phandle = <0x88>;
    					};
    
    					sys_clkin2 {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x1588800>;
    						phandle = <0x45>;
    					};
    
    					usb_otg_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x8f>;
    					};
    
    					video1_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x3a>;
    					};
    
    					video1_m2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x2f>;
    					};
    
    					video2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x3b>;
    					};
    
    					video2_m2_clkin_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x2e>;
    					};
    
    					dpll_abe_ck@1e0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-m4xen-clock";
    						clocks = <0x12 0x13>;
    						reg = <0x1e0 0x1e4 0x1ec 0x1e8>;
    						assigned-clocks = <0x14>;
    						assigned-clock-rates = <0x2faf080>;
    						phandle = <0x14>;
    					};
    
    					dpll_abe_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x14>;
    						phandle = <0x15>;
    					};
    
    					dpll_abe_m2x2_ck@1f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x15>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x16>;
    					};
    
    					abe_clk@108 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x16>;
    						ti,max-div = <0x4>;
    						reg = <0x108>;
    						ti,index-power-of-two;
    						phandle = <0x8a>;
    					};
    
    					dpll_abe_m2_ck@1f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x14>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x70>;
    					};
    
    					dpll_abe_m3x2_ck@1f4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x15>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1f4>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x17>;
    					};
    
    					dpll_core_byp_mux@12c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x12c>;
    						phandle = <0x18>;
    					};
    
    					dpll_core_ck@120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-core-clock";
    						clocks = <0x11 0x18>;
    						reg = <0x120 0x124 0x12c 0x128>;
    						phandle = <0x19>;
    					};
    
    					dpll_core_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x19>;
    						phandle = <0x1a>;
    					};
    
    					dpll_core_h12x2_ck@13c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x13c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x1b>;
    					};
    
    					mpu_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x1c>;
    					};
    
    					dpll_mpu_ck@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap5-mpu-dpll-clock";
    						clocks = <0x11 0x1c>;
    						reg = <0x160 0x164 0x16c 0x168>;
    						phandle = <0x4>;
    					};
    
    					dpll_mpu_m2_ck@170 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x4>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x170>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x1d>;
    					};
    
    					mpu_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1d>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x96>;
    					};
    
    					dsp_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x1e>;
    					};
    
    					dpll_dsp_byp_mux@240 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x1e>;
    						ti,bit-shift = <0x17>;
    						reg = <0x240>;
    						phandle = <0x1f>;
    					};
    
    					dpll_dsp_ck@234 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x1f>;
    						reg = <0x234 0x238 0x240 0x23c>;
    						assigned-clocks = <0x20>;
    						assigned-clock-rates = <0x23c34600>;
    						phandle = <0x20>;
    					};
    
    					dpll_dsp_m2_ck@244 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x20>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x244>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x21>;
    						assigned-clock-rates = <0x23c34600>;
    						phandle = <0x21>;
    					};
    
    					iva_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x22>;
    					};
    
    					dpll_iva_byp_mux@1ac {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x22>;
    						ti,bit-shift = <0x17>;
    						reg = <0x1ac>;
    						phandle = <0x23>;
    					};
    
    					dpll_iva_ck@1a0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x23>;
    						reg = <0x1a0 0x1a4 0x1ac 0x1a8>;
    						assigned-clocks = <0x24>;
    						assigned-clock-rates = <0x45707d40>;
    						phandle = <0x24>;
    					};
    
    					dpll_iva_m2_ck@1b0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x24>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x1b0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x25>;
    						assigned-clock-rates = <0x17257f16>;
    						phandle = <0x25>;
    					};
    
    					iva_dclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x25>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x98>;
    					};
    
    					dpll_gpu_byp_mux@2e4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x2e4>;
    						phandle = <0x26>;
    					};
    
    					dpll_gpu_ck@2d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x26>;
    						reg = <0x2d8 0x2dc 0x2e4 0x2e0>;
    						assigned-clocks = <0x27>;
    						assigned-clock-rates = <0x4c1d7940>;
    						phandle = <0x27>;
    					};
    
    					dpll_gpu_m2_ck@2e8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x27>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2e8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x28>;
    						assigned-clock-rates = <0x195f286b>;
    						phandle = <0x28>;
    					};
    
    					dpll_core_m2_ck@130 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x19>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x130>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x29>;
    					};
    
    					core_dpll_out_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x29>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x9a>;
    					};
    
    					dpll_ddr_byp_mux@21c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x21c>;
    						phandle = <0x2a>;
    					};
    
    					dpll_ddr_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x2a>;
    						reg = <0x210 0x214 0x21c 0x218>;
    						phandle = <0x2b>;
    					};
    
    					dpll_ddr_m2_ck@220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x2b>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x220>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x8c>;
    					};
    
    					dpll_gmac_byp_mux@2b4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x17>;
    						ti,bit-shift = <0x17>;
    						reg = <0x2b4>;
    						phandle = <0x2c>;
    					};
    
    					dpll_gmac_ck@2a8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x2c>;
    						reg = <0x2a8 0x2ac 0x2b4 0x2b0>;
    						phandle = <0x2d>;
    					};
    
    					dpll_gmac_m2_ck@2b8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x2d>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2b8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x8d>;
    					};
    
    					video2_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2e>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x9c>;
    					};
    
    					video1_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x2f>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x9d>;
    					};
    
    					hdmi_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x30>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x9e>;
    					};
    
    					per_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x17>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x5f>;
    					};
    
    					usb_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x17>;
    						clock-mult = <0x1>;
    						clock-div = <0x3>;
    						phandle = <0x63>;
    					};
    
    					eve_dpll_hs_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x1b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x31>;
    					};
    
    					dpll_eve_byp_mux@290 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x31>;
    						ti,bit-shift = <0x17>;
    						reg = <0x290>;
    						phandle = <0x32>;
    					};
    
    					dpll_eve_ck@284 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x32>;
    						reg = <0x284 0x288 0x290 0x28c>;
    						phandle = <0x33>;
    					};
    
    					dpll_eve_m2_ck@294 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x33>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x294>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x34>;
    					};
    
    					eve_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x34>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0xa7>;
    					};
    
    					dpll_core_h13x2_ck@140 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x140>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x144>;
    					};
    
    					dpll_core_h14x2_ck@144 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x144>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x73>;
    					};
    
    					dpll_core_h22x2_ck@154 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x154>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x3c>;
    					};
    
    					dpll_core_h23x2_ck@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x158>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x81>;
    					};
    
    					dpll_core_h24x2_ck@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x1a>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x15c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x10a>;
    					};
    
    					dpll_ddr_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x2b>;
    						phandle = <0x35>;
    					};
    
    					dpll_ddr_h11x2_ck@228 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x35>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x228>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x145>;
    					};
    
    					dpll_dsp_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x20>;
    						phandle = <0x36>;
    					};
    
    					dpll_dsp_m3x2_ck@248 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x36>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x248>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						assigned-clocks = <0x37>;
    						assigned-clock-rates = <0x17d78400>;
    						phandle = <0x37>;
    					};
    
    					dpll_gmac_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x2d>;
    						phandle = <0x38>;
    					};
    
    					dpll_gmac_h11x2_ck@2c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c0>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x39>;
    					};
    
    					dpll_gmac_h12x2_ck@2c4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c4>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x146>;
    					};
    
    					dpll_gmac_h13x2_ck@2c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2c8>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0xe0>;
    					};
    
    					dpll_gmac_m3x2_ck@2bc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x38>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x2bc>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x147>;
    					};
    
    					gmii_m_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x39>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x148>;
    					};
    
    					hdmi_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x30>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x4f>;
    					};
    
    					hdmi_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x30>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x55>;
    					};
    
    					l3_iclk_div@100 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						ti,max-div = <0x2>;
    						ti,bit-shift = <0x4>;
    						reg = <0x100>;
    						clocks = <0x1b>;
    						ti,index-power-of-two;
    						phandle = <0xa>;
    					};
    
    					l4_root_clk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0xa>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0xb>;
    					};
    
    					video1_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x4d>;
    					};
    
    					video1_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3a>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x53>;
    					};
    
    					video2_clk2_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x4e>;
    					};
    
    					video2_div_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x3b>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x54>;
    					};
    
    					ipu1_gfclk_mux@520 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x16 0x3c>;
    						ti,bit-shift = <0x18>;
    						reg = <0x520>;
    						assigned-clocks = <0x3d>;
    						assigned-clock-parents = <0x3c>;
    						phandle = <0x3d>;
    					};
    
    					mcasp1_ahclkr_mux@550 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x1c>;
    						reg = <0x550>;
    						phandle = <0xf6>;
    					};
    
    					mcasp1_ahclkx_mux@550 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x18>;
    						reg = <0x550>;
    						phandle = <0xf5>;
    					};
    
    					mcasp1_aux_gfclk_mux@550 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4c 0x4d 0x4e 0x4f>;
    						ti,bit-shift = <0x16>;
    						reg = <0x550>;
    						phandle = <0xf4>;
    					};
    
    					timer5_gfclk_mux@558 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x558>;
    						phandle = <0x149>;
    					};
    
    					timer6_gfclk_mux@560 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x560>;
    						phandle = <0x14a>;
    					};
    
    					timer7_gfclk_mux@568 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x568>;
    						phandle = <0x14b>;
    					};
    
    					timer8_gfclk_mux@570 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
    						ti,bit-shift = <0x18>;
    						reg = <0x570>;
    						phandle = <0x14c>;
    					};
    
    					uart6_gfclk_mux@580 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x580>;
    						phandle = <0x14d>;
    					};
    
    					dummy_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-clock";
    						clock-frequency = <0x0>;
    						phandle = <0x14e>;
    					};
    				};
    
    				clockdomains {
    					phandle = <0x14f>;
    				};
    			};
    
    			cm_core@8000 {
    				compatible = "ti,dra7-cm-core";
    				reg = <0x8000 0x3000>;
    				phandle = <0x150>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					phandle = <0x151>;
    
    					dpll_pcie_ref_ck@200 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x11>;
    						reg = <0x200 0x204 0x20c 0x208>;
    						phandle = <0x59>;
    					};
    
    					dpll_pcie_ref_m2ldo_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x59>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x210>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x5a>;
    					};
    
    					apll_pcie_in_clk_mux@4ae06118 {
    						compatible = "ti,mux-clock";
    						clocks = <0x5a 0x5b>;
    						#clock-cells = <0x0>;
    						reg = <0x21c 0x4>;
    						ti,bit-shift = <0x7>;
    						phandle = <0x5c>;
    					};
    
    					apll_pcie_ck@21c {
    						#clock-cells = <0x0>;
    						compatible = "ti,dra7-apll-clock";
    						clocks = <0x5c 0x59>;
    						reg = <0x21c 0x220>;
    						phandle = <0x5d>;
    					};
    
    					optfclk_pciephy1_32khz@4a0093b0 {
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						#clock-cells = <0x0>;
    						reg = <0x13b0>;
    						ti,bit-shift = <0x8>;
    						phandle = <0xe4>;
    					};
    
    					optfclk_pciephy2_32khz@4a0093b8 {
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						#clock-cells = <0x0>;
    						reg = <0x13b8>;
    						ti,bit-shift = <0x8>;
    						phandle = <0xe7>;
    					};
    
    					optfclk_pciephy_div@4a00821c {
    						compatible = "ti,divider-clock";
    						clocks = <0x5d>;
    						#clock-cells = <0x0>;
    						reg = <0x21c>;
    						ti,dividers = <0x2 0x1>;
    						ti,bit-shift = <0x8>;
    						ti,max-div = <0x2>;
    						phandle = <0x5e>;
    					};
    
    					optfclk_pciephy1_clk@4a0093b0 {
    						compatible = "ti,gate-clock";
    						clocks = <0x5d>;
    						#clock-cells = <0x0>;
    						reg = <0x13b0>;
    						ti,bit-shift = <0x9>;
    						phandle = <0xe5>;
    					};
    
    					optfclk_pciephy2_clk@4a0093b8 {
    						compatible = "ti,gate-clock";
    						clocks = <0x5d>;
    						#clock-cells = <0x0>;
    						reg = <0x13b8>;
    						ti,bit-shift = <0x9>;
    						phandle = <0xe8>;
    					};
    
    					optfclk_pciephy1_div_clk@4a0093b0 {
    						compatible = "ti,gate-clock";
    						clocks = <0x5e>;
    						#clock-cells = <0x0>;
    						reg = <0x13b0>;
    						ti,bit-shift = <0xa>;
    						phandle = <0xe6>;
    					};
    
    					optfclk_pciephy2_div_clk@4a0093b8 {
    						compatible = "ti,gate-clock";
    						clocks = <0x5e>;
    						#clock-cells = <0x0>;
    						reg = <0x13b8>;
    						ti,bit-shift = <0xa>;
    						phandle = <0xe9>;
    					};
    
    					apll_pcie_clkvcoldo {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x5d>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x152>;
    					};
    
    					apll_pcie_clkvcoldo_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x5d>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x153>;
    					};
    
    					apll_pcie_m2_ck {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x5d>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x91>;
    					};
    
    					dpll_per_byp_mux@14c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x5f>;
    						ti,bit-shift = <0x17>;
    						reg = <0x14c>;
    						phandle = <0x60>;
    					};
    
    					dpll_per_ck@140 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-clock";
    						clocks = <0x11 0x60>;
    						reg = <0x140 0x144 0x14c 0x148>;
    						phandle = <0x61>;
    					};
    
    					dpll_per_m2_ck@150 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x61>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x150>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x62>;
    					};
    
    					func_96m_aon_dclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x62>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x9f>;
    					};
    
    					dpll_usb_byp_mux@18c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x63>;
    						ti,bit-shift = <0x17>;
    						reg = <0x18c>;
    						phandle = <0x64>;
    					};
    
    					dpll_usb_ck@180 {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-j-type-clock";
    						clocks = <0x11 0x64>;
    						reg = <0x180 0x184 0x18c 0x188>;
    						phandle = <0x65>;
    					};
    
    					dpll_usb_m2_ck@190 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x65>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x190>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x68>;
    					};
    
    					dpll_pcie_ref_m2_ck@210 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x59>;
    						ti,max-div = <0x7f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x210>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x90>;
    					};
    
    					dpll_per_x2_ck {
    						#clock-cells = <0x0>;
    						compatible = "ti,omap4-dpll-x2-clock";
    						clocks = <0x61>;
    						phandle = <0x66>;
    					};
    
    					dpll_per_h11x2_ck@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x66>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x158>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x67>;
    					};
    
    					dpll_per_h12x2_ck@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x66>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x15c>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x6b>;
    					};
    
    					dpll_per_h13x2_ck@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x66>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x160>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x7e>;
    					};
    
    					dpll_per_h14x2_ck@164 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x66>;
    						ti,max-div = <0x3f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x164>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x74>;
    					};
    
    					dpll_per_m2x2_ck@150 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x66>;
    						ti,max-div = <0x1f>;
    						ti,autoidle-shift = <0x8>;
    						reg = <0x150>;
    						ti,index-starts-at-one;
    						ti,invert-autoidle-bit;
    						phandle = <0x58>;
    					};
    
    					dpll_usb_clkdcoldo {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x65>;
    						clock-mult = <0x1>;
    						clock-div = <0x1>;
    						phandle = <0x6a>;
    					};
    
    					func_128m_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x67>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x79>;
    					};
    
    					func_12m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x58>;
    						clock-mult = <0x1>;
    						clock-div = <0x10>;
    						phandle = <0x154>;
    					};
    
    					func_24m_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x62>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    						phandle = <0x40>;
    					};
    
    					func_48m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x58>;
    						clock-mult = <0x1>;
    						clock-div = <0x4>;
    						phandle = <0x57>;
    					};
    
    					func_96m_fclk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x58>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x155>;
    					};
    
    					l3init_60m_fclk@104 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x68>;
    						reg = <0x104>;
    						ti,dividers = <0x1 0x8>;
    						phandle = <0x156>;
    					};
    
    					clkout2_clk@6b0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x69>;
    						ti,bit-shift = <0x8>;
    						reg = <0x6b0>;
    						phandle = <0x12b>;
    					};
    
    					l3init_960m_gfclk@6c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6a>;
    						ti,bit-shift = <0x8>;
    						reg = <0x6c0>;
    						phandle = <0x6f>;
    					};
    
    					dss_32khz_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0xb>;
    						reg = <0x1120>;
    						phandle = <0x157>;
    					};
    
    					dss_48mhz_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x57>;
    						ti,bit-shift = <0x9>;
    						reg = <0x1120>;
    						phandle = <0x10e>;
    					};
    
    					dss_dss_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6b>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1120>;
    						ti,set-rate-parent;
    						phandle = <0x10b>;
    					};
    
    					dss_hdmi_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6c>;
    						ti,bit-shift = <0xa>;
    						reg = <0x1120>;
    						phandle = <0x10f>;
    					};
    
    					dss_video1_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6d>;
    						ti,bit-shift = <0xc>;
    						reg = <0x1120>;
    						phandle = <0x10c>;
    					};
    
    					dss_video2_clk@1120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6e>;
    						ti,bit-shift = <0xd>;
    						reg = <0x1120>;
    						phandle = <0x10d>;
    					};
    
    					gpio2_dbclk@1760 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1760>;
    						phandle = <0x158>;
    					};
    
    					gpio3_dbclk@1768 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1768>;
    						phandle = <0x159>;
    					};
    
    					gpio4_dbclk@1770 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1770>;
    						phandle = <0x15a>;
    					};
    
    					gpio5_dbclk@1778 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1778>;
    						phandle = <0x15b>;
    					};
    
    					gpio6_dbclk@1780 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1780>;
    						phandle = <0x15c>;
    					};
    
    					gpio7_dbclk@1810 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1810>;
    						phandle = <0x15d>;
    					};
    
    					gpio8_dbclk@1818 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1818>;
    						phandle = <0x15e>;
    					};
    
    					mmc1_clk32k@1328 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1328>;
    						phandle = <0x15f>;
    					};
    
    					mmc2_clk32k@1330 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1330>;
    						phandle = <0x160>;
    					};
    
    					mmc3_clk32k@1820 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1820>;
    						phandle = <0x161>;
    					};
    
    					mmc4_clk32k@1828 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1828>;
    						phandle = <0x162>;
    					};
    
    					sata_ref_clk@1388 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x11>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1388>;
    						phandle = <0xe3>;
    					};
    
    					usb_otg_ss1_refclk960m@13f0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6f>;
    						ti,bit-shift = <0x8>;
    						reg = <0x13f0>;
    						phandle = <0xec>;
    					};
    
    					usb_otg_ss2_refclk960m@1340 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x6f>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1340>;
    						phandle = <0xee>;
    					};
    
    					usb_phy1_always_on_clk32k@640 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x640>;
    						phandle = <0xeb>;
    					};
    
    					usb_phy2_always_on_clk32k@688 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x688>;
    						phandle = <0xed>;
    					};
    
    					usb_phy3_always_on_clk32k@698 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x698>;
    						phandle = <0xef>;
    					};
    
    					atl_dpll_clk_mux@c00 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x51 0x3a 0x3b 0x30>;
    						ti,bit-shift = <0x18>;
    						reg = <0xc00>;
    						phandle = <0x71>;
    					};
    
    					atl_gfclk_mux@c00 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x70 0x71>;
    						ti,bit-shift = <0x1a>;
    						reg = <0xc00>;
    						phandle = <0x10>;
    					};
    
    					rmii_50mhz_clk_mux@13d0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x39 0x72>;
    						ti,bit-shift = <0x18>;
    						reg = <0x13d0>;
    						phandle = <0x163>;
    					};
    
    					gmac_rft_clk_mux@13d0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3a 0x3b 0x70 0x30 0xa>;
    						ti,bit-shift = <0x19>;
    						reg = <0x13d0>;
    						phandle = <0x106>;
    					};
    
    					gpu_core_gclk_mux@1220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x73 0x74 0x28>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1220>;
    						assigned-clocks = <0x75>;
    						assigned-clock-parents = <0x28>;
    						phandle = <0x75>;
    					};
    
    					gpu_hyd_gclk_mux@1220 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x73 0x74 0x28>;
    						ti,bit-shift = <0x1a>;
    						reg = <0x1220>;
    						assigned-clocks = <0x76>;
    						assigned-clock-parents = <0x28>;
    						phandle = <0x76>;
    					};
    
    					l3instr_ts_gclk_div@e50 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x77>;
    						ti,bit-shift = <0x18>;
    						reg = <0xe50>;
    						ti,dividers = <0x8 0x10 0x20>;
    						phandle = <0x164>;
    					};
    
    					mcasp2_ahclkr_mux@1860 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x1c>;
    						reg = <0x1860>;
    						phandle = <0xf9>;
    					};
    
    					mcasp2_ahclkx_mux@1860 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1860>;
    						phandle = <0xf8>;
    					};
    
    					mcasp2_aux_gfclk_mux@1860 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4c 0x4d 0x4e 0x4f>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1860>;
    						phandle = <0xf7>;
    					};
    
    					mcasp3_ahclkx_mux@1868 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1868>;
    						assigned-clocks = <0x78>;
    						assigned-clock-parents = <0x3e>;
    						phandle = <0x78>;
    					};
    
    					mcasp3_aux_gfclk_mux@1868 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4c 0x4d 0x4e 0x4f>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1868>;
    						phandle = <0xfa>;
    					};
    
    					mcasp4_ahclkx_mux@1898 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1898>;
    						phandle = <0xfc>;
    					};
    
    					mcasp4_aux_gfclk_mux@1898 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4c 0x4d 0x4e 0x4f>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1898>;
    						phandle = <0xfb>;
    					};
    
    					mcasp5_ahclkx_mux@1878 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1878>;
    						phandle = <0xfe>;
    					};
    
    					mcasp5_aux_gfclk_mux@1878 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4c 0x4d 0x4e 0x4f>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1878>;
    						phandle = <0xfd>;
    					};
    
    					mcasp6_ahclkx_mux@1904 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1904>;
    						phandle = <0x100>;
    					};
    
    					mcasp6_aux_gfclk_mux@1904 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4c 0x4d 0x4e 0x4f>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1904>;
    						phandle = <0xff>;
    					};
    
    					mcasp7_ahclkx_mux@1908 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1908>;
    						phandle = <0x102>;
    					};
    
    					mcasp7_aux_gfclk_mux@1908 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4c 0x4d 0x4e 0x4f>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1908>;
    						phandle = <0x101>;
    					};
    
    					mcasp8_ahclkx_mux@1890 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
    						ti,bit-shift = <0x16>;
    						reg = <0x1890>;
    						phandle = <0x104>;
    					};
    
    					mcasp8_aux_gfclk_mux@1890 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x4c 0x4d 0x4e 0x4f>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1890>;
    						phandle = <0x103>;
    					};
    
    					mmc1_fclk_mux@1328 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x79 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1328>;
    						phandle = <0x7a>;
    					};
    
    					mmc1_fclk_div@1328 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x7a>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1328>;
    						ti,index-power-of-two;
    						phandle = <0x165>;
    					};
    
    					mmc2_fclk_mux@1330 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x79 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1330>;
    						phandle = <0x7b>;
    					};
    
    					mmc2_fclk_div@1330 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x7b>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1330>;
    						ti,index-power-of-two;
    						phandle = <0x166>;
    					};
    
    					mmc3_gfclk_mux@1820 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1820>;
    						phandle = <0x7c>;
    					};
    
    					mmc3_gfclk_div@1820 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x7c>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1820>;
    						ti,index-power-of-two;
    						phandle = <0x167>;
    					};
    
    					mmc4_gfclk_mux@1828 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1828>;
    						phandle = <0x7d>;
    					};
    
    					mmc4_gfclk_div@1828 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x7d>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1828>;
    						ti,index-power-of-two;
    						phandle = <0x168>;
    					};
    
    					qspi_gfclk_mux@1838 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x79 0x7e>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1838>;
    						phandle = <0x7f>;
    					};
    
    					qspi_gfclk_div@1838 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x7f>;
    						ti,bit-shift = <0x19>;
    						ti,max-div = <0x4>;
    						reg = <0x1838>;
    						ti,index-power-of-two;
    						phandle = <0xe2>;
    					};
    
    					timer10_gfclk_mux@1728 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1728>;
    						phandle = <0x169>;
    					};
    
    					timer11_gfclk_mux@1730 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1730>;
    						phandle = <0x16a>;
    					};
    
    					timer13_gfclk_mux@17c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x17c8>;
    						phandle = <0x16b>;
    					};
    
    					timer14_gfclk_mux@17d0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x17d0>;
    						phandle = <0x16c>;
    					};
    
    					timer15_gfclk_mux@17d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x17d8>;
    						phandle = <0x16d>;
    					};
    
    					timer16_gfclk_mux@1830 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1830>;
    						assigned-clocks = <0x80>;
    						assigned-clock-parents = <0x52>;
    						phandle = <0x80>;
    					};
    
    					timer2_gfclk_mux@1738 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1738>;
    						phandle = <0x16e>;
    					};
    
    					timer3_gfclk_mux@1740 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1740>;
    						phandle = <0x16f>;
    					};
    
    					timer4_gfclk_mux@1748 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1748>;
    						phandle = <0x170>;
    					};
    
    					timer9_gfclk_mux@1750 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1750>;
    						phandle = <0x171>;
    					};
    
    					uart1_gfclk_mux@1840 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1840>;
    						phandle = <0x172>;
    					};
    
    					uart2_gfclk_mux@1848 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1848>;
    						phandle = <0x173>;
    					};
    
    					uart3_gfclk_mux@1850 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1850>;
    						phandle = <0x174>;
    					};
    
    					uart4_gfclk_mux@1858 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1858>;
    						phandle = <0x175>;
    					};
    
    					uart5_gfclk_mux@1870 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1870>;
    						phandle = <0x176>;
    					};
    
    					uart7_gfclk_mux@18d0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x18d0>;
    						phandle = <0x177>;
    					};
    
    					uart8_gfclk_mux@18e0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x18e0>;
    						phandle = <0x178>;
    					};
    
    					uart9_gfclk_mux@18e8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x18e8>;
    						phandle = <0x179>;
    					};
    
    					vip1_gclk_mux@1020 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x81>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1020>;
    						phandle = <0x17a>;
    					};
    
    					vip2_gclk_mux@1028 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x81>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1028>;
    						phandle = <0x17b>;
    					};
    
    					vip3_gclk_mux@1030 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0xa 0x81>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1030>;
    						phandle = <0x17c>;
    					};
    				};
    
    				clockdomains {
    					phandle = <0x17d>;
    
    					coreaon_clkdm {
    						compatible = "ti,clockdomain";
    						clocks = <0x65>;
    						phandle = <0x17e>;
    					};
    				};
    			};
    		};
    
    		l4@4ae00000 {
    			compatible = "ti,dra7-l4-wkup", "simple-bus";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4ae00000 0x3f000>;
    			phandle = <0x17f>;
    
    			counter@4000 {
    				compatible = "ti,omap-counter32k";
    				reg = <0x4000 0x40>;
    				ti,hwmods = "counter_32k";
    				phandle = <0x180>;
    			};
    
    			prm@6000 {
    				compatible = "ti,dra7-prm";
    				reg = <0x6000 0x3000>;
    				interrupts = <0x0 0x6 0x4>;
    				phandle = <0x181>;
    
    				clocks {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					phandle = <0x182>;
    
    					sys_clkin1@110 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x82 0x83 0x84 0x85 0x86 0x87 0x88>;
    						reg = <0x110>;
    						ti,index-starts-at-one;
    						phandle = <0x11>;
    					};
    
    					abe_dpll_sys_clk_mux@118 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x45>;
    						reg = <0x118>;
    						phandle = <0x89>;
    					};
    
    					abe_dpll_bypass_clk_mux@114 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x89 0x51>;
    						reg = <0x114>;
    						phandle = <0x13>;
    					};
    
    					abe_dpll_clk_mux@10c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x89 0x51>;
    						reg = <0x10c>;
    						phandle = <0x12>;
    					};
    
    					abe_24m_fclk@11c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x16>;
    						reg = <0x11c>;
    						ti,dividers = <0x8 0x10>;
    						phandle = <0x3e>;
    					};
    
    					aess_fclk@178 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8a>;
    						reg = <0x178>;
    						ti,max-div = <0x2>;
    						phandle = <0x8b>;
    					};
    
    					abe_giclk_div@174 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8b>;
    						reg = <0x174>;
    						ti,max-div = <0x2>;
    						phandle = <0x52>;
    					};
    
    					abe_lp_clk_div@1d8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x16>;
    						reg = <0x1d8>;
    						ti,dividers = <0x10 0x20>;
    						phandle = <0xaa>;
    					};
    
    					abe_sys_clk_div@120 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						reg = <0x120>;
    						ti,max-div = <0x2>;
    						phandle = <0x3f>;
    					};
    
    					adc_gfclk_mux@1dc {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x45 0x51>;
    						reg = <0x1dc>;
    						phandle = <0x183>;
    					};
    
    					sys_clk1_dclk_div@1c8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						ti,max-div = <0x40>;
    						reg = <0x1c8>;
    						ti,index-power-of-two;
    						phandle = <0x93>;
    					};
    
    					sys_clk2_dclk_div@1cc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x45>;
    						ti,max-div = <0x40>;
    						reg = <0x1cc>;
    						ti,index-power-of-two;
    						phandle = <0x94>;
    					};
    
    					per_abe_x1_dclk_div@1bc {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x70>;
    						ti,max-div = <0x40>;
    						reg = <0x1bc>;
    						ti,index-power-of-two;
    						phandle = <0x95>;
    					};
    
    					dsp_gclk_div@18c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x21>;
    						ti,max-div = <0x40>;
    						reg = <0x18c>;
    						ti,index-power-of-two;
    						phandle = <0x97>;
    					};
    
    					gpu_dclk@1a0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x28>;
    						ti,max-div = <0x40>;
    						reg = <0x1a0>;
    						ti,index-power-of-two;
    						phandle = <0x99>;
    					};
    
    					emif_phy_dclk_div@190 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8c>;
    						ti,max-div = <0x40>;
    						reg = <0x190>;
    						ti,index-power-of-two;
    						phandle = <0x9b>;
    					};
    
    					gmac_250m_dclk_div@19c {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8d>;
    						ti,max-div = <0x40>;
    						reg = <0x19c>;
    						ti,index-power-of-two;
    						phandle = <0x8e>;
    					};
    
    					gmac_main_clk {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x8e>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x105>;
    					};
    
    					l3init_480m_dclk_div@1ac {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x68>;
    						ti,max-div = <0x40>;
    						reg = <0x1ac>;
    						ti,index-power-of-two;
    						phandle = <0xa0>;
    					};
    
    					usb_otg_dclk_div@184 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x8f>;
    						ti,max-div = <0x40>;
    						reg = <0x184>;
    						ti,index-power-of-two;
    						phandle = <0xa1>;
    					};
    
    					sata_dclk_div@1c0 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						ti,max-div = <0x40>;
    						reg = <0x1c0>;
    						ti,index-power-of-two;
    						phandle = <0xa2>;
    					};
    
    					pcie2_dclk_div@1b8 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x90>;
    						ti,max-div = <0x40>;
    						reg = <0x1b8>;
    						ti,index-power-of-two;
    						phandle = <0xa3>;
    					};
    
    					pcie_dclk_div@1b4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x91>;
    						ti,max-div = <0x40>;
    						reg = <0x1b4>;
    						ti,index-power-of-two;
    						phandle = <0xa4>;
    					};
    
    					emu_dclk_div@194 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						ti,max-div = <0x40>;
    						reg = <0x194>;
    						ti,index-power-of-two;
    						phandle = <0xa5>;
    					};
    
    					secure_32k_dclk_div@1c4 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x92>;
    						ti,max-div = <0x40>;
    						reg = <0x1c4>;
    						ti,index-power-of-two;
    						phandle = <0xa6>;
    					};
    
    					clkoutmux0_clk_mux@158 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x8e 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>;
    						reg = <0x158>;
    						phandle = <0x56>;
    					};
    
    					clkoutmux1_clk_mux@15c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x8e 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>;
    						reg = <0x15c>;
    						phandle = <0x184>;
    					};
    
    					clkoutmux2_clk_mux@160 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x8e 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>;
    						reg = <0x160>;
    						phandle = <0x69>;
    					};
    
    					custefuse_sys_gfclk_div {
    						#clock-cells = <0x0>;
    						compatible = "fixed-factor-clock";
    						clocks = <0x11>;
    						clock-mult = <0x1>;
    						clock-div = <0x2>;
    						phandle = <0x185>;
    					};
    
    					eve_clk@180 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x34 0x37>;
    						reg = <0x180>;
    						phandle = <0x186>;
    					};
    
    					hdmi_dpll_clk_mux@164 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x45>;
    						reg = <0x164>;
    						phandle = <0x6c>;
    					};
    
    					mlb_clk@134 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0xa8>;
    						ti,max-div = <0x40>;
    						reg = <0x134>;
    						ti,index-power-of-two;
    						phandle = <0x4a>;
    					};
    
    					mlbp_clk@130 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0xa9>;
    						ti,max-div = <0x40>;
    						reg = <0x130>;
    						ti,index-power-of-two;
    						phandle = <0x4b>;
    					};
    
    					per_abe_x1_gfclk2_div@138 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x70>;
    						ti,max-div = <0x40>;
    						reg = <0x138>;
    						ti,index-power-of-two;
    						phandle = <0x4c>;
    					};
    
    					timer_sys_clk_div@144 {
    						#clock-cells = <0x0>;
    						compatible = "ti,divider-clock";
    						clocks = <0x11>;
    						reg = <0x144>;
    						ti,max-div = <0x2>;
    						phandle = <0x50>;
    					};
    
    					video1_dpll_clk_mux@168 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x45>;
    						reg = <0x168>;
    						phandle = <0x6d>;
    					};
    
    					video2_dpll_clk_mux@16c {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x45>;
    						reg = <0x16c>;
    						phandle = <0x6e>;
    					};
    
    					wkupaon_iclk_mux@108 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0xaa>;
    						reg = <0x108>;
    						phandle = <0x77>;
    					};
    
    					gpio1_dbclk@1838 {
    						#clock-cells = <0x0>;
    						compatible = "ti,gate-clock";
    						clocks = <0x51>;
    						ti,bit-shift = <0x8>;
    						reg = <0x1838>;
    						phandle = <0x187>;
    					};
    
    					dcan1_sys_clk_mux@1888 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x11 0x45>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1888>;
    						phandle = <0x109>;
    					};
    
    					timer1_gfclk_mux@1840 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1840>;
    						phandle = <0x188>;
    					};
    
    					uart10_gfclk_mux@1880 {
    						#clock-cells = <0x0>;
    						compatible = "ti,mux-clock";
    						clocks = <0x57 0x58>;
    						ti,bit-shift = <0x18>;
    						reg = <0x1880>;
    						phandle = <0x189>;
    					};
    				};
    
    				clockdomains {
    					phandle = <0x18a>;
    				};
    			};
    
    			scm_conf@c000 {
    				compatible = "syscon";
    				reg = <0xc000 0x1000>;
    				phandle = <0x7>;
    			};
    		};
    
    		axi@0 {
    			compatible = "simple-bus";
    			#size-cells = <0x1>;
    			#address-cells = <0x1>;
    			ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>;
    
    			pcie@51000000 {
    				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
    				reg = <0x51000000 0x2000 0x51002000 0x14c 0x1000 0x2000>;
    				reg-names = "rc_dbics", "ti_conf", "config";
    				interrupts = <0x0 0xe8 0x4 0x0 0xe9 0x4>;
    				#address-cells = <0x3>;
    				#size-cells = <0x2>;
    				device_type = "pci";
    				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x20013000 0x13000 0x0 0xffed000>;
    				bus-range = <0x0 0xff>;
    				#interrupt-cells = <0x1>;
    				num-lanes = <0x1>;
    				linux,pci-domain = <0x0>;
    				ti,hwmods = "pcie1";
    				phys = <0xab>;
    				phy-names = "pcie-phy0";
    				ti,syscon-conf = <0x9>;
    				ti,syscon-pcie = <0xac>;
    				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    				interrupt-map = <0x0 0x0 0x0 0x1 0xad 0x1 0x0 0x0 0x0 0x2 0xad 0x2 0x0 0x0 0x0 0x3 0xad 0x3 0x0 0x0 0x0 0x4 0xad 0x4>;
    				ti,syscon-unaligned-access = <0xae 0x14 0x1>;
    				status = "ok";
    				gpios = <0xaf 0x8 0x1>;
    				phandle = <0x18b>;
    
    				interrupt-controller {
    					interrupt-controller;
    					#address-cells = <0x0>;
    					#interrupt-cells = <0x1>;
    					phandle = <0xad>;
    				};
    			};
    
    			pcie_ep@51000000 {
    				compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
    				reg = <0x51000000 0x28 0x51002000 0x14c 0x51001000 0x28 0x1000 0x10000000>;
    				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
    				interrupts = <0x0 0xe8 0x4>;
    				num-lanes = <0x1>;
    				num-ib-windows = <0x4>;
    				num-ob-windows = <0x10>;
    				ti,hwmods = "pcie1";
    				phys = <0xab>;
    				phy-names = "pcie-phy0";
    				ti,syscon-unaligned-access = <0xae 0x14 0x1>;
    				ti,syscon-conf = <0x9>;
    				ti,syscon-pcie = <0xac>;
    				status = "disabled";
    				gpios = <0xaf 0x8 0x1>;
    				phandle = <0x18c>;
    			};
    		};
    
    		axi@1 {
    			compatible = "simple-bus";
    			#size-cells = <0x1>;
    			#address-cells = <0x1>;
    			ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>;
    			status = "disabled";
    
    			pcie@51800000 {
    				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
    				reg = <0x51800000 0x2000 0x51802000 0x14c 0x1000 0x2000>;
    				reg-names = "rc_dbics", "ti_conf", "config";
    				interrupts = <0x0 0x163 0x4 0x0 0x164 0x4>;
    				#address-cells = <0x3>;
    				#size-cells = <0x2>;
    				device_type = "pci";
    				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x30013000 0x13000 0x0 0xffed000>;
    				bus-range = <0x0 0xff>;
    				#interrupt-cells = <0x1>;
    				num-lanes = <0x1>;
    				linux,pci-domain = <0x1>;
    				ti,hwmods = "pcie2";
    				phys = <0xb0>;
    				phy-names = "pcie-phy0";
    				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
    				interrupt-map = <0x0 0x0 0x0 0x1 0xb1 0x1 0x0 0x0 0x0 0x2 0xb1 0x2 0x0 0x0 0x0 0x3 0xb1 0x3 0x0 0x0 0x0 0x4 0xb1 0x4>;
    				ti,syscon-unaligned-access = <0xae 0x14 0x2>;
    				phandle = <0x18d>;
    
    				interrupt-controller {
    					interrupt-controller;
    					#address-cells = <0x0>;
    					#interrupt-cells = <0x1>;
    					phandle = <0xb1>;
    				};
    			};
    		};
    
    		ocmcram@40300000 {
    			compatible = "mmio-sram";
    			reg = <0x40300000 0x80000>;
    			ranges = <0x0 0x40300000 0x80000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			phandle = <0x18e>;
    
    			sram-hs@0 {
    				compatible = "ti,secure-ram";
    				reg = <0x0 0x0>;
    			};
    		};
    
    		ocmcram@40400000 {
    			status = "disabled";
    			compatible = "mmio-sram";
    			reg = <0x40400000 0x100000>;
    			ranges = <0x0 0x40400000 0x100000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			phandle = <0x18f>;
    		};
    
    		ocmcram@40500000 {
    			status = "disabled";
    			compatible = "mmio-sram";
    			reg = <0x40500000 0x100000>;
    			ranges = <0x0 0x40500000 0x100000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			phandle = <0x190>;
    		};
    
    		bandgap@4a0021e0 {
    			reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023c0 0x3c 0x4a002564 0x8 0x4a002574 0x50>;
    			compatible = "ti,dra752-bandgap";
    			interrupts = <0x0 0x79 0x4>;
    			#thermal-sensor-cells = <0x1>;
    			phandle = <0x11b>;
    		};
    
    		dsp_system@40d00000 {
    			compatible = "syscon";
    			reg = <0x40d00000 0x100>;
    			phandle = <0xde>;
    		};
    
    		padconf@4844a000 {
    			compatible = "ti,dra7-iodelay";
    			reg = <0x4844a000 0xd1c>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			#pinctrl-cells = <0x2>;
    			phandle = <0x191>;
    
    			mmc1_iodelay_ddr_rev11_conf {
    				pinctrl-pin-array = <0x618 0x23c 0x21c 0x620 0x5f5 0x0 0x624 0x0 0x258 0x628 0x0 0x0 0x62c 0x37 0x0 0x630 0x193 0x78 0x634 0x0 0x0 0x638 0x0 0x0 0x63c 0x17 0x3c 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x19 0x3c 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    				phandle = <0x192>;
    			};
    
    			mmc1_iodelay_ddr50_rev20_conf {
    				pinctrl-pin-array = <0x618 0x434 0x14a 0x620 0x4f7 0x0 0x624 0x2d2 0x0 0x628 0x0 0x0 0x62c 0x0 0x0 0x630 0x2ef 0x0 0x634 0x0 0x0 0x638 0x14 0x0 0x63c 0x100 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x107 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    				phandle = <0xd8>;
    			};
    
    			mmc1_iodelay_sdr104_rev11_conf {
    				pinctrl-pin-array = <0x620 0x427 0x11 0x628 0x0 0x0 0x62c 0x17 0x0 0x634 0x0 0x0 0x638 0x0 0x0 0x640 0x0 0x0 0x644 0x2 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    				phandle = <0x193>;
    			};
    
    			mmc1_iodelay_sdr104_rev20_conf {
    				pinctrl-pin-array = <0x620 0x258 0x190 0x628 0x0 0x0 0x62c 0x0 0x0 0x634 0x0 0x0 0x638 0x1e 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
    				phandle = <0xda>;
    			};
    
    			mmc2_iodelay_hs200_rev11_conf {
    				pinctrl-pin-array = <0x190 0x26d 0x258 0x194 0x12c 0x0 0x1a8 0x2e3 0x258 0x1ac 0xf0 0x0 0x1b4 0x32c 0x258 0x1b8 0xf0 0x0 0x1c0 0x3ba 0x258 0x1c4 0x3c 0x0 0x1d0 0x53c 0x1a4 0x1d8 0x3a7 0x258 0x1dc 0x0 0x0 0x1e4 0x20d 0x258 0x1e8 0x78 0x0 0x1f0 0x2ff 0x258 0x1f4 0xe1 0x0 0x1fc 0x235 0x258 0x200 0x3c 0x0 0x364 0x3c9 0x258 0x368 0xb4 0x0>;
    				phandle = <0x194>;
    			};
    
    			mmc2_iodelay_hs200_rev20_conf {
    				pinctrl-pin-array = <0x190 0x112 0x0 0x194 0xa2 0x0 0x1a8 0x191 0x0 0x1ac 0x49 0x0 0x1b4 0x1d1 0x0 0x1b8 0x73 0x0 0x1c0 0x279 0x0 0x1c4 0x2f 0x0 0x1d0 0x3a7 0x118 0x1d8 0x26d 0x0 0x1dc 0x0 0x0 0x1e4 0xb7 0x0 0x1e8 0x0 0x0 0x1f0 0x1d3 0x0 0x1f4 0x0 0x0 0x1fc 0x106 0x0 0x200 0x2e 0x0 0x364 0x2ac 0x0 0x368 0x4c 0x0>;
    				phandle = <0x195>;
    			};
    
    			mmc2_iodelay_ddr_3_3v_rev11_conf {
    				pinctrl-pin-array = <0x18c 0x0 0x78 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x109 0x168 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x78 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x78 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x11f 0x1a4 0x1d0 0x36f 0x0 0x1d4 0x90 0xf0 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x78 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x78 0xb4 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
    				phandle = <0x196>;
    			};
    
    			mmc2_iodelay_ddr_1_8v_rev11_conf {
    				pinctrl-pin-array = <0x18c 0x0 0x0 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x112 0xf0 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x3c 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x3c 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x202 0x168 0x1d0 0x36f 0x0 0x1d4 0xbb 0x78 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x3c 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x79 0x3c 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
    				phandle = <0x197>;
    			};
    
    			mmc3_iodelay_manual1_conf {
    				pinctrl-pin-array = <0x678 0x196 0x0 0x680 0x293 0x0 0x684 0x0 0x0 0x688 0x0 0x0 0x68c 0x0 0x0 0x690 0x82 0x0 0x694 0x0 0x0 0x698 0x0 0x0 0x69c 0xa9 0x0 0x6a0 0x0 0x0 0x6a4 0x0 0x0 0x6a8 0x0 0x0 0x6ac 0x0 0x0 0x6b0 0x0 0x0 0x6b4 0x1c9 0x0 0x6b8 0x0 0x0 0x6bc 0x0 0x0>;
    				phandle = <0x198>;
    			};
    
    			mmc4_iodelay_ds_rev11_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x60 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x246 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x187 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x231 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x24c 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    				phandle = <0x199>;
    			};
    
    			mmc4_iodelay_ds_rev20_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x133 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x311 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x265 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x2ab 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x343 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    				phandle = <0x19a>;
    			};
    
    			mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0xa5b 0x0 0x84c 0x624 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x779 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x6b9 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x763 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x77f 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
    				phandle = <0x19b>;
    			};
    
    			mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
    				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x47b 0x0 0x84c 0x72a 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x875 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x789 0x40 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x78f 0x80 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x87c 0x2c 0x898 0x0 0x0 0x89c 0x0 0x0>;
    				phandle = <0x19c>;
    			};
    		};
    
    		dma-controller@4a056000 {
    			compatible = "ti,omap4430-sdma";
    			reg = <0x4a056000 0x1000>;
    			interrupts = <0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4 0x0 0xa 0x4>;
    			#dma-cells = <0x1>;
    			dma-channels = <0x20>;
    			dma-requests = <0x7f>;
    			phandle = <0xe>;
    		};
    
    		edma@43300000 {
    			compatible = "ti,edma3-tpcc";
    			ti,hwmods = "tpcc";
    			reg = <0x43300000 0x100000>;
    			reg-names = "edma3_cc";
    			interrupts = <0x0 0x169 0x4 0x0 0x168 0x4 0x0 0x167 0x4>;
    			interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
    			dma-requests = <0x40>;
    			#dma-cells = <0x2>;
    			ti,tptcs = <0xb2 0x7 0xb3 0x0>;
    			phandle = <0xf>;
    		};
    
    		tptc@43400000 {
    			compatible = "ti,edma3-tptc";
    			ti,hwmods = "tptc0";
    			reg = <0x43400000 0x100000>;
    			interrupts = <0x0 0x172 0x4>;
    			interrupt-names = "edma3_tcerrint";
    			phandle = <0xb2>;
    		};
    
    		tptc@43500000 {
    			compatible = "ti,edma3-tptc";
    			ti,hwmods = "tptc1";
    			reg = <0x43500000 0x100000>;
    			interrupts = <0x0 0x173 0x4>;
    			interrupt-names = "edma3_tcerrint";
    			phandle = <0xb3>;
    		};
    
    		gpio@4ae10000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4ae10000 0x200>;
    			interrupts = <0x0 0x18 0x4>;
    			ti,hwmods = "gpio1";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0xcb>;
    		};
    
    		gpio@48055000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48055000 0x200>;
    			interrupts = <0x0 0x19 0x4>;
    			ti,hwmods = "gpio2";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0xaf>;
    		};
    
    		gpio@48057000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48057000 0x200>;
    			interrupts = <0x0 0x1a 0x4>;
    			ti,hwmods = "gpio3";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0x19d>;
    		};
    
    		gpio@48059000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48059000 0x200>;
    			interrupts = <0x0 0x1b 0x4>;
    			ti,hwmods = "gpio4";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0xcd>;
    		};
    
    		gpio@4805b000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4805b000 0x200>;
    			interrupts = <0x0 0x1c 0x4>;
    			ti,hwmods = "gpio5";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0x19e>;
    		};
    
    		gpio@4805d000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x4805d000 0x200>;
    			interrupts = <0x0 0x1d 0x4>;
    			ti,hwmods = "gpio6";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0x19f>;
    		};
    
    		gpio@48051000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48051000 0x200>;
    			interrupts = <0x0 0x1e 0x4>;
    			ti,hwmods = "gpio7";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			ti,no-reset-on-init;
    			ti,no-idle-on-init;
    			phandle = <0xce>;
    		};
    
    		gpio@48053000 {
    			compatible = "ti,omap4-gpio";
    			reg = <0x48053000 0x200>;
    			interrupts = <0x0 0x74 0x4>;
    			ti,hwmods = "gpio8";
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			phandle = <0x1a0>;
    		};
    
    		serial@4806a000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806a000 0x100>;
    			interrupts-extended = <0x1 0x0 0x43 0x4>;
    			ti,hwmods = "uart1";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xb4 0x31 0xb4 0x32>;
    			dma-names = "tx", "rx";
    			phandle = <0x1a1>;
    		};
    
    		serial@4806c000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806c000 0x100>;
    			interrupts = <0x0 0x44 0x4>;
    			ti,hwmods = "uart2";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xb4 0x33 0xb4 0x34>;
    			dma-names = "tx", "rx";
    			phandle = <0x1a2>;
    		};
    
    		serial@48020000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48020000 0x100>;
    			interrupts = <0x0 0x45 0x4>;
    			ti,hwmods = "uart3";
    			clock-frequency = <0x2dc6c00>;
    			status = "okay";
    			dmas = <0xb4 0x35 0xb4 0x36>;
    			dma-names = "tx", "rx";
    			interrupts-extended = <0x1 0x0 0x45 0x4 0xb5 0x3f8>;
    			phandle = <0x1a3>;
    		};
    
    		serial@4806e000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4806e000 0x100>;
    			interrupts = <0x0 0x41 0x4>;
    			ti,hwmods = "uart4";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xb4 0x37 0xb4 0x38>;
    			dma-names = "tx", "rx";
    			phandle = <0x1a4>;
    		};
    
    		serial@48066000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48066000 0x100>;
    			interrupts = <0x0 0x64 0x4>;
    			ti,hwmods = "uart5";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xb4 0x3f 0xb4 0x40>;
    			dma-names = "tx", "rx";
    			phandle = <0x1a5>;
    		};
    
    		serial@48068000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48068000 0x100>;
    			interrupts = <0x0 0x65 0x4>;
    			ti,hwmods = "uart6";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			dmas = <0xb4 0x4f 0xb4 0x50>;
    			dma-names = "tx", "rx";
    			phandle = <0x1a6>;
    		};
    
    		serial@48420000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48420000 0x100>;
    			interrupts = <0x0 0xda 0x4>;
    			ti,hwmods = "uart7";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			phandle = <0x1a7>;
    		};
    
    		serial@48422000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48422000 0x100>;
    			interrupts = <0x0 0xdb 0x4>;
    			ti,hwmods = "uart8";
    			clock-frequency = <0x2dc6c00>;
    			status = "okay";
    			phandle = <0x1a8>;
    		};
    
    		serial@48424000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x48424000 0x100>;
    			interrupts = <0x0 0xdc 0x4>;
    			ti,hwmods = "uart9";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			phandle = <0x1a9>;
    		};
    
    		serial@4ae2b000 {
    			compatible = "ti,dra742-uart", "ti,omap4-uart";
    			reg = <0x4ae2b000 0x100>;
    			interrupts = <0x0 0xdd 0x4>;
    			ti,hwmods = "uart10";
    			clock-frequency = <0x2dc6c00>;
    			status = "disabled";
    			phandle = <0x1aa>;
    		};
    
    		mailbox@4a0f4000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4a0f4000 0x200>;
    			interrupts = <0x0 0x15 0x4 0x0 0x87 0x4 0x0 0x86 0x4>;
    			ti,hwmods = "mailbox1";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x3>;
    			ti,mbox-num-fifos = <0x8>;
    			status = "disabled";
    			phandle = <0x1ab>;
    		};
    
    		mailbox@4883a000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883a000 0x200>;
    			interrupts = <0x0 0xed 0x4 0x0 0xee 0x4 0x0 0xef 0x4 0x0 0xf0 0x4>;
    			ti,hwmods = "mailbox2";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1ac>;
    		};
    
    		mailbox@4883c000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883c000 0x200>;
    			interrupts = <0x0 0xf1 0x4 0x0 0xf2 0x4 0x0 0xf3 0x4 0x0 0xf4 0x4>;
    			ti,hwmods = "mailbox3";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1ad>;
    		};
    
    		mailbox@4883e000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4883e000 0x200>;
    			interrupts = <0x0 0xf5 0x4 0x0 0xf6 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4>;
    			ti,hwmods = "mailbox4";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1ae>;
    		};
    
    		mailbox@48840000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48840000 0x200>;
    			interrupts = <0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4>;
    			ti,hwmods = "mailbox5";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "okay";
    			phandle = <0xb7>;
    
    			mbox_ipu1_ipc3x {
    				ti,mbox-tx = <0x6 0x2 0x2>;
    				ti,mbox-rx = <0x4 0x2 0x2>;
    				status = "okay";
    				phandle = <0xb8>;
    			};
    
    			mbox_dsp1_ipc3x {
    				ti,mbox-tx = <0x5 0x2 0x2>;
    				ti,mbox-rx = <0x1 0x2 0x2>;
    				status = "okay";
    				phandle = <0xc7>;
    			};
    		};
    
    		mailbox@48842000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48842000 0x200>;
    			interrupts = <0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4>;
    			ti,hwmods = "mailbox6";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "okay";
    			phandle = <0xbf>;
    
    			mbox_ipu2_ipc3x {
    				ti,mbox-tx = <0x6 0x2 0x2>;
    				ti,mbox-rx = <0x4 0x2 0x2>;
    				status = "okay";
    				phandle = <0xc0>;
    			};
    
    			mbox_dsp2_ipc3x {
    				ti,mbox-tx = <0x5 0x2 0x2>;
    				ti,mbox-rx = <0x1 0x2 0x2>;
    				status = "okay";
    				phandle = <0x117>;
    			};
    		};
    
    		mailbox@48844000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48844000 0x200>;
    			interrupts = <0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4>;
    			ti,hwmods = "mailbox7";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1af>;
    		};
    
    		mailbox@48846000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48846000 0x200>;
    			interrupts = <0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4>;
    			ti,hwmods = "mailbox8";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1b0>;
    		};
    
    		mailbox@4885e000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x4885e000 0x200>;
    			interrupts = <0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4>;
    			ti,hwmods = "mailbox9";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1b1>;
    		};
    
    		mailbox@48860000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48860000 0x200>;
    			interrupts = <0x0 0x10d 0x4 0x0 0x10e 0x4 0x0 0x10f 0x4 0x0 0x110 0x4>;
    			ti,hwmods = "mailbox10";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1b2>;
    		};
    
    		mailbox@48862000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48862000 0x200>;
    			interrupts = <0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>;
    			ti,hwmods = "mailbox11";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1b3>;
    		};
    
    		mailbox@48864000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48864000 0x200>;
    			interrupts = <0x0 0x115 0x4 0x0 0x116 0x4 0x0 0x117 0x4 0x0 0x118 0x4>;
    			ti,hwmods = "mailbox12";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1b4>;
    		};
    
    		mailbox@48802000 {
    			compatible = "ti,omap4-mailbox";
    			reg = <0x48802000 0x200>;
    			interrupts = <0x0 0x17b 0x4 0x0 0x17c 0x4 0x0 0x17d 0x4 0x0 0x17e 0x4>;
    			ti,hwmods = "mailbox13";
    			#mbox-cells = <0x1>;
    			ti,mbox-num-users = <0x4>;
    			ti,mbox-num-fifos = <0xc>;
    			status = "disabled";
    			phandle = <0x1b5>;
    		};
    
    		timer@4ae18000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4ae18000 0x80>;
    			interrupts = <0x0 0x20 0x4>;
    			ti,hwmods = "timer1";
    			ti,timer-alwon;
    			phandle = <0x1b6>;
    		};
    
    		timer@48032000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48032000 0x80>;
    			interrupts = <0x0 0x21 0x4>;
    			ti,hwmods = "timer2";
    			phandle = <0x1b7>;
    		};
    
    		timer@48034000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48034000 0x80>;
    			interrupts = <0x0 0x22 0x4>;
    			ti,hwmods = "timer3";
    			phandle = <0xc1>;
    		};
    
    		timer@48036000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48036000 0x80>;
    			interrupts = <0x0 0x23 0x4>;
    			ti,hwmods = "timer4";
    			phandle = <0xc2>;
    		};
    
    		timer@48820000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48820000 0x80>;
    			interrupts = <0x0 0x24 0x4>;
    			ti,hwmods = "timer5";
    			phandle = <0xc8>;
    		};
    
    		timer@48822000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48822000 0x80>;
    			interrupts = <0x0 0x25 0x4>;
    			ti,hwmods = "timer6";
    			phandle = <0x118>;
    		};
    
    		timer@48824000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48824000 0x80>;
    			interrupts = <0x0 0x26 0x4>;
    			ti,hwmods = "timer7";
    			phandle = <0xbb>;
    		};
    
    		timer@48826000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48826000 0x80>;
    			interrupts = <0x0 0x27 0x4>;
    			ti,hwmods = "timer8";
    			phandle = <0xbc>;
    		};
    
    		timer@4803e000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4803e000 0x80>;
    			interrupts = <0x0 0x28 0x4>;
    			ti,hwmods = "timer9";
    			phandle = <0xc3>;
    		};
    
    		timer@48086000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48086000 0x80>;
    			interrupts = <0x0 0x29 0x4>;
    			ti,hwmods = "timer10";
    			phandle = <0xc9>;
    		};
    
    		timer@48088000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48088000 0x80>;
    			interrupts = <0x0 0x2a 0x4>;
    			ti,hwmods = "timer11";
    			phandle = <0xb9>;
    		};
    
    		timer@4ae20000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4ae20000 0x80>;
    			interrupts = <0x0 0x5a 0x4>;
    			ti,hwmods = "timer12";
    			ti,timer-alwon;
    			ti,timer-secure;
    			phandle = <0x1b8>;
    		};
    
    		timer@48828000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x48828000 0x80>;
    			interrupts = <0x0 0x153 0x4>;
    			ti,hwmods = "timer13";
    			phandle = <0x119>;
    		};
    
    		timer@4882a000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882a000 0x80>;
    			interrupts = <0x0 0x154 0x4>;
    			ti,hwmods = "timer14";
    			phandle = <0xba>;
    		};
    
    		timer@4882c000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882c000 0x80>;
    			interrupts = <0x0 0x155 0x4>;
    			ti,hwmods = "timer15";
    			phandle = <0x1b9>;
    		};
    
    		timer@4882e000 {
    			compatible = "ti,omap5430-timer";
    			reg = <0x4882e000 0x80>;
    			interrupts = <0x0 0x156 0x4>;
    			ti,hwmods = "timer16";
    			phandle = <0x1ba>;
    		};
    
    		wdt@4ae14000 {
    			compatible = "ti,omap3-wdt";
    			reg = <0x4ae14000 0x80>;
    			interrupts = <0x0 0x4b 0x4>;
    			ti,hwmods = "wd_timer2";
    			phandle = <0x1bb>;
    		};
    
    		spinlock@4a0f6000 {
    			compatible = "ti,omap4-hwspinlock";
    			reg = <0x4a0f6000 0x1000>;
    			ti,hwmods = "spinlock";
    			#hwlock-cells = <0x1>;
    			phandle = <0x1bc>;
    		};
    
    		dmm@4e000000 {
    			compatible = "ti,dra7-dmm", "ti,omap5-dmm";
    			reg = <0x4e000000 0x800>;
    			interrupts = <0x0 0x6c 0x4>;
    			ti,hwmods = "dmm";
    		};
    
    		ipu@58820000 {
    			compatible = "ti,dra7-ipu";
    			reg = <0x58820000 0x10000>;
    			reg-names = "l2ram";
    			ti,hwmods = "ipu1";
    			iommus = <0xb6>;
    			ti,rproc-standby-info = <0x4a005520>;
    			status = "okay";
    			mboxes = <0xb7 0xb8>;
    			timers = <0xb9 0xba>;
    			watchdog-timers = <0xbb 0xbc>;
    			memory-region = <0xbd>;
    			phandle = <0x1bd>;
    		};
    
    		ipu@55020000 {
    			compatible = "ti,dra7-ipu";
    			reg = <0x55020000 0x10000>;
    			reg-names = "l2ram";
    			ti,hwmods = "ipu2";
    			iommus = <0xbe>;
    			ti,rproc-standby-info = <0x4a008920>;
    			status = "okay";
    			mboxes = <0xbf 0xc0>;
    			timers = <0xc1>;
    			watchdog-timers = <0xc2 0xc3>;
    			memory-region = <0xc4>;
    			phandle = <0x1be>;
    		};
    
    		dsp@40800000 {
    			compatible = "ti,dra7-dsp";
    			reg = <0x40800000 0x48000 0x40e00000 0x8000 0x40f00000 0x8000>;
    			reg-names = "l2ram", "l1pram", "l1dram";
    			ti,hwmods = "dsp1";
    			syscon-bootreg = <0x9 0x55c>;
    			iommus = <0xc5 0xc6>;
    			ti,rproc-standby-info = <0x4a005420>;
    			status = "okay";
    			mboxes = <0xb7 0xc7>;
    			timers = <0xc8>;
    			watchdog-timers = <0xc9>;
    			memory-region = <0xca>;
    			phandle = <0x1bf>;
    		};
    
    		i2c@48070000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48070000 0x100>;
    			interrupts = <0x0 0x33 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c1";
    			status = "okay";
    			clock-frequency = <0x61a80>;
    			phandle = <0x1c0>;
    
    			tps659038@58 {
    				status = "disabled";
    				compatible = "ti,tps659038";
    				reg = <0x58>;
    				interrupt-parent = <0xcb>;
    				interrupts = <0x0 0x8>;
    				#interrupt-cells = <0x2>;
    				interrupt-controller;
    				ti,system-power-controller;
    				ti,palmas-override-powerhold;
    				phandle = <0xcc>;
    
    				tps659038_pmic {
    					compatible = "ti,tps659038-pmic";
    
    					regulators {
    
    						smps12 {
    							regulator-name = "smps12";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x1312d0>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x6>;
    						};
    
    						smps3 {
    							regulator-name = "smps3";
    							regulator-min-microvolt = <0x149970>;
    							regulator-max-microvolt = <0x149970>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x123>;
    						};
    
    						smps45 {
    							regulator-name = "smps45";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x1312d0>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1c1>;
    						};
    
    						smps6 {
    							regulator-name = "smps6";
    							regulator-min-microvolt = <0xcf850>;
    							regulator-max-microvolt = <0x118c30>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1c2>;
    						};
    
    						smps8 {
    							regulator-name = "smps8";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1c3>;
    						};
    
    						ldo1 {
    							regulator-name = "ldo1";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-boot-on;
    							regulator-always-on;
    							phandle = <0x1c4>;
    						};
    
    						ldo2 {
    							regulator-name = "ldo2";
    							regulator-min-microvolt = <0x325aa0>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1c5>;
    						};
    
    						ldo3 {
    							regulator-name = "ldo3";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1c6>;
    						};
    
    						ldo4 {
    							regulator-name = "ldo4";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1c7>;
    						};
    
    						ldo9 {
    							regulator-name = "ldo9";
    							regulator-min-microvolt = <0x100590>;
    							regulator-max-microvolt = <0x100590>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1c8>;
    						};
    
    						ldoln {
    							regulator-name = "ldoln";
    							regulator-min-microvolt = <0x1b7740>;
    							regulator-max-microvolt = <0x1b7740>;
    							regulator-always-on;
    							regulator-boot-on;
    							phandle = <0x1c9>;
    						};
    
    						ldousb {
    							regulator-name = "ldousb";
    							regulator-min-microvolt = <0x325aa0>;
    							regulator-max-microvolt = <0x325aa0>;
    							regulator-boot-on;
    							phandle = <0x1ca>;
    						};
    
    						regen1 {
    							regulator-name = "regen1";
    							regulator-boot-on;
    							regulator-always-on;
    							phandle = <0x1cb>;
    						};
    					};
    				};
    
    				tps659038_rtc {
    					compatible = "ti,palmas-rtc";
    					interrupt-parent = <0xcc>;
    					interrupts = <0x8 0x2>;
    					wakeup-source;
    					phandle = <0x1cc>;
    				};
    
    				tps659038_pwr_button {
    					compatible = "ti,palmas-pwrbutton";
    					interrupt-parent = <0xcc>;
    					interrupts = <0x1 0x2>;
    					wakeup-source;
    					ti,palmas-long-press-seconds = <0xc>;
    					phandle = <0x1cd>;
    				};
    
    				tps659038_gpio {
    					compatible = "ti,palmas-gpio";
    					gpio-controller;
    					#gpio-cells = <0x2>;
    					phandle = <0x124>;
    				};
    
    				tps659038_usb {
    					compatible = "ti,palmas-usb-vid";
    					ti,enable-vbus-detection;
    					vbus-gpio = <0xcd 0x15 0x0>;
    					phandle = <0x1ce>;
    				};
    			};
    
    			tmp102@48 {
    				compatible = "ti,tmp102";
    				reg = <0x48>;
    				interrupt-parent = <0xce>;
    				interrupts = <0x10 0x8>;
    				#thermal-sensor-cells = <0x1>;
    				phandle = <0x120>;
    			};
    
    			tlv320aic3104@18 {
    				#sound-dai-cells = <0x0>;
    				compatible = "ti,tlv320aic3104";
    				reg = <0x18>;
    				assigned-clocks = <0x69>;
    				assigned-clock-parents = <0x94>;
    				status = "okay";
    				adc-settle-ms = <0x28>;
    				AVDD-supply = <0xcf>;
    				IOVDD-supply = <0xcf>;
    				DRVDD-supply = <0xcf>;
    				DVDD-supply = <0xd0>;
    				phandle = <0x12a>;
    			};
    
    			eeprom@50 {
    				compatible = "atmel,24c32";
    				reg = <0x50>;
    				phandle = <0x1cf>;
    			};
    		};
    
    		i2c@48072000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48072000 0x100>;
    			interrupts = <0x0 0x34 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c2";
    			status = "disabled";
    			phandle = <0x1d0>;
    		};
    
    		i2c@48060000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x48060000 0x100>;
    			interrupts = <0x0 0x38 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c3";
    			status = "okay";
    			clock-frequency = <0x61a80>;
    			phandle = <0x1d1>;
    
    			rtc@6f {
    				compatible = "microchip,mcp7941x";
    				reg = <0x6f>;
    				interrupts-extended = <0x1 0x0 0x2 0x1 0xb5 0x424>;
    				interrupt-names = "irq", "wakeup";
    				vcc-supply = <0xcf>;
    				wakeup-source;
    				phandle = <0x1d2>;
    			};
    		};
    
    		i2c@4807a000 {
    			compatible = "ti,omap4-i2c";
    			reg = <0x4807a000 0x100>;
    			interrupts = <0x0 0x39 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c4";
    			status = "disabled";
    			phandle = <0x1d3>;
    		};
    
    		i2c@4807c000 {
    			clock-frequency = <0x61a80>;
    			compatible = "ti,omap4-i2c";
    			reg = <0x4807c000 0x100>;
    			interrupts = <0x0 0x37 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "i2c5";
    			status = "okay";
    			phandle = <0x1d4>;
    
    			pixcir_ts@5c {
    				touchscreen-size-y = <0x258>;
    				touchscreen-size-x = <0x400>;
    				reset-gpio = <0xaf 0x6 0x0>;
    				reg = <0x5c>;
    				interrupts = <0x4 0x0>;
    				interrupt-parent = <0xaf>;
    				attb-gpio = <0xaf 0x4 0x0>;
    				compatible = "pixcir,pixcir_tangoc";
    			};
    		};
    
    		mmc@4809c000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x4809c000 0x400>;
    			interrupts = <0x0 0x4e 0x4>;
    			ti,hwmods = "mmc1";
    			status = "okay";
    			pbias-supply = <0xd1>;
    			max-frequency = <0xb71b000>;
    			pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
    			pinctrl-0 = <0xd2>;
    			bus-width = <0x4>;
    			pinctrl-1 = <0xd3>;
    			pinctrl-2 = <0xd4>;
    			pinctrl-3 = <0xd5>;
    			pinctrl-4 = <0xd6>;
    			pinctrl-5 = <0xd7 0xd8>;
    			pinctrl-6 = <0xd9 0xda>;
    			vmmc-supply = <0xcf>;
    			phandle = <0x1d5>;
    		};
    
    		mmc@480b4000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x480b4000 0x400>;
    			interrupts = <0x0 0x51 0x4>;
    			ti,hwmods = "mmc2";
    			status = "disabled";
    			max-frequency = <0xb71b000>;
    			sdhci-caps-mask = <0x7 0x0>;
    			mmc-hs200-1_8v;
    			mmc-ddr-1_8v;
    			pinctrl-names = "default", "hs", "ddr_1_8v";
    			pinctrl-0 = <0xdb>;
    			vmmc-supply = <0xcf>;
    			vqmmc-supply = <0xcf>;
    			bus-width = <0x8>;
    			non-removable;
    			no-1-8-v;
    			pinctrl-1 = <0xdc>;
    			pinctrl-2 = <0xdd>;
    			phandle = <0x1d6>;
    		};
    
    		mmc@480ad000 {
    			pinctrl-4 = <0x13d 0x198>;
    			pinctrl-3 = <0x13c>;
    			pinctrl-2 = <0x13b>;
    			pinctrl-1 = <0x13a>;
    			pinctrl-0 = <0x139>;
    			pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50";
    			#size-cells = <0x0>;
    			#address-cells = <0x1>;
    			non-removable;
    			keep-power-in-suspend;
    			cap-power-off-card;
    			bus-width = <0x4>;
    			vqmmc-supply = <0x247>;
    			vmmc-supply = <0x246>;
    			compatible = "ti,dra7-sdhci";
    			reg = <0x480ad000 0x400>;
    			interrupts = <0x0 0x59 0x4>;
    			ti,hwmods = "mmc3";
    			status = "disabled";
    			max-frequency = <0x3d09000>;
    			sdhci-caps-mask = <0x0 0x400000>;
    			phandle = <0x1d7>;
    
    			wlcore@2 {
    				phandle = <0x249>;
    				interrupts = <0x7 0x1>;
    				interrupt-parent = <0x19e>;
    				reg = <0x2>;
    				compatible = "ti,wl1835";
    			};
    		};
    
    		mmc@480d1000 {
    			compatible = "ti,dra7-sdhci";
    			reg = <0x480d1000 0x400>;
    			interrupts = <0x0 0x5b 0x4>;
    			ti,hwmods = "mmc4";
    			status = "disabled";
    			max-frequency = <0xb71b000>;
    			sdhci-caps-mask = <0x0 0x400000>;
    			phandle = <0x1d8>;
    		};
    
    		mmu@40d01000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x40d01000 0x100>;
    			interrupts = <0x0 0x17 0x4>;
    			ti,hwmods = "mmu0_dsp1";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xde 0x0>;
    			phandle = <0xc5>;
    		};
    
    		mmu@40d02000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x40d02000 0x100>;
    			interrupts = <0x0 0x91 0x4>;
    			ti,hwmods = "mmu1_dsp1";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0xde 0x1>;
    			phandle = <0xc6>;
    		};
    
    		mmu@58882000 {
    			compatible = "ti,dra7-iommu";
    			reg = <0x58882000 0x100>;
    			interrupts = <0x0 0x18b 0x4>;
    			ti,hwmods = "mmu_ipu1";
    			#iommu-cells = <0x0>;
    			ti,iommu-bus-err-back;
    			phandle = <0xb6>;
    		};
    
    		mmu@55082000 {
    			compatible = "ti,dra7-iommu";
    			reg = <0x55082000 0x100>;
    			interrupts = <0x0 0x18c 0x4>;
    			ti,hwmods = "mmu_ipu2";
    			#iommu-cells = <0x0>;
    			ti,iommu-bus-err-back;
    			phandle = <0xbe>;
    		};
    
    		pruss_soc_bus@4b226004 {
    			compatible = "ti,am5728-pruss-soc-bus";
    			reg = <0x4b226004 0x4>;
    			ti,hwmods = "pruss1";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4b200000 0x80000>;
    			status = "okay";
    			phandle = <0x1d9>;
    
    			pruss@0 {
    				compatible = "ti,am5728-pruss";
    				reg = <0x0 0x80000>;
    				interrupts = <0x0 0xba 0x4 0x0 0xbb 0x4 0x0 0xbc 0x4 0x0 0xbd 0x4 0x0 0xbe 0x4 0x0 0xbf 0x4 0x0 0xc0 0x4 0x0 0xc1 0x4>;
    				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges;
    				status = "okay";
    				phandle = <0x1da>;
    
    				memories@0 {
    					reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x8000 0x2e000 0x31c 0x30000 0x60>;
    					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
    					phandle = <0x1db>;
    				};
    
    				cfg@26000 {
    					compatible = "syscon";
    					reg = <0x26000 0x2000>;
    					phandle = <0x1dc>;
    				};
    
    				mii_rt@32000 {
    					compatible = "syscon";
    					reg = <0x32000 0x58>;
    					phandle = <0x1dd>;
    				};
    
    				intc@20000 {
    					compatible = "ti,am5728-pruss-intc";
    					reg = <0x20000 0x2000>;
    					reg-names = "intc";
    					interrupt-controller;
    					#interrupt-cells = <0x1>;
    					phandle = <0xdf>;
    				};
    
    				pru@34000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x34000 0x3000 0x22000 0x400 0x22400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru1_0-fw";
    					interrupt-parent = <0xdf>;
    					interrupts = <0x10 0x11>;
    					interrupt-names = "vring", "kick";
    					phandle = <0x1de>;
    				};
    
    				pru@38000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x38000 0x3000 0x24000 0x400 0x24400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru1_1-fw";
    					interrupt-parent = <0xdf>;
    					interrupts = <0x12 0x13>;
    					interrupt-names = "vring", "kick";
    					phandle = <0x1df>;
    				};
    
    				mdio@32400 {
    					compatible = "ti,davinci_mdio";
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					clocks = <0xe0>;
    					clock-names = "fck";
    					bus_freq = <0xf4240>;
    					reg = <0x32400 0x90>;
    					status = "disabled";
    					phandle = <0x1e0>;
    				};
    			};
    		};
    
    		pruss_soc_bus@4b2a6004 {
    			compatible = "ti,am5728-pruss-soc-bus";
    			reg = <0x4b2a6004 0x4>;
    			ti,hwmods = "pruss2";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges = <0x0 0x4b280000 0x80000>;
    			status = "okay";
    			phandle = <0x1e1>;
    
    			pruss@0 {
    				compatible = "ti,am5728-pruss";
    				reg = <0x0 0x80000>;
    				interrupts = <0x0 0xc4 0x4 0x0 0xc5 0x4 0x0 0xc6 0x4 0x0 0xc7 0x4 0x0 0xc8 0x4 0x0 0xc9 0x4 0x0 0xca 0x4 0x0 0xcb 0x4>;
    				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
    				#address-cells = <0x1>;
    				#size-cells = <0x1>;
    				ranges;
    				status = "okay";
    				phandle = <0x1e2>;
    
    				memories@0 {
    					reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x8000 0x2e000 0x31c 0x30000 0x60>;
    					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
    					phandle = <0x1e3>;
    				};
    
    				cfg@26000 {
    					compatible = "syscon";
    					reg = <0x26000 0x2000>;
    					phandle = <0x1e4>;
    				};
    
    				iep@2e000 {
    					compatible = "syscon";
    					reg = <0x2e000 0x31c>;
    					phandle = <0x1e5>;
    				};
    
    				mii_rt@32000 {
    					compatible = "syscon";
    					reg = <0x32000 0x58>;
    					phandle = <0x1e6>;
    				};
    
    				intc@20000 {
    					compatible = "ti,am5728-pruss-intc";
    					reg = <0x20000 0x2000>;
    					reg-names = "intc";
    					interrupt-controller;
    					#interrupt-cells = <0x1>;
    					phandle = <0xe1>;
    				};
    
    				pru@34000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x34000 0x3000 0x22000 0x400 0x22400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru2_0-fw";
    					interrupt-parent = <0xe1>;
    					interrupts = <0x10 0x11>;
    					interrupt-names = "vring", "kick";
    					phandle = <0x1e7>;
    				};
    
    				pru@38000 {
    					compatible = "ti,am5728-pru";
    					reg = <0x38000 0x3000 0x24000 0x400 0x24400 0x100>;
    					reg-names = "iram", "control", "debug";
    					firmware-name = "am57xx-pru2_1-fw";
    					interrupt-parent = <0xe1>;
    					interrupts = <0x12 0x13>;
    					interrupt-names = "vring", "kick";
    					phandle = <0x1e8>;
    				};
    
    				mdio@32400 {
    					compatible = "ti,davinci_mdio";
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					clocks = <0xe0>;
    					clock-names = "fck";
    					bus_freq = <0xf4240>;
    					reg = <0x32400 0x90>;
    					status = "disabled";
    					phandle = <0x1e9>;
    				};
    			};
    		};
    
    		regulator-abb-mpu {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_mpu";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07ddc 0x4 0x4ae07de0 0x4 0x4ae06014 0x4 0x4a003b20 0xc 0x4ae0c158 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x80>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x102ca0 0x0 0x0 0x0 0x2000000 0x1f00000 0x11b340 0x0 0x4 0x0 0x2000000 0x1f00000 0x127690 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x5>;
    		};
    
    		regulator-abb-ivahd {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_ivahd";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07e34 0x4 0x4ae07e24 0x4 0x4ae06010 0x4 0x4a0025cc 0xc 0x4a002470 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x40000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x1ea>;
    		};
    
    		regulator-abb-dspeve {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_dspeve";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07e30 0x4 0x4ae07e20 0x4 0x4ae06010 0x4 0x4a0025e0 0xc 0x4a00246c 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x20000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x1eb>;
    		};
    
    		regulator-abb-gpu {
    			compatible = "ti,abb-v3";
    			regulator-name = "abb_gpu";
    			#address-cells = <0x0>;
    			#size-cells = <0x0>;
    			clocks = <0x11>;
    			ti,settling-time = <0x32>;
    			ti,clock-cycles = <0x10>;
    			reg = <0x4ae07de4 0x4 0x4ae07de8 0x4 0x4ae06010 0x4 0x4a003b08 0xc 0x4ae0c154 0x4>;
    			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
    			ti,tranxdone-status-mask = <0x10000000>;
    			ti,ldovbb-override-mask = <0x400>;
    			ti,ldovbb-vset-mask = <0x1f>;
    			ti,abb_info = <0x10a1d0 0x0 0x0 0x0 0x2000000 0x1f00000 0x127690 0x0 0x4 0x0 0x2000000 0x1f00000 0x138800 0x0 0x8 0x0 0x2000000 0x1f00000>;
    			phandle = <0x1ec>;
    		};
    
    		spi@48098000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x48098000 0x200>;
    			interrupts = <0x0 0x3c 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi1";
    			ti,spi-num-cs = <0x4>;
    			dmas = <0xb4 0x23 0xb4 0x24 0xb4 0x25 0xb4 0x26 0xb4 0x27 0xb4 0x28 0xb4 0x29 0xb4 0x2a>;
    			dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3";
    			status = "disabled";
    			phandle = <0x1ed>;
    		};
    
    		spi@4809a000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x4809a000 0x200>;
    			interrupts = <0x0 0x3d 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi2";
    			ti,spi-num-cs = <0x2>;
    			dmas = <0xb4 0x2b 0xb4 0x2c 0xb4 0x2d 0xb4 0x2e>;
    			dma-names = "tx0", "rx0", "tx1", "rx1";
    			status = "disabled";
    			phandle = <0x1ee>;
    		};
    
    		spi@480b8000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x480b8000 0x200>;
    			interrupts = <0x0 0x56 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi3";
    			ti,spi-num-cs = <0x2>;
    			dmas = <0xb4 0xf 0xb4 0x10>;
    			dma-names = "tx0", "rx0";
    			status = "disabled";
    			phandle = <0x1ef>;
    		};
    
    		spi@480ba000 {
    			compatible = "ti,omap4-mcspi";
    			reg = <0x480ba000 0x200>;
    			interrupts = <0x0 0x2b 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "mcspi4";
    			ti,spi-num-cs = <0x1>;
    			dmas = <0xb4 0x46 0xb4 0x47>;
    			dma-names = "tx0", "rx0";
    			status = "disabled";
    			phandle = <0x1f0>;
    		};
    
    		qspi@4b300000 {
    			compatible = "ti,dra7xxx-qspi";
    			reg = <0x4b300000 0x100 0x5c000000 0x4000000>;
    			reg-names = "qspi_base", "qspi_mmap";
    			syscon-chipselects = <0x9 0x558>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			ti,hwmods = "qspi";
    			clocks = <0xe2>;
    			clock-names = "fck";
    			num-cs = <0x4>;
    			interrupts = <0x0 0x157 0x4>;
    			status = "disabled";
    			phandle = <0x1f1>;
    		};
    
    		ocp2scp@4a090000 {
    			compatible = "ti,omap-ocp2scp";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x4a090000 0x20>;
    			ti,hwmods = "ocp2scp3";
    
    			phy@4A096000 {
    				compatible = "ti,phy-pipe3-sata";
    				reg = <0x4a096000 0x80 0x4a096400 0x64 0x4a096800 0x40>;
    				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    				syscon-phy-power = <0x9 0x374>;
    				clocks = <0x11 0xe3>;
    				clock-names = "sysclk", "refclk";
    				syscon-pllreset = <0x9 0x3fc>;
    				#phy-cells = <0x0>;
    				phandle = <0xea>;
    			};
    
    			pciephy@4a094000 {
    				compatible = "ti,phy-pipe3-pcie";
    				reg = <0x4a094000 0x80 0x4a094400 0x64>;
    				reg-names = "phy_rx", "phy_tx";
    				syscon-phy-power = <0xac 0x1c>;
    				syscon-pcs = <0xac 0x10>;
    				clocks = <0x59 0x5a 0xe4 0xe5 0xe6 0x5e 0x11>;
    				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
    				#phy-cells = <0x0>;
    				phandle = <0xab>;
    			};
    
    			pciephy@4a095000 {
    				compatible = "ti,phy-pipe3-pcie";
    				reg = <0x4a095000 0x80 0x4a095400 0x64>;
    				reg-names = "phy_rx", "phy_tx";
    				syscon-phy-power = <0xac 0x20>;
    				syscon-pcs = <0xac 0x10>;
    				clocks = <0x59 0x5a 0xe7 0xe8 0xe9 0x5e 0x11>;
    				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
    				#phy-cells = <0x0>;
    				status = "disabled";
    				phandle = <0xb0>;
    			};
    		};
    
    		sata@4a141100 {
    			compatible = "snps,dwc-ahci";
    			reg = <0x4a140000 0x1100 0x4a141100 0x7>;
    			interrupts = <0x0 0x31 0x4>;
    			phys = <0xea>;
    			phy-names = "sata-phy";
    			clocks = <0xe3>;
    			ti,hwmods = "sata";
    			ports-implemented = <0x1>;
    			status = "okay";
    			phandle = <0x1f2>;
    		};
    
    		rtc@48838000 {
    			compatible = "ti,am3352-rtc";
    			reg = <0x48838000 0x100>;
    			interrupts = <0x0 0xd9 0x4 0x0 0xd9 0x4>;
    			ti,hwmods = "rtcss";
    			clocks = <0x51>;
    			phandle = <0x1f3>;
    		};
    
    		ocp2scp@4a080000 {
    			compatible = "ti,omap-ocp2scp";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x4a080000 0x20>;
    			ti,hwmods = "ocp2scp1";
    
    			phy@4a084000 {
    				compatible = "ti,dra7x-usb2", "ti,omap-usb2";
    				reg = <0x4a084000 0x400>;
    				syscon-phy-power = <0x9 0x300>;
    				clocks = <0xeb 0xec>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				phandle = <0xf0>;
    			};
    
    			phy@4a085000 {
    				compatible = "ti,dra7x-usb2-phy2", "ti,omap-usb2";
    				reg = <0x4a085000 0x400>;
    				syscon-phy-power = <0x9 0xe74>;
    				clocks = <0xed 0xee>;
    				clock-names = "wkupclk", "refclk";
    				#phy-cells = <0x0>;
    				phandle = <0xf2>;
    			};
    
    			phy@4a084400 {
    				compatible = "ti,omap-usb3";
    				reg = <0x4a084400 0x80 0x4a084800 0x64 0x4a084c00 0x40>;
    				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
    				syscon-phy-power = <0x9 0x370>;
    				clocks = <0xef 0x11 0xec>;
    				clock-names = "wkupclk", "sysclk", "refclk";
    				#phy-cells = <0x0>;
    				phandle = <0xf1>;
    			};
    		};
    
    		omap_dwc3_1@48880000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss1";
    			reg = <0x48880000 0x10000>;
    			interrupts = <0x0 0x48 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			phandle = <0x1f4>;
    
    			usb@48890000 {
    				compatible = "snps,dwc3";
    				reg = <0x48890000 0x17000>;
    				interrupts = <0x0 0x47 0x4 0x0 0x47 0x4 0x0 0x48 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				phys = <0xf0 0xf1>;
    				phy-names = "usb2-phy", "usb3-phy";
    				maximum-speed = "super-speed";
    				dr_mode = "host";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				phandle = <0x1f5>;
    			};
    		};
    
    		omap_dwc3_2@488c0000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss2";
    			reg = <0x488c0000 0x10000>;
    			interrupts = <0x0 0x57 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			phandle = <0x1f6>;
    
    			usb@488d0000 {
    				compatible = "snps,dwc3";
    				reg = <0x488d0000 0x17000>;
    				interrupts = <0x0 0x49 0x4 0x0 0x49 0x4 0x0 0x57 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				phys = <0xf2>;
    				phy-names = "usb2-phy";
    				maximum-speed = "high-speed";
    				dr_mode = "host";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				snps,dis_metastability_quirk;
    				phandle = <0x1f7>;
    			};
    		};
    
    		omap_dwc3_3@48900000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss3";
    			reg = <0x48900000 0x10000>;
    			interrupts = <0x0 0x158 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			status = "disabled";
    			phandle = <0x1f8>;
    
    			usb@48910000 {
    				compatible = "snps,dwc3";
    				reg = <0x48910000 0x17000>;
    				interrupts = <0x0 0x58 0x4 0x0 0x58 0x4 0x0 0x158 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				maximum-speed = "high-speed";
    				dr_mode = "otg";
    				snps,dis_u3_susphy_quirk;
    				snps,dis_u2_susphy_quirk;
    				phandle = <0x1f9>;
    			};
    		};
    
    		elm@48078000 {
    			compatible = "ti,am3352-elm";
    			reg = <0x48078000 0xfc0>;
    			interrupts = <0x0 0x1 0x4>;
    			ti,hwmods = "elm";
    			status = "disabled";
    			phandle = <0x1fa>;
    		};
    
    		gpmc@50000000 {
    			compatible = "ti,am3352-gpmc";
    			ti,hwmods = "gpmc";
    			reg = <0x50000000 0x37c>;
    			interrupts = <0x0 0xf 0x4>;
    			dmas = <0xf3 0x4 0x0>;
    			dma-names = "rxtx";
    			gpmc,num-cs = <0x8>;
    			gpmc,num-waitpins = <0x2>;
    			#address-cells = <0x2>;
    			#size-cells = <0x1>;
    			interrupt-controller;
    			#interrupt-cells = <0x2>;
    			gpio-controller;
    			#gpio-cells = <0x2>;
    			status = "disabled";
    			phandle = <0x1fb>;
    		};
    
    		atl@4843c000 {
    			compatible = "ti,dra7-atl";
    			reg = <0x4843c000 0x3ff>;
    			ti,hwmods = "atl";
    			ti,provided-clocks = <0x44 0x43 0x42 0x41>;
    			clocks = <0x10>;
    			clock-names = "fck";
    			status = "disabled";
    			phandle = <0x1fc>;
    		};
    
    		mcasp@48460000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp1";
    			reg = <0x48460000 0x2000 0x45800000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x68 0x4 0x0 0x67 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xf3 0x81 0x1 0xf3 0x80 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xf4 0xf5 0xf6>;
    			clock-names = "fck", "ahclkx", "ahclkr";
    			status = "disabled";
    			phandle = <0x1fd>;
    		};
    
    		mcasp@48464000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp2";
    			reg = <0x48464000 0x2000 0x45c00000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x95 0x4 0x0 0x94 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xf3 0x83 0x1 0xf3 0x82 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xf7 0xf8 0xf9>;
    			clock-names = "fck", "ahclkx", "ahclkr";
    			status = "disabled";
    			phandle = <0x1fe>;
    		};
    
    		mcasp@48468000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp3";
    			reg = <0x48468000 0x2000 0x46000000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x97 0x4 0x0 0x96 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xf3 0x85 0x1 0xf3 0x84 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xfa 0x78>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			#sound-dai-cells = <0x0>;
    			assigned-clocks = <0x78>;
    			assigned-clock-parents = <0x45>;
    			op-mode = <0x0>;
    			tdm-slots = <0x2>;
    			serial-dir = <0x1 0x2 0x0 0x0>;
    			tx-num-evt = <0x20>;
    			rx-num-evt = <0x20>;
    			phandle = <0x129>;
    		};
    
    		mcasp@4846c000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp4";
    			reg = <0x4846c000 0x2000 0x48436000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x99 0x4 0x0 0x98 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xf3 0x87 0x1 0xf3 0x86 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xfb 0xfc>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x1ff>;
    		};
    
    		mcasp@48470000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp5";
    			reg = <0x48470000 0x2000 0x4843a000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9b 0x4 0x0 0x9a 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xf3 0x89 0x1 0xf3 0x88 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xfd 0xfe>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x200>;
    		};
    
    		mcasp@48474000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp6";
    			reg = <0x48474000 0x2000 0x4844c000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9d 0x4 0x0 0x9c 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xf3 0x8b 0x1 0xf3 0x8a 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0xff 0x100>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x201>;
    		};
    
    		mcasp@48478000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp7";
    			reg = <0x48478000 0x2000 0x48450000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0x9f 0x4 0x0 0x9e 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xf3 0x8d 0x1 0xf3 0x8c 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x101 0x102>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x202>;
    		};
    
    		mcasp@4847c000 {
    			compatible = "ti,dra7-mcasp-audio";
    			ti,hwmods = "mcasp8";
    			reg = <0x4847c000 0x2000 0x48454000 0x1000>;
    			reg-names = "mpu", "dat";
    			interrupts = <0x0 0xa1 0x4 0x0 0xa0 0x4>;
    			interrupt-names = "tx", "rx";
    			dmas = <0xf3 0x8f 0x1 0xf3 0x8e 0x1>;
    			dma-names = "tx", "rx";
    			clocks = <0x103 0x104>;
    			clock-names = "fck", "ahclkx";
    			status = "disabled";
    			phandle = <0x203>;
    		};
    
    		crossbar@4a002a48 {
    			compatible = "ti,irq-crossbar";
    			reg = <0x4a002a48 0x130>;
    			interrupt-controller;
    			interrupt-parent = <0x8>;
    			#interrupt-cells = <0x3>;
    			ti,max-irqs = <0xa0>;
    			ti,max-crossbar-sources = <0x190>;
    			ti,reg-size = <0x2>;
    			ti,irqs-reserved = <0x0 0x1 0x2 0x3 0x5 0x6 0x83 0x84>;
    			ti,irqs-skip = <0xa 0x85 0x8b 0x8c>;
    			ti,irqs-safe-map = <0x0>;
    			phandle = <0x1>;
    		};
    
    		ethernet@48484000 {
    			compatible = "ti,dra7-cpsw", "ti,cpsw";
    			ti,hwmods = "gmac";
    			clocks = <0x105 0x106>;
    			clock-names = "fck", "cpts";
    			cpdma_channels = <0x8>;
    			ale_entries = <0x400>;
    			bd_ram_size = <0x2000>;
    			mac_control = <0x20>;
    			slaves = <0x2>;
    			active_slave = <0x1>;
    			cpts_clock_mult = <0x784cfe14>;
    			cpts_clock_shift = <0x1d>;
    			reg = <0x48484000 0x1000 0x48485200 0x2e00>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ti,no-idle;
    			interrupts = <0x0 0x14e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4>;
    			ranges;
    			syscon = <0x9>;
    			status = "okay";
    			dual_emac;
    			phandle = <0x204>;
    
    			mdio@48485000 {
    				compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				ti,hwmods = "davinci_mdio";
    				bus_freq = <0xf4240>;
    				reg = <0x48485000 0x100>;
    				phandle = <0x205>;
    
    				ethernet-phy@0 {
    					reg = <0x0>;
    					phandle = <0x107>;
    				};
    
    				ethernet-phy@2 {
    					reg = <0x2>;
    					phandle = <0x108>;
    				};
    			};
    
    			slave@48480200 {
    				mac-address = [00 00 00 00 00 00];
    				phy-handle = <0x107>;
    				phy-mode = "rgmii";
    				dual_emac_res_vlan = <0x1>;
    				phandle = <0x206>;
    			};
    
    			slave@48480300 {
    				mac-address = [00 00 00 00 00 00];
    				phy-handle = <0x108>;
    				phy-mode = "rgmii";
    				dual_emac_res_vlan = <0x2>;
    				phandle = <0x207>;
    			};
    
    			cpsw-phy-sel@4a002554 {
    				compatible = "ti,dra7xx-cpsw-phy-sel";
    				reg = <0x4a002554 0x4>;
    				reg-names = "gmii-sel";
    				phandle = <0x208>;
    			};
    		};
    
    		can@4ae3c000 {
    			compatible = "ti,dra7-d_can";
    			ti,hwmods = "dcan1";
    			reg = <0x4ae3c000 0x2000>;
    			syscon-raminit = <0x9 0x558 0x0>;
    			interrupts = <0x0 0xde 0x4>;
    			clocks = <0x109>;
    			status = "disabled";
    			phandle = <0x209>;
    		};
    
    		can@48480000 {
    			compatible = "ti,dra7-d_can";
    			ti,hwmods = "dcan2";
    			reg = <0x48480000 0x2000>;
    			syscon-raminit = <0x9 0x558 0x1>;
    			interrupts = <0x0 0xe1 0x4>;
    			clocks = <0x11>;
    			status = "disabled";
    			phandle = <0x20a>;
    		};
    
    		gpu@56000000 {
    			compatible = "ti,dra7-sgx544", "img,sgx544";
    			reg = <0x56000000 0x10000>;
    			reg-names = "gpu_ocp_base";
    			interrupts = <0x0 0x10 0x4>;
    			ti,hwmods = "gpu";
    			clocks = <0xa 0x75 0x76>;
    			clock-names = "iclk", "fclk1", "fclk2";
    			status = "ok";
    			phandle = <0x20b>;
    		};
    
    		bb2d@59000000 {
    			compatible = "ti,dra7-bb2d";
    			reg = <0x59000000 0x700>;
    			interrupts = <0x0 0x78 0x4>;
    			ti,hwmods = "bb2d";
    			clocks = <0x10a>;
    			clock-names = "fclk";
    			status = "okay";
    			phandle = <0x20c>;
    		};
    
    		dss@58000000 {
    			compatible = "ti,dra7-dss";
    			status = "ok";
    			ti,hwmods = "dss_core";
    			syscon-pll-ctrl = <0x9 0x538>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			ranges;
    			reg = <0x58000000 0x80 0x58004054 0x4 0x58004300 0x20 0x58009054 0x4 0x58009300 0x20>;
    			reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2";
    			clocks = <0x10b 0x10c 0x10d>;
    			clock-names = "fck", "video1_clk", "video2_clk";
    			phandle = <0x20d>;
    
    			dispc@58001000 {
    				compatible = "ti,dra7-dispc";
    				reg = <0x58001000 0x1000>;
    				interrupts = <0x0 0x14 0x4>;
    				ti,hwmods = "dss_dispc";
    				clocks = <0x10b>;
    				clock-names = "fck";
    				syscon-pol = <0x9 0x534>;
    			};
    
    			encoder@58060000 {
    				compatible = "ti,dra7-hdmi";
    				reg = <0x58040000 0x200 0x58040200 0x80 0x58040300 0x80 0x58060000 0x19000>;
    				reg-names = "wp", "pll", "phy", "core";
    				interrupts = <0x0 0x60 0x4>;
    				status = "ok";
    				ti,hwmods = "dss_hdmi";
    				clocks = <0x10e 0x10f>;
    				clock-names = "fck", "sys_clk";
    				dmas = <0xb4 0x4c>;
    				dma-names = "audio_tx";
    				phandle = <0x20e>;
    
    				port {
    
    					endpoint {
    						remote-endpoint = <0x110>;
    						phandle = <0x126>;
    					};
    				};
    			};
    		};
    
    		epwmss@4843e000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x4843e000 0x30>;
    			ti,hwmods = "epwmss0";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    			phandle = <0x20f>;
    
    			pwm@4843e200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x4843e200 0x80>;
    				clocks = <0x111 0xb>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    				phandle = <0x210>;
    			};
    
    			ecap@4843e100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x4843e100 0x80>;
    				clocks = <0xb>;
    				clock-names = "fck";
    				status = "disabled";
    				phandle = <0x211>;
    			};
    		};
    
    		epwmss@48440000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48440000 0x30>;
    			ti,hwmods = "epwmss1";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "okay";
    			ranges;
    			phandle = <0x212>;
    
    			pwm@48440200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48440200 0x80>;
    				clocks = <0x112 0xb>;
    				clock-names = "tbclk", "fck";
    				status = "okay";
    				phandle = <0x213>;
    			};
    
    			ecap@48440100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48440100 0x80>;
    				clocks = <0xb>;
    				clock-names = "fck";
    				status = "disabled";
    				phandle = <0x214>;
    			};
    		};
    
    		epwmss@48442000 {
    			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
    			reg = <0x48442000 0x30>;
    			ti,hwmods = "epwmss2";
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			status = "disabled";
    			ranges;
    			phandle = <0x215>;
    
    			pwm@48442200 {
    				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
    				#pwm-cells = <0x3>;
    				reg = <0x48442200 0x80>;
    				clocks = <0x113 0xb>;
    				clock-names = "tbclk", "fck";
    				status = "disabled";
    				phandle = <0x216>;
    			};
    
    			ecap@48442100 {
    				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
    				#pwm-cells = <0x3>;
    				reg = <0x48442100 0x80>;
    				clocks = <0xb>;
    				clock-names = "fck";
    				status = "disabled";
    				phandle = <0x217>;
    			};
    		};
    
    		aes@4b500000 {
    			compatible = "ti,omap4-aes";
    			ti,hwmods = "aes1";
    			reg = <0x4b500000 0xa0>;
    			interrupts = <0x0 0x50 0x4>;
    			dmas = <0xf3 0x6f 0x0 0xf3 0x6e 0x0>;
    			dma-names = "tx", "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    			phandle = <0x218>;
    		};
    
    		aes@4b700000 {
    			compatible = "ti,omap4-aes";
    			ti,hwmods = "aes2";
    			reg = <0x4b700000 0xa0>;
    			interrupts = <0x0 0x3b 0x4>;
    			dmas = <0xf3 0x72 0x0 0xf3 0x71 0x0>;
    			dma-names = "tx", "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    			phandle = <0x219>;
    		};
    
    		des@480a5000 {
    			compatible = "ti,omap4-des";
    			ti,hwmods = "des";
    			reg = <0x480a5000 0xa0>;
    			interrupts = <0x0 0x4d 0x4>;
    			dmas = <0xb4 0x75 0xb4 0x74>;
    			dma-names = "tx", "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    			phandle = <0x21a>;
    		};
    
    		sham@53100000 {
    			compatible = "ti,omap5-sham";
    			ti,hwmods = "sham";
    			reg = <0x4b101000 0x300>;
    			interrupts = <0x0 0x2e 0x4>;
    			dmas = <0xf3 0x77 0x0>;
    			dma-names = "rx";
    			clocks = <0xa>;
    			clock-names = "fck";
    			phandle = <0x21b>;
    		};
    
    		rng@48090000 {
    			compatible = "ti,omap4-rng";
    			ti,hwmods = "rng";
    			reg = <0x48090000 0x2000>;
    			interrupts = <0x0 0x2f 0x4>;
    			clocks = <0xa>;
    			clock-names = "fck";
    			phandle = <0x21c>;
    		};
    
    		opp-supply@4a003b20 {
    			compatible = "ti,omap5-opp-supply";
    			reg = <0x4a003b20 0xc>;
    			ti,efuse-settings = <0x102ca0 0x0 0x11b340 0x4 0x127690 0x8>;
    			ti,absolute-max-voltage-uv = <0x16e360>;
    			phandle = <0x21d>;
    		};
    
    		vpe {
    			compatible = "ti,vpe";
    			ti,hwmods = "vpe";
    			clocks = <0x81>;
    			clock-names = "fck";
    			reg = <0x489d0000 0x120 0x489d0300 0x20 0x489d0400 0x20 0x489d0500 0x20 0x489d0600 0x3c 0x489d0700 0x80 0x489d5700 0x18 0x489dd000 0x400>;
    			reg-names = "vpe_top", "vpe_chr_us0", "vpe_chr_us1", "vpe_chr_us2", "vpe_dei", "sc", "csc", "vpdma";
    			interrupts = <0x0 0x162 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    		};
    
    		vip@0x48970000 {
    			compatible = "ti,vip1";
    			reg = <0x48970000 0x114 0x48975500 0xd8 0x48975700 0x18 0x48975800 0x80 0x48975a00 0xd8 0x48975c00 0x18 0x48975d00 0x80 0x4897d000 0x400>;
    			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
    			ti,hwmods = "vip1";
    			interrupts = <0x0 0x15f 0x4 0x0 0x188 0x4>;
    			syscon-pol = <0x9 0x534>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0x21e>;
    
    			port@0 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x0>;
    				status = "disabled";
    				phandle = <0x21f>;
    			};
    
    			port@1 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x1>;
    				status = "disabled";
    				phandle = <0x220>;
    			};
    
    			port@2 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x2>;
    				status = "disabled";
    				phandle = <0x221>;
    			};
    
    			port@3 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x3>;
    				status = "disabled";
    				phandle = <0x222>;
    			};
    		};
    
    		dsp_system@41500000 {
    			compatible = "syscon";
    			reg = <0x41500000 0x100>;
    			phandle = <0x114>;
    		};
    
    		omap_dwc3_4@48940000 {
    			compatible = "ti,dwc3";
    			ti,hwmods = "usb_otg_ss4";
    			reg = <0x48940000 0x10000>;
    			interrupts = <0x0 0x15a 0x4>;
    			#address-cells = <0x1>;
    			#size-cells = <0x1>;
    			utmi-mode = <0x2>;
    			ranges;
    			status = "disabled";
    			phandle = <0x223>;
    
    			usb@48950000 {
    				compatible = "snps,dwc3";
    				reg = <0x48950000 0x17000>;
    				interrupts = <0x0 0x159 0x4 0x0 0x159 0x4 0x0 0x15a 0x4>;
    				interrupt-names = "peripheral", "host", "otg";
    				maximum-speed = "high-speed";
    				dr_mode = "otg";
    				phandle = <0x224>;
    			};
    		};
    
    		mmu@41501000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x41501000 0x100>;
    			interrupts = <0x0 0x92 0x4>;
    			ti,hwmods = "mmu0_dsp2";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0x114 0x0>;
    			phandle = <0x115>;
    		};
    
    		mmu@41502000 {
    			compatible = "ti,dra7-dsp-iommu";
    			reg = <0x41502000 0x100>;
    			interrupts = <0x0 0x93 0x4>;
    			ti,hwmods = "mmu1_dsp2";
    			#iommu-cells = <0x0>;
    			ti,syscon-mmuconfig = <0x114 0x1>;
    			phandle = <0x116>;
    		};
    
    		dsp@41000000 {
    			compatible = "ti,dra7-dsp";
    			reg = <0x41000000 0x48000 0x41600000 0x8000 0x41700000 0x8000>;
    			reg-names = "l2ram", "l1pram", "l1dram";
    			ti,hwmods = "dsp2";
    			syscon-bootreg = <0x9 0x560>;
    			iommus = <0x115 0x116>;
    			ti,rproc-standby-info = <0x4a005620>;
    			status = "okay";
    			mboxes = <0xbf 0x117>;
    			timers = <0x118>;
    			watchdog-timers = <0x119>;
    			memory-region = <0x11a>;
    			phandle = <0x225>;
    		};
    
    		vip@0x48990000 {
    			compatible = "ti,vip2";
    			reg = <0x48990000 0x114 0x48995500 0xd8 0x48995700 0x18 0x48995800 0x80 0x48995a00 0xd8 0x48995c00 0x18 0x48995d00 0x80 0x4899d000 0x400>;
    			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
    			ti,hwmods = "vip2";
    			interrupts = <0x0 0x160 0x4 0x0 0x189 0x4>;
    			syscon-pol = <0x9 0x534>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0x226>;
    
    			port@0 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x0>;
    				status = "disabled";
    				phandle = <0x227>;
    			};
    
    			port@1 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x1>;
    				status = "disabled";
    				phandle = <0x228>;
    			};
    
    			port@2 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x2>;
    				status = "disabled";
    				phandle = <0x229>;
    			};
    
    			port@3 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x3>;
    				status = "disabled";
    				phandle = <0x22a>;
    			};
    		};
    
    		vip@0x489b0000 {
    			compatible = "ti,vip3";
    			reg = <0x489b0000 0x114 0x489b5500 0xd8 0x489b5700 0x18 0x489b5800 0x80 0x489b5a00 0xd8 0x489b5c00 0x18 0x489b5d00 0x80 0x489bd000 0x400>;
    			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
    			ti,hwmods = "vip3";
    			interrupts = <0x0 0x161 0x4 0x0 0x18a 0x4>;
    			syscon-pol = <0x9 0x534>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			status = "disabled";
    			phandle = <0x22b>;
    
    			port@0 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x0>;
    				status = "disabled";
    				phandle = <0x22c>;
    			};
    
    			port@1 {
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x1>;
    				status = "disabled";
    				phandle = <0x22d>;
    			};
    		};
    	};
    
    	thermal-zones {
    		phandle = <0x22e>;
    
    		cpu_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0x11b 0x0>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x22f>;
    
    			trips {
    				phandle = <0x230>;
    
    				cpu_alert {
    					temperature = <0x13880>;
    					hysteresis = <0x7d0>;
    					type = "passive";
    					phandle = <0x11c>;
    				};
    
    				cpu_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x231>;
    				};
    
    				cpu_alert1 {
    					temperature = <0xc350>;
    					hysteresis = <0x7d0>;
    					type = "active";
    					phandle = <0x11e>;
    				};
    			};
    
    			cooling-maps {
    				phandle = <0x232>;
    
    				map0 {
    					trip = <0x11c>;
    					cooling-device = <0x11d 0xffffffff 0xffffffff>;
    				};
    
    				map1 {
    					trip = <0x11e>;
    					cooling-device = <0x11f 0xffffffff 0xffffffff>;
    				};
    			};
    		};
    
    		gpu_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0x11b 0x1>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x233>;
    
    			trips {
    
    				gpu_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x234>;
    				};
    			};
    		};
    
    		core_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0x11b 0x2>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x235>;
    
    			trips {
    
    				core_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x236>;
    				};
    			};
    		};
    
    		dspeve_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0x11b 0x3>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x237>;
    
    			trips {
    
    				dspeve_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x238>;
    				};
    			};
    		};
    
    		iva_thermal {
    			polling-delay-passive = <0xfa>;
    			polling-delay = <0x1f4>;
    			thermal-sensors = <0x11b 0x4>;
    			coefficients = <0x0 0x7d0>;
    			phandle = <0x239>;
    
    			trips {
    
    				iva_crit {
    					temperature = <0x15f90>;
    					hysteresis = <0x7d0>;
    					type = "critical";
    					phandle = <0x23a>;
    				};
    			};
    		};
    
    		board_thermal {
    			polling-delay-passive = <0x4e2>;
    			polling-delay = <0x5dc>;
    			thermal-sensors = <0x120 0x0>;
    			phandle = <0x23b>;
    
    			trips {
    				phandle = <0x23c>;
    
    				board_alert {
    					temperature = <0x9c40>;
    					hysteresis = <0x7d0>;
    					type = "active";
    					phandle = <0x121>;
    				};
    
    				board_crit {
    					temperature = <0x19a28>;
    					hysteresis = <0x0>;
    					type = "critical";
    					phandle = <0x23d>;
    				};
    			};
    
    			cooling-maps {
    				phandle = <0x23e>;
    
    				map0 {
    					trip = <0x121>;
    					cooling-device = <0x11f 0xffffffff 0xffffffff>;
    				};
    			};
    		};
    	};
    
    	pmu {
    		compatible = "arm,cortex-a15-pmu";
    		interrupt-parent = <0x8>;
    		interrupts = <0x0 0x83 0x4 0x0 0x84 0x4>;
    	};
    
    	memory@0 {
    		device_type = "memory";
    		reg = <0x0 0x80000000 0x0 0x80000000>;
    	};
    
    	reserved-memory {
    		#address-cells = <0x2>;
    		#size-cells = <0x2>;
    		ranges;
    
    		ipu2-memory@95800000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x95800000 0x0 0x3800000>;
    			reusable;
    			status = "okay";
    			phandle = <0xc4>;
    		};
    
    		dsp1-memory@99000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x99000000 0x0 0x4000000>;
    			reusable;
    			status = "okay";
    			phandle = <0xca>;
    		};
    
    		ipu1-memory@9d000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x9d000000 0x0 0x2000000>;
    			reusable;
    			status = "okay";
    			phandle = <0xbd>;
    		};
    
    		dsp2-memory@9f000000 {
    			compatible = "shared-dma-pool";
    			reg = <0x0 0x9f000000 0x0 0x800000>;
    			reusable;
    			status = "okay";
    			phandle = <0x11a>;
    		};
    
    		cmem_block_mem@a0000000 {
    			reg = <0x0 0xa0000000 0x0 0xc000000>;
    			no-map;
    			status = "okay";
    			phandle = <0x12c>;
    		};
    
    		cmem_block_mem@40500000 {
    			reg = <0x0 0x40500000 0x0 0x100000>;
    			no-map;
    			status = "okay";
    			phandle = <0x12d>;
    		};
    	};
    
    	fixedregulator-main_12v0 {
    		compatible = "regulator-fixed";
    		regulator-name = "main_12v0";
    		regulator-min-microvolt = <0xb71b00>;
    		regulator-max-microvolt = <0xb71b00>;
    		regulator-always-on;
    		regulator-boot-on;
    		phandle = <0x122>;
    	};
    
    	fixedregulator-evm_5v0 {
    		compatible = "regulator-fixed";
    		regulator-name = "evm_5v0";
    		regulator-min-microvolt = <0x4c4b40>;
    		regulator-max-microvolt = <0x4c4b40>;
    		vin-supply = <0x122>;
    		regulator-always-on;
    		regulator-boot-on;
    		phandle = <0x23f>;
    	};
    
    	fixedregulator-vdd_3v3 {
    		compatible = "regulator-fixed";
    		regulator-name = "vdd_3v3";
    		regulator-min-microvolt = <0x325aa0>;
    		regulator-max-microvolt = <0x325aa0>;
    		phandle = <0xcf>;
    	};
    
    	fixedregulator-aic_dvdd {
    		compatible = "regulator-fixed";
    		regulator-name = "aic_dvdd_fixed";
    		vin-supply = <0xcf>;
    		regulator-min-microvolt = <0x1b7740>;
    		regulator-max-microvolt = <0x1b7740>;
    		phandle = <0xd0>;
    	};
    
    	fixedregulator-vtt {
    		compatible = "regulator-fixed";
    		regulator-name = "vtt_fixed";
    		vin-supply = <0x123>;
    		regulator-min-microvolt = <0x325aa0>;
    		regulator-max-microvolt = <0x325aa0>;
    		regulator-always-on;
    		regulator-boot-on;
    		enable-active-high;
    		gpio = <0xce 0xb 0x0>;
    		phandle = <0x240>;
    	};
    
    	leds {
    		compatible = "gpio-leds";
    
    		led0 {
    			label = "beagle-x15:usr0";
    			gpios = <0xce 0x9 0x0>;
    			linux,default-trigger = "heartbeat";
    			default-state = "off";
    		};
    
    		led1 {
    			label = "beagle-x15:usr1";
    			gpios = <0xce 0x8 0x0>;
    			linux,default-trigger = "cpu0";
    			default-state = "off";
    		};
    
    		led2 {
    			label = "beagle-x15:usr2";
    			gpios = <0xce 0xe 0x0>;
    			linux,default-trigger = "mmc0";
    			default-state = "off";
    		};
    
    		led3 {
    			label = "beagle-x15:usr3";
    			gpios = <0xce 0xf 0x0>;
    			linux,default-trigger = "disk-activity";
    			default-state = "off";
    		};
    
    		led4 {
    			label = "218_error";
    			gpios = <0xce 0x1e 0x0>;
    			default-state = "off";
    		};
    
    		led5 {
    			label = "218_connection";
    			gpios = <0xce 0x1f 0x0>;
    			default-state = "on";
    		};
    	};
    
    	gpio_fan {
    		compatible = "gpio-fan";
    		gpios = <0x124 0x2 0x0>;
    		gpio-fan,speed-map = <0x0 0x0 0x32c8 0x1>;
    		#cooling-cells = <0x2>;
    		phandle = <0x11f>;
    	};
    
    	connector {
    		compatible = "hdmi-connector";
    		label = "hdmi";
    		type = [61 00];
    		phandle = <0x241>;
    
    		port {
    
    			endpoint {
    				remote-endpoint = <0x125>;
    				phandle = <0x127>;
    			};
    		};
    	};
    
    	encoder {
    		compatible = "ti,tpd12s015";
    		gpios = <0xce 0xa 0x0 0xaf 0x1e 0x0 0xce 0xc 0x0>;
    		phandle = <0x242>;
    
    		ports {
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    
    			port@0 {
    				reg = <0x0>;
    
    				endpoint {
    					remote-endpoint = <0x126>;
    					phandle = <0x110>;
    				};
    			};
    
    			port@1 {
    				reg = <0x1>;
    
    				endpoint {
    					remote-endpoint = <0x127>;
    					phandle = <0x125>;
    				};
    			};
    		};
    	};
    
    	sound0 {
    		status = "disabled";
    		compatible = "simple-audio-card";
    		simple-audio-card,name = "BeagleBoard-X15";
    		simple-audio-card,widgets = "Line", "Line Out", "Line", "Line In";
    		simple-audio-card,routing = "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC2L", "Line In", "MIC2R", "Line In";
    		simple-audio-card,format = "dsp_b";
    		simple-audio-card,bitclock-master = <0x128>;
    		simple-audio-card,frame-master = <0x128>;
    		simple-audio-card,bitclock-inversion;
    		phandle = <0x243>;
    
    		simple-audio-card,cpu {
    			sound-dai = <0x129>;
    			status = "disabled";
    		};
    
    		simple-audio-card,codec {
    			sound-dai = <0x12a>;
    			clocks = <0x12b>;
    			phandle = <0x128>;
    		};
    	};
    
    	cmem {
    		compatible = "ti,cmem";
    		#address-cells = <0x1>;
    		#size-cells = <0x0>;
    		#pool-size-cells = <0x2>;
    		status = "okay";
    
    		cmem_block@0 {
    			reg = <0x0>;
    			memory-region = <0x12c>;
    			cmem-buf-pools = <0x1 0x0 0xc000000>;
    			phandle = <0x244>;
    		};
    
    		cmem_block@1 {
    			reg = <0x1>;
    			memory-region = <0x12d>;
    			phandle = <0x245>;
    		};
    	};
    
    	__symbols__ {
    		wlcore = "/ocp/mmc@480ad000/wlcore@2", "";
    		vmmcwl_fixed = "/fixedregulator-mmcwl", "";
    		com_3v6 = "/fixedregulator-com_3v6", "";
    		lcd_bl = "/backlight", "";
    		gic = "/interrupt-controller@48211000";
    		wakeupgen = "/interrupt-controller@48281000";
    		cpu0 = "/cpus/cpu@0";
    		cpu0_opp_table = "/opp-table";
    		l4_cfg = "/ocp/l4@4a000000";
    		scm = "/ocp/l4@4a000000/scm@2000";
    		scm_conf = "/ocp/l4@4a000000/scm@2000/scm_conf@0";
    		pbias_regulator = "/ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00";
    		pbias_mmc_reg = "/ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00/pbias_mmc_omap5";
    		scm_conf_clocks = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks";
    		dss_deshdcp_clk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/dss_deshdcp_clk@558";
    		ehrpwm0_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm0_tbclk@558";
    		ehrpwm1_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm1_tbclk@558";
    		ehrpwm2_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm2_tbclk@558";
    		sys_32k_ck = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/sys_32k_ck";
    		dra7_pmx_core = "/ocp/l4@4a000000/scm@2000/pinmux@1400";
    		mmc1_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default";
    		mmc1_pins_default_no_clk_pu = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default_no_clk_pu";
    		mmc1_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr12";
    		mmc1_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_hs";
    		mmc1_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr25";
    		mmc1_pins_sdr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr50";
    		mmc1_pins_ddr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_ddr50";
    		mmc1_pins_sdr104 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr104";
    		mmc2_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_default";
    		mmc2_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs";
    		mmc2_pins_ddr_3_3v_rev11 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_3_3v_rev11";
    		mmc2_pins_ddr_1_8v_rev11 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_1_8v_rev11";
    		mmc2_pins_ddr_rev20 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_rev20";
    		mmc2_pins_hs200 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs200";
    		mmc4_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_default";
    		mmc4_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_hs";
    		mmc3_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_default";
    		mmc3_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_hs";
    		mmc3_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr12";
    		mmc3_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr25";
    		mmc3_pins_sdr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr50";
    		mmc4_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr12";
    		mmc4_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr25";
    		scm_conf1 = "/ocp/l4@4a000000/scm@2000/scm_conf@1c04";
    		scm_conf_pcie = "/ocp/l4@4a000000/scm@2000/scm_conf@1c24";
    		sdma_xbar = "/ocp/l4@4a000000/scm@2000/dma-router@b78";
    		edma_xbar = "/ocp/l4@4a000000/scm@2000/dma-router@c78";
    		cm_core_aon = "/ocp/l4@4a000000/cm_core_aon@5000";
    		cm_core_aon_clocks = "/ocp/l4@4a000000/cm_core_aon@5000/clocks";
    		atl_clkin0_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin0_ck";
    		atl_clkin1_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin1_ck";
    		atl_clkin2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin2_ck";
    		atl_clkin3_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin3_ck";
    		hdmi_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clkin_ck";
    		mlb_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlb_clkin_ck";
    		mlbp_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlbp_clkin_ck";
    		pciesref_acs_clk_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/pciesref_acs_clk_ck";
    		ref_clkin0_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin0_ck";
    		ref_clkin1_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin1_ck";
    		ref_clkin2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin2_ck";
    		ref_clkin3_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin3_ck";
    		rmii_clk_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/rmii_clk_ck";
    		sdvenc_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sdvenc_clkin_ck";
    		secure_32k_clk_src_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/secure_32k_clk_src_ck";
    		sys_clk32_crystal_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_crystal_ck";
    		sys_clk32_pseudo_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_pseudo_ck";
    		virt_12000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_12000000_ck";
    		virt_13000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_13000000_ck";
    		virt_16800000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_16800000_ck";
    		virt_19200000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_19200000_ck";
    		virt_20000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_20000000_ck";
    		virt_26000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_26000000_ck";
    		virt_27000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_27000000_ck";
    		virt_38400000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_38400000_ck";
    		sys_clkin2 = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clkin2";
    		usb_otg_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_otg_clkin_ck";
    		video1_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clkin_ck";
    		video1_m2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_m2_clkin_ck";
    		video2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clkin_ck";
    		video2_m2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_m2_clkin_ck";
    		dpll_abe_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_ck@1e0";
    		dpll_abe_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_x2_ck";
    		dpll_abe_m2x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2x2_ck@1f0";
    		abe_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/abe_clk@108";
    		dpll_abe_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2_ck@1f0";
    		dpll_abe_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m3x2_ck@1f4";
    		dpll_core_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_byp_mux@12c";
    		dpll_core_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_ck@120";
    		dpll_core_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_x2_ck";
    		dpll_core_h12x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h12x2_ck@13c";
    		mpu_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dpll_hs_clk_div";
    		dpll_mpu_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_ck@160";
    		dpll_mpu_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_m2_ck@170";
    		mpu_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dclk_div";
    		dsp_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dsp_dpll_hs_clk_div";
    		dpll_dsp_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_byp_mux@240";
    		dpll_dsp_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_ck@234";
    		dpll_dsp_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m2_ck@244";
    		iva_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dpll_hs_clk_div";
    		dpll_iva_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_byp_mux@1ac";
    		dpll_iva_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_ck@1a0";
    		dpll_iva_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_m2_ck@1b0";
    		iva_dclk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dclk";
    		dpll_gpu_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_byp_mux@2e4";
    		dpll_gpu_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_ck@2d8";
    		dpll_gpu_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_m2_ck@2e8";
    		dpll_core_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_m2_ck@130";
    		core_dpll_out_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/core_dpll_out_dclk_div";
    		dpll_ddr_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_byp_mux@21c";
    		dpll_ddr_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_ck@210";
    		dpll_ddr_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_m2_ck@220";
    		dpll_gmac_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_byp_mux@2b4";
    		dpll_gmac_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_ck@2a8";
    		dpll_gmac_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m2_ck@2b8";
    		video2_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_dclk_div";
    		video1_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_dclk_div";
    		hdmi_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_dclk_div";
    		per_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/per_dpll_hs_clk_div";
    		usb_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_dpll_hs_clk_div";
    		eve_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dpll_hs_clk_div";
    		dpll_eve_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_byp_mux@290";
    		dpll_eve_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_ck@284";
    		dpll_eve_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_m2_ck@294";
    		eve_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dclk_div";
    		dpll_core_h13x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h13x2_ck@140";
    		dpll_core_h14x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h14x2_ck@144";
    		dpll_core_h22x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h22x2_ck@154";
    		dpll_core_h23x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h23x2_ck@158";
    		dpll_core_h24x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h24x2_ck@15c";
    		dpll_ddr_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_x2_ck";
    		dpll_ddr_h11x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_h11x2_ck@228";
    		dpll_dsp_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_x2_ck";
    		dpll_dsp_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m3x2_ck@248";
    		dpll_gmac_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_x2_ck";
    		dpll_gmac_h11x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h11x2_ck@2c0";
    		dpll_gmac_h12x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h12x2_ck@2c4";
    		dpll_gmac_h13x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h13x2_ck@2c8";
    		dpll_gmac_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m3x2_ck@2bc";
    		gmii_m_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/gmii_m_clk_div";
    		hdmi_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clk2_div";
    		hdmi_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_div_clk";
    		l3_iclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/l3_iclk_div@100";
    		l4_root_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/l4_root_clk_div";
    		video1_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clk2_div";
    		video1_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_div_clk";
    		video2_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clk2_div";
    		video2_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_div_clk";
    		ipu1_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ipu1_gfclk_mux@520";
    		mcasp1_ahclkr_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_ahclkr_mux@550";
    		mcasp1_ahclkx_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_ahclkx_mux@550";
    		mcasp1_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_aux_gfclk_mux@550";
    		timer5_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer5_gfclk_mux@558";
    		timer6_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer6_gfclk_mux@560";
    		timer7_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer7_gfclk_mux@568";
    		timer8_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer8_gfclk_mux@570";
    		uart6_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/uart6_gfclk_mux@580";
    		dummy_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dummy_ck";
    		cm_core_aon_clockdomains = "/ocp/l4@4a000000/cm_core_aon@5000/clockdomains";
    		cm_core = "/ocp/l4@4a000000/cm_core@8000";
    		cm_core_clocks = "/ocp/l4@4a000000/cm_core@8000/clocks";
    		dpll_pcie_ref_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_ck@200";
    		dpll_pcie_ref_m2ldo_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2ldo_ck@210";
    		apll_pcie_in_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_in_clk_mux@4ae06118";
    		apll_pcie_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_ck@21c";
    		optfclk_pciephy1_32khz = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_32khz@4a0093b0";
    		optfclk_pciephy2_32khz = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_32khz@4a0093b8";
    		optfclk_pciephy_div = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy_div@4a00821c";
    		optfclk_pciephy1_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_clk@4a0093b0";
    		optfclk_pciephy2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_clk@4a0093b8";
    		optfclk_pciephy1_div_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_div_clk@4a0093b0";
    		optfclk_pciephy2_div_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_div_clk@4a0093b8";
    		apll_pcie_clkvcoldo = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo";
    		apll_pcie_clkvcoldo_div = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo_div";
    		apll_pcie_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_m2_ck";
    		dpll_per_byp_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_byp_mux@14c";
    		dpll_per_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_ck@140";
    		dpll_per_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2_ck@150";
    		func_96m_aon_dclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_aon_dclk_div";
    		dpll_usb_byp_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_byp_mux@18c";
    		dpll_usb_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_ck@180";
    		dpll_usb_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_m2_ck@190";
    		dpll_pcie_ref_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2_ck@210";
    		dpll_per_x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_x2_ck";
    		dpll_per_h11x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h11x2_ck@158";
    		dpll_per_h12x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h12x2_ck@15c";
    		dpll_per_h13x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h13x2_ck@160";
    		dpll_per_h14x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h14x2_ck@164";
    		dpll_per_m2x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2x2_ck@150";
    		dpll_usb_clkdcoldo = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_clkdcoldo";
    		func_128m_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_128m_clk";
    		func_12m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_12m_fclk";
    		func_24m_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_24m_clk";
    		func_48m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_48m_fclk";
    		func_96m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_fclk";
    		l3init_60m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/l3init_60m_fclk@104";
    		clkout2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/clkout2_clk@6b0";
    		l3init_960m_gfclk = "/ocp/l4@4a000000/cm_core@8000/clocks/l3init_960m_gfclk@6c0";
    		dss_32khz_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_32khz_clk@1120";
    		dss_48mhz_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_48mhz_clk@1120";
    		dss_dss_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_dss_clk@1120";
    		dss_hdmi_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_hdmi_clk@1120";
    		dss_video1_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_video1_clk@1120";
    		dss_video2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_video2_clk@1120";
    		gpio2_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio2_dbclk@1760";
    		gpio3_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio3_dbclk@1768";
    		gpio4_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio4_dbclk@1770";
    		gpio5_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio5_dbclk@1778";
    		gpio6_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio6_dbclk@1780";
    		gpio7_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio7_dbclk@1810";
    		gpio8_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio8_dbclk@1818";
    		mmc1_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_clk32k@1328";
    		mmc2_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_clk32k@1330";
    		mmc3_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_clk32k@1820";
    		mmc4_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_clk32k@1828";
    		sata_ref_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/sata_ref_clk@1388";
    		usb_otg_ss1_refclk960m = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_otg_ss1_refclk960m@13f0";
    		usb_otg_ss2_refclk960m = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_otg_ss2_refclk960m@1340";
    		usb_phy1_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy1_always_on_clk32k@640";
    		usb_phy2_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy2_always_on_clk32k@688";
    		usb_phy3_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy3_always_on_clk32k@698";
    		atl_dpll_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/atl_dpll_clk_mux@c00";
    		atl_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/atl_gfclk_mux@c00";
    		rmii_50mhz_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/rmii_50mhz_clk_mux@13d0";
    		gmac_rft_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gmac_rft_clk_mux@13d0";
    		gpu_core_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gpu_core_gclk_mux@1220";
    		gpu_hyd_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gpu_hyd_gclk_mux@1220";
    		l3instr_ts_gclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/l3instr_ts_gclk_div@e50";
    		mcasp2_ahclkr_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_ahclkr_mux@1860";
    		mcasp2_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_ahclkx_mux@1860";
    		mcasp2_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_aux_gfclk_mux@1860";
    		mcasp3_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp3_ahclkx_mux@1868";
    		mcasp3_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp3_aux_gfclk_mux@1868";
    		mcasp4_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp4_ahclkx_mux@1898";
    		mcasp4_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp4_aux_gfclk_mux@1898";
    		mcasp5_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp5_ahclkx_mux@1878";
    		mcasp5_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp5_aux_gfclk_mux@1878";
    		mcasp6_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp6_ahclkx_mux@1904";
    		mcasp6_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp6_aux_gfclk_mux@1904";
    		mcasp7_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp7_ahclkx_mux@1908";
    		mcasp7_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp7_aux_gfclk_mux@1908";
    		mcasp8_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp8_ahclkx_mux@1890";
    		mcasp8_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp8_aux_gfclk_mux@1890";
    		mmc1_fclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_fclk_mux@1328";
    		mmc1_fclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_fclk_div@1328";
    		mmc2_fclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_fclk_mux@1330";
    		mmc2_fclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_fclk_div@1330";
    		mmc3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_gfclk_mux@1820";
    		mmc3_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_gfclk_div@1820";
    		mmc4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_gfclk_mux@1828";
    		mmc4_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_gfclk_div@1828";
    		qspi_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/qspi_gfclk_mux@1838";
    		qspi_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/qspi_gfclk_div@1838";
    		timer10_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer10_gfclk_mux@1728";
    		timer11_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer11_gfclk_mux@1730";
    		timer13_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer13_gfclk_mux@17c8";
    		timer14_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer14_gfclk_mux@17d0";
    		timer15_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer15_gfclk_mux@17d8";
    		timer16_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer16_gfclk_mux@1830";
    		timer2_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer2_gfclk_mux@1738";
    		timer3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer3_gfclk_mux@1740";
    		timer4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer4_gfclk_mux@1748";
    		timer9_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer9_gfclk_mux@1750";
    		uart1_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart1_gfclk_mux@1840";
    		uart2_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart2_gfclk_mux@1848";
    		uart3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart3_gfclk_mux@1850";
    		uart4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart4_gfclk_mux@1858";
    		uart5_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart5_gfclk_mux@1870";
    		uart7_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart7_gfclk_mux@18d0";
    		uart8_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart8_gfclk_mux@18e0";
    		uart9_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart9_gfclk_mux@18e8";
    		vip1_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip1_gclk_mux@1020";
    		vip2_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip2_gclk_mux@1028";
    		vip3_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip3_gclk_mux@1030";
    		cm_core_clockdomains = "/ocp/l4@4a000000/cm_core@8000/clockdomains";
    		coreaon_clkdm = "/ocp/l4@4a000000/cm_core@8000/clockdomains/coreaon_clkdm";
    		l4_wkup = "/ocp/l4@4ae00000";
    		counter32k = "/ocp/l4@4ae00000/counter@4000";
    		prm = "/ocp/l4@4ae00000/prm@6000";
    		prm_clocks = "/ocp/l4@4ae00000/prm@6000/clocks";
    		sys_clkin1 = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clkin1@110";
    		abe_dpll_sys_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_sys_clk_mux@118";
    		abe_dpll_bypass_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_bypass_clk_mux@114";
    		abe_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_clk_mux@10c";
    		abe_24m_fclk = "/ocp/l4@4ae00000/prm@6000/clocks/abe_24m_fclk@11c";
    		aess_fclk = "/ocp/l4@4ae00000/prm@6000/clocks/aess_fclk@178";
    		abe_giclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_giclk_div@174";
    		abe_lp_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_lp_clk_div@1d8";
    		abe_sys_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_sys_clk_div@120";
    		adc_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/adc_gfclk_mux@1dc";
    		sys_clk1_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clk1_dclk_div@1c8";
    		sys_clk2_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clk2_dclk_div@1cc";
    		per_abe_x1_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_dclk_div@1bc";
    		dsp_gclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/dsp_gclk_div@18c";
    		gpu_dclk = "/ocp/l4@4ae00000/prm@6000/clocks/gpu_dclk@1a0";
    		emif_phy_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/emif_phy_dclk_div@190";
    		gmac_250m_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/gmac_250m_dclk_div@19c";
    		gmac_main_clk = "/ocp/l4@4ae00000/prm@6000/clocks/gmac_main_clk";
    		l3init_480m_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/l3init_480m_dclk_div@1ac";
    		usb_otg_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/usb_otg_dclk_div@184";
    		sata_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sata_dclk_div@1c0";
    		pcie2_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/pcie2_dclk_div@1b8";
    		pcie_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/pcie_dclk_div@1b4";
    		emu_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/emu_dclk_div@194";
    		secure_32k_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/secure_32k_dclk_div@1c4";
    		clkoutmux0_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux0_clk_mux@158";
    		clkoutmux1_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux1_clk_mux@15c";
    		clkoutmux2_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux2_clk_mux@160";
    		custefuse_sys_gfclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/custefuse_sys_gfclk_div";
    		eve_clk = "/ocp/l4@4ae00000/prm@6000/clocks/eve_clk@180";
    		hdmi_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/hdmi_dpll_clk_mux@164";
    		mlb_clk = "/ocp/l4@4ae00000/prm@6000/clocks/mlb_clk@134";
    		mlbp_clk = "/ocp/l4@4ae00000/prm@6000/clocks/mlbp_clk@130";
    		per_abe_x1_gfclk2_div = "/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_gfclk2_div@138";
    		timer_sys_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/timer_sys_clk_div@144";
    		video1_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/video1_dpll_clk_mux@168";
    		video2_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/video2_dpll_clk_mux@16c";
    		wkupaon_iclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/wkupaon_iclk_mux@108";
    		gpio1_dbclk = "/ocp/l4@4ae00000/prm@6000/clocks/gpio1_dbclk@1838";
    		dcan1_sys_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/dcan1_sys_clk_mux@1888";
    		timer1_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/timer1_gfclk_mux@1840";
    		uart10_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/uart10_gfclk_mux@1880";
    		prm_clockdomains = "/ocp/l4@4ae00000/prm@6000/clockdomains";
    		scm_wkup = "/ocp/l4@4ae00000/scm_conf@c000";
    		pcie1_rc = "/ocp/axi@0/pcie@51000000";
    		pcie1_intc = "/ocp/axi@0/pcie@51000000/interrupt-controller";
    		pcie1_ep = "/ocp/axi@0/pcie_ep@51000000";
    		pcie2_rc = "/ocp/axi@1/pcie@51800000";
    		pcie2_intc = "/ocp/axi@1/pcie@51800000/interrupt-controller";
    		ocmcram1 = "/ocp/ocmcram@40300000";
    		ocmcram2 = "/ocp/ocmcram@40400000";
    		ocmcram3 = "/ocp/ocmcram@40500000";
    		bandgap = "/ocp/bandgap@4a0021e0";
    		dsp1_system = "/ocp/dsp_system@40d00000";
    		dra7_iodelay_core = "/ocp/padconf@4844a000";
    		mmc1_iodelay_ddr_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr_rev11_conf";
    		mmc1_iodelay_ddr_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr50_rev20_conf";
    		mmc1_iodelay_sdr104_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev11_conf";
    		mmc1_iodelay_sdr104_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev20_conf";
    		mmc2_iodelay_hs200_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev11_conf";
    		mmc2_iodelay_hs200_rev20_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev20_conf";
    		mmc2_iodelay_ddr_3_3v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_3_3v_rev11_conf";
    		mmc2_iodelay_ddr_1_8v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_1_8v_rev11_conf";
    		mmc3_iodelay_manual1_rev11_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
    		mmc3_iodelay_manual1_rev20_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
    		mmc4_iodelay_ds_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev11_conf";
    		mmc4_iodelay_ds_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev20_conf";
    		mmc4_iodelay_sdr12_hs_sdr25_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev11_conf";
    		mmc4_iodelay_sdr12_hs_sdr25_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev20_conf";
    		sdma = "/ocp/dma-controller@4a056000";
    		edma = "/ocp/edma@43300000";
    		edma_tptc0 = "/ocp/tptc@43400000";
    		edma_tptc1 = "/ocp/tptc@43500000";
    		gpio1 = "/ocp/gpio@4ae10000";
    		gpio2 = "/ocp/gpio@48055000";
    		gpio3 = "/ocp/gpio@48057000";
    		gpio4 = "/ocp/gpio@48059000";
    		gpio5 = "/ocp/gpio@4805b000";
    		gpio6 = "/ocp/gpio@4805d000";
    		gpio7 = "/ocp/gpio@48051000";
    		gpio8 = "/ocp/gpio@48053000";
    		uart1 = "/ocp/serial@4806a000";
    		uart2 = "/ocp/serial@4806c000";
    		uart3 = "/ocp/serial@48020000";
    		uart4 = "/ocp/serial@4806e000";
    		uart5 = "/ocp/serial@48066000";
    		uart6 = "/ocp/serial@48068000";
    		uart7 = "/ocp/serial@48420000";
    		uart8 = "/ocp/serial@48422000";
    		uart9 = "/ocp/serial@48424000";
    		uart10 = "/ocp/serial@4ae2b000";
    		mailbox1 = "/ocp/mailbox@4a0f4000";
    		mailbox2 = "/ocp/mailbox@4883a000";
    		mailbox3 = "/ocp/mailbox@4883c000";
    		mailbox4 = "/ocp/mailbox@4883e000";
    		mailbox5 = "/ocp/mailbox@48840000";
    		mbox_ipu1_ipc3x = "/ocp/mailbox@48840000/mbox_ipu1_ipc3x";
    		mbox_dsp1_ipc3x = "/ocp/mailbox@48840000/mbox_dsp1_ipc3x";
    		mailbox6 = "/ocp/mailbox@48842000";
    		mbox_ipu2_ipc3x = "/ocp/mailbox@48842000/mbox_ipu2_ipc3x";
    		mbox_dsp2_ipc3x = "/ocp/mailbox@48842000/mbox_dsp2_ipc3x";
    		mailbox7 = "/ocp/mailbox@48844000";
    		mailbox8 = "/ocp/mailbox@48846000";
    		mailbox9 = "/ocp/mailbox@4885e000";
    		mailbox10 = "/ocp/mailbox@48860000";
    		mailbox11 = "/ocp/mailbox@48862000";
    		mailbox12 = "/ocp/mailbox@48864000";
    		mailbox13 = "/ocp/mailbox@48802000";
    		timer1 = "/ocp/timer@4ae18000";
    		timer2 = "/ocp/timer@48032000";
    		timer3 = "/ocp/timer@48034000";
    		timer4 = "/ocp/timer@48036000";
    		timer5 = "/ocp/timer@48820000";
    		timer6 = "/ocp/timer@48822000";
    		timer7 = "/ocp/timer@48824000";
    		timer8 = "/ocp/timer@48826000";
    		timer9 = "/ocp/timer@4803e000";
    		timer10 = "/ocp/timer@48086000";
    		timer11 = "/ocp/timer@48088000";
    		timer12 = "/ocp/timer@4ae20000";
    		timer13 = "/ocp/timer@48828000";
    		timer14 = "/ocp/timer@4882a000";
    		timer15 = "/ocp/timer@4882c000";
    		timer16 = "/ocp/timer@4882e000";
    		wdt2 = "/ocp/wdt@4ae14000";
    		hwspinlock = "/ocp/spinlock@4a0f6000";
    		ipu1 = "/ocp/ipu@58820000";
    		ipu2 = "/ocp/ipu@55020000";
    		dsp1 = "/ocp/dsp@40800000";
    		i2c1 = "/ocp/i2c@48070000";
    		tps659038 = "/ocp/i2c@48070000/tps659038@58";
    		smps12_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps12";
    		smps3_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps3";
    		smps45_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps45";
    		smps6_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps6";
    		smps8_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps8";
    		ldo1_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo1";
    		ldo2_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo2";
    		ldo3_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo3";
    		ldo4_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo4";
    		ldo9_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo9";
    		ldoln_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldoln";
    		ldousb_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldousb";
    		regen1 = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/regen1";
    		tps659038_rtc = "/ocp/i2c@48070000/tps659038@58/tps659038_rtc";
    		tps659038_pwr_button = "/ocp/i2c@48070000/tps659038@58/tps659038_pwr_button";
    		tps659038_gpio = "/ocp/i2c@48070000/tps659038@58/tps659038_gpio";
    		extcon_usb2 = "/ocp/i2c@48070000/tps659038@58/tps659038_usb";
    		tmp102 = "/ocp/i2c@48070000/tmp102@48";
    		tlv320aic3104 = "/ocp/i2c@48070000/tlv320aic3104@18";
    		eeprom = "/ocp/i2c@48070000/eeprom@50";
    		i2c2 = "/ocp/i2c@48072000";
    		i2c3 = "/ocp/i2c@48060000";
    		mcp_rtc = "/ocp/i2c@48060000/rtc@6f";
    		i2c4 = "/ocp/i2c@4807a000";
    		i2c5 = "/ocp/i2c@4807c000";
    		mmc1 = "/ocp/mmc@4809c000";
    		mmc2 = "/ocp/mmc@480b4000";
    		mmc3 = "/ocp/mmc@480ad000";
    		mmc4 = "/ocp/mmc@480d1000";
    		mmu0_dsp1 = "/ocp/mmu@40d01000";
    		mmu1_dsp1 = "/ocp/mmu@40d02000";
    		mmu_ipu1 = "/ocp/mmu@58882000";
    		mmu_ipu2 = "/ocp/mmu@55082000";
    		pruss_soc_bus1 = "/ocp/pruss_soc_bus@4b226004";
    		pruss1 = "/ocp/pruss_soc_bus@4b226004/pruss@0";
    		pruss1_mem = "/ocp/pruss_soc_bus@4b226004/pruss@0/memories@0";
    		pruss1_cfg = "/ocp/pruss_soc_bus@4b226004/pruss@0/cfg@26000";
    		pruss1_mii_rt = "/ocp/pruss_soc_bus@4b226004/pruss@0/mii_rt@32000";
    		pruss1_intc = "/ocp/pruss_soc_bus@4b226004/pruss@0/intc@20000";
    		pru1_0 = "/ocp/pruss_soc_bus@4b226004/pruss@0/pru@34000";
    		pru1_1 = "/ocp/pruss_soc_bus@4b226004/pruss@0/pru@38000";
    		pruss1_mdio = "/ocp/pruss_soc_bus@4b226004/pruss@0/mdio@32400";
    		pruss_soc_bus2 = "/ocp/pruss_soc_bus@4b2a6004";
    		pruss2 = "/ocp/pruss_soc_bus@4b2a6004/pruss@0";
    		pruss2_mem = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/memories@0";
    		pruss2_cfg = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/cfg@26000";
    		pruss2_iep = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/iep@2e000";
    		pruss2_mii_rt = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/mii_rt@32000";
    		pruss2_intc = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/intc@20000";
    		pru2_0 = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/pru@34000";
    		pru2_1 = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/pru@38000";
    		pruss2_mdio = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/mdio@32400";
    		abb_mpu = "/ocp/regulator-abb-mpu";
    		abb_ivahd = "/ocp/regulator-abb-ivahd";
    		abb_dspeve = "/ocp/regulator-abb-dspeve";
    		abb_gpu = "/ocp/regulator-abb-gpu";
    		mcspi1 = "/ocp/spi@48098000";
    		mcspi2 = "/ocp/spi@4809a000";
    		mcspi3 = "/ocp/spi@480b8000";
    		mcspi4 = "/ocp/spi@480ba000";
    		qspi = "/ocp/qspi@4b300000";
    		sata_phy = "/ocp/ocp2scp@4a090000/phy@4A096000";
    		pcie1_phy = "/ocp/ocp2scp@4a090000/pciephy@4a094000";
    		pcie2_phy = "/ocp/ocp2scp@4a090000/pciephy@4a095000";
    		sata = "/ocp/sata@4a141100";
    		rtc = "/ocp/rtc@48838000";
    		usb2_phy1 = "/ocp/ocp2scp@4a080000/phy@4a084000";
    		usb2_phy2 = "/ocp/ocp2scp@4a080000/phy@4a085000";
    		usb3_phy1 = "/ocp/ocp2scp@4a080000/phy@4a084400";
    		omap_dwc3_1 = "/ocp/omap_dwc3_1@48880000";
    		usb1 = "/ocp/omap_dwc3_1@48880000/usb@48890000";
    		omap_dwc3_2 = "/ocp/omap_dwc3_2@488c0000";
    		usb2 = "/ocp/omap_dwc3_2@488c0000/usb@488d0000";
    		omap_dwc3_3 = "/ocp/omap_dwc3_3@48900000";
    		usb3 = "/ocp/omap_dwc3_3@48900000/usb@48910000";
    		elm = "/ocp/elm@48078000";
    		gpmc = "/ocp/gpmc@50000000";
    		atl = "/ocp/atl@4843c000";
    		mcasp1 = "/ocp/mcasp@48460000";
    		mcasp2 = "/ocp/mcasp@48464000";
    		mcasp3 = "/ocp/mcasp@48468000";
    		mcasp4 = "/ocp/mcasp@4846c000";
    		mcasp5 = "/ocp/mcasp@48470000";
    		mcasp6 = "/ocp/mcasp@48474000";
    		mcasp7 = "/ocp/mcasp@48478000";
    		mcasp8 = "/ocp/mcasp@4847c000";
    		crossbar_mpu = "/ocp/crossbar@4a002a48";
    		mac = "/ocp/ethernet@48484000";
    		davinci_mdio = "/ocp/ethernet@48484000/mdio@48485000";
    		phy0 = "/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@0";
    		phy1 = "/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@2";
    		cpsw_emac0 = "/ocp/ethernet@48484000/slave@48480200";
    		cpsw_emac1 = "/ocp/ethernet@48484000/slave@48480300";
    		phy_sel = "/ocp/ethernet@48484000/cpsw-phy-sel@4a002554";
    		dcan1 = "/ocp/can@4ae3c000";
    		dcan2 = "/ocp/can@48480000";
    		gpu = "/ocp/gpu@56000000";
    		bb2d = "/ocp/bb2d@59000000";
    		dss = "/ocp/dss@58000000";
    		hdmi = "/ocp/dss@58000000/encoder@58060000";
    		hdmi_out = "/ocp/dss@58000000/encoder@58060000/port/endpoint";
    		epwmss0 = "/ocp/epwmss@4843e000";
    		ehrpwm0 = "/ocp/epwmss@4843e000/pwm@4843e200";
    		ecap0 = "/ocp/epwmss@4843e000/ecap@4843e100";
    		epwmss1 = "/ocp/epwmss@48440000";
    		ehrpwm1 = "/ocp/epwmss@48440000/pwm@48440200";
    		ecap1 = "/ocp/epwmss@48440000/ecap@48440100";
    		epwmss2 = "/ocp/epwmss@48442000";
    		ehrpwm2 = "/ocp/epwmss@48442000/pwm@48442200";
    		ecap2 = "/ocp/epwmss@48442000/ecap@48442100";
    		aes1 = "/ocp/aes@4b500000";
    		aes2 = "/ocp/aes@4b700000";
    		des = "/ocp/des@480a5000";
    		sham = "/ocp/sham@53100000";
    		rng = "/ocp/rng@48090000";
    		opp_supply_mpu = "/ocp/opp-supply@4a003b20";
    		vip1 = "/ocp/vip@0x48970000";
    		vin1a = "/ocp/vip@0x48970000/port@0";
    		vin2a = "/ocp/vip@0x48970000/port@1";
    		vin1b = "/ocp/vip@0x48970000/port@2";
    		vin2b = "/ocp/vip@0x48970000/port@3";
    		dsp2_system = "/ocp/dsp_system@41500000";
    		omap_dwc3_4 = "/ocp/omap_dwc3_4@48940000";
    		usb4 = "/ocp/omap_dwc3_4@48940000/usb@48950000";
    		mmu0_dsp2 = "/ocp/mmu@41501000";
    		mmu1_dsp2 = "/ocp/mmu@41502000";
    		dsp2 = "/ocp/dsp@41000000";
    		vip2 = "/ocp/vip@0x48990000";
    		vin3a = "/ocp/vip@0x48990000/port@0";
    		vin4a = "/ocp/vip@0x48990000/port@1";
    		vin3b = "/ocp/vip@0x48990000/port@2";
    		vin4b = "/ocp/vip@0x48990000/port@3";
    		vip3 = "/ocp/vip@0x489b0000";
    		vin5a = "/ocp/vip@0x489b0000/port@0";
    		vin6a = "/ocp/vip@0x489b0000/port@1";
    		thermal_zones = "/thermal-zones";
    		cpu_thermal = "/thermal-zones/cpu_thermal";
    		cpu_trips = "/thermal-zones/cpu_thermal/trips";
    		cpu_alert0 = "/thermal-zones/cpu_thermal/trips/cpu_alert";
    		cpu_crit = "/thermal-zones/cpu_thermal/trips/cpu_crit";
    		cpu_alert1 = "/thermal-zones/cpu_thermal/trips/cpu_alert1";
    		cpu_cooling_maps = "/thermal-zones/cpu_thermal/cooling-maps";
    		gpu_thermal = "/thermal-zones/gpu_thermal";
    		gpu_crit = "/thermal-zones/gpu_thermal/trips/gpu_crit";
    		core_thermal = "/thermal-zones/core_thermal";
    		core_crit = "/thermal-zones/core_thermal/trips/core_crit";
    		dspeve_thermal = "/thermal-zones/dspeve_thermal";
    		dspeve_crit = "/thermal-zones/dspeve_thermal/trips/dspeve_crit";
    		iva_thermal = "/thermal-zones/iva_thermal";
    		iva_crit = "/thermal-zones/iva_thermal/trips/iva_crit";
    		board_thermal = "/thermal-zones/board_thermal";
    		board_trips = "/thermal-zones/board_thermal/trips";
    		board_alert0 = "/thermal-zones/board_thermal/trips/board_alert";
    		board_crit = "/thermal-zones/board_thermal/trips/board_crit";
    		board_cooling_maps = "/thermal-zones/board_thermal/cooling-maps";
    		ipu2_memory_region = "/reserved-memory/ipu2-memory@95800000";
    		dsp1_memory_region = "/reserved-memory/dsp1-memory@99000000";
    		ipu1_memory_region = "/reserved-memory/ipu1-memory@9d000000";
    		dsp2_memory_region = "/reserved-memory/dsp2-memory@9f000000";
    		cmem_block_mem_0 = "/reserved-memory/cmem_block_mem@a0000000";
    		cmem_block_mem_1_ocmc3 = "/reserved-memory/cmem_block_mem@40500000";
    		main_12v0 = "/fixedregulator-main_12v0";
    		evm_5v0 = "/fixedregulator-evm_5v0";
    		vdd_3v3 = "/fixedregulator-vdd_3v3";
    		aic_dvdd = "/fixedregulator-aic_dvdd";
    		vtt_fixed = "/fixedregulator-vtt";
    		gpio_fan = "/gpio_fan";
    		hdmi0 = "/connector";
    		hdmi_connector_in = "/connector/port/endpoint";
    		tpd12s015 = "/encoder";
    		tpd12s015_in = "/encoder/ports/port@0/endpoint";
    		tpd12s015_out = "/encoder/ports/port@1/endpoint";
    		sound0 = "/sound0";
    		sound0_master = "/sound0/simple-audio-card,codec";
    		cmem_block_0 = "/cmem/cmem_block@0";
    		cmem_block_1 = "/cmem/cmem_block@1";
    	};
    };

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    你好。
    对我的问题有什么想法吗? 请问您能回答我的问题吗?

  • 请注意,本文内容源自机器翻译,可能存在语法或其它翻译错误,仅供参考。如需获取准确内容,请参阅链接中的英语原文或自行翻译。

    问题已解决。 原因是 PCIe 端点设备(带有 FPGA)未响应 Root Complex。 请原谅我的不安。