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器件型号：AM6442 在 E2E 论坛中、有人回复说版本08_04中支持双 NIC 配置。 但是、在 SDK 的版本08_05中、我们注意到、当 ICSSG 和 CPSW 同时配置时、SYSCFG 生成的配置信息仍不会合并、从而导致 Enet 配置部分中存在大量重复的定义、 连接到 LWIP 的接口不支持双 NIC。 如何同时配置 ICSSG 和 CPSW？
以 ti_enet_soc.c 文件为例、以下是生成的 ti_enet_soc.c 文件代码和编译信息：
syscfg/ti_enet_soc.c:1137:10: error: redefinition of 'gEnetSoc_perObj'
Enet_Obj gEnetSoc_perObj[] =
^
syscfg/ti_enet_soc.c:290:10: note: previous definition is here
Enet_Obj gEnetSoc_perObj[] =
^
syscfg/ti_enet_soc.c:1255:24: error: redefinition of 'gEnetSoc_dmaObjMemInfo'
EnetUdma_DrvObjMemInfo gEnetSoc_dmaObjMemInfo =
^
syscfg/ti_enet_soc.c:300:24: note: previous definition is here
EnetUdma_DrvObjMemInfo gEnetSoc_dmaObjMemInfo =
^
syscfg/ti_enet_soc.c:1270:9: error: redefinition of 'EnetSoc_init'
int32_t EnetSoc_init(void)
^
syscfg/ti_enet_soc.c:310:9: note: previous definition is here
int32_t EnetSoc_init(void)
^
syscfg/ti_enet_soc.c:1286:6: error: redefinition of 'EnetSoc_deinit'
void EnetSoc_deinit(void)
^
syscfg/ti_enet_soc.c:315:6: note: previous definition is here
void EnetSoc_deinit(void)
^
syscfg/ti_enet_soc.c:1297:16: error: redefinition of 'EnetSoc_getDmaHandle'
EnetDma_Handle EnetSoc_getDmaHandle(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:320:16: note: previous definition is here
EnetDma_Handle EnetSoc_getDmaHandle(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:1325:13: error: redefinition of 'EnetSoc_getEnetHandleByIdx'
Enet_Handle EnetSoc_getEnetHandleByIdx(uint32_t idx)
^
syscfg/ti_enet_soc.c:342:13: note: previous definition is here
Enet_Handle EnetSoc_getEnetHandleByIdx(uint32_t idx)
^
syscfg/ti_enet_soc.c:1338:13: error: redefinition of 'EnetSoc_getEnetHandle'
Enet_Handle EnetSoc_getEnetHandle(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:355:13: note: previous definition is here
Enet_Handle EnetSoc_getEnetHandle(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:1401:14: error: redefinition of 'EnetSoc_isValidEnetType'
static bool EnetSoc_isValidEnetType(Enet_Type enetType)
^
syscfg/ti_enet_soc.c:379:14: note: previous definition is here
static bool EnetSoc_isValidEnetType(Enet_Type enetType)
^
syscfg/ti_enet_soc.c:1413:10: error: redefinition of 'EnetSoc_getEnetNum'
uint32_t EnetSoc_getEnetNum(void)
^
syscfg/ti_enet_soc.c:390:10: note: previous definition is here
uint32_t EnetSoc_getEnetNum(void)
^
syscfg/ti_enet_soc.c:1418:10: error: redefinition of 'EnetSoc_getMacPortMax'
uint32_t EnetSoc_getMacPortMax(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:395:10: note: previous definition is here
uint32_t EnetSoc_getMacPortMax(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:1439:10: error: redefinition of 'EnetSoc_isIpSupported'
uint32_t EnetSoc_isIpSupported(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:412:10: note: previous definition is here
uint32_t EnetSoc_isIpSupported(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:1455:10: error: redefinition of 'EnetSoc_getCoreId'
uint32_t EnetSoc_getCoreId(void)
^
syscfg/ti_enet_soc.c:427:10: note: previous definition is here
uint32_t EnetSoc_getCoreId(void)
^
syscfg/ti_enet_soc.c:1462:10: error: redefinition of 'EnetSoc_getClkFreq'
uint32_t EnetSoc_getClkFreq(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:444:10: note: previous definition is here
uint32_t EnetSoc_getClkFreq(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:1486:10: error: redefinition of 'EnetSoc_getIntrTriggerType'
uint32_t EnetSoc_getIntrTriggerType(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:554:10: note: previous definition is here
uint32_t EnetSoc_getIntrTriggerType(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:1495:9: error: redefinition of 'EnetSoc_getEFusedMacAddrs'
int32_t EnetSoc_getEFusedMacAddrs(uint8_t macAddr[][ENET_MAC_ADDR_LEN],
^
syscfg/ti_enet_soc.c:563:9: note: previous definition is here
int32_t EnetSoc_getEFusedMacAddrs(uint8_t macAddr[][ENET_MAC_ADDR_LEN],
^
syscfg/ti_enet_soc.c:1530:10: error: redefinition of 'EnetSoc_getMacPortCaps'
uint32_t EnetSoc_getMacPortCaps(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:598:10: note: previous definition is here
uint32_t EnetSoc_getMacPortCaps(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:1557:9: error: redefinition of 'EnetSoc_getMacPortMii'
int32_t EnetSoc_getMacPortMii(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:623:9: note: previous definition is here
int32_t EnetSoc_getMacPortMii(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:1565:9: error: redefinition of 'EnetSoc_validateQsgmiiCfg'
int32_t EnetSoc_validateQsgmiiCfg(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:708:9: note: previous definition is here
int32_t EnetSoc_validateQsgmiiCfg(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:1571:9: error: redefinition of 'EnetSoc_mapPort2QsgmiiId'
int32_t EnetSoc_mapPort2QsgmiiId(Enet_Type enetType,
^
syscfg/ti_enet_soc.c:714:9: note: previous definition is here
int32_t EnetSoc_mapPort2QsgmiiId(Enet_Type enetType,
^
fatal error: too many errors emitted, stopping now [-ferror-limit=]
6 warnings and 20 errors generated.
gmake: *** [syscfg/ti_enet_soc.o] Error 1
/*
* Copyright (c) Texas Instruments Incorporated 2020
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* \file ti_enet_soc.c
*
* \brief This file contains enet soc config related functionality.
*/
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
#include <string.h>
#include <stdint.h>
#include <stdarg.h>
#include <drivers/sciclient.h>
#include <enet.h>
#include <enet_cfg.h>
#include <priv/mod/cpsw_ale_priv.h>
#include <priv/mod/cpsw_cpts_priv.h>
#include <priv/mod/cpsw_hostport_priv.h>
#include <priv/mod/cpsw_macport_priv.h>
#include <priv/mod/cpsw_stats_priv.h>
#include <priv/mod/mdio_priv.h>
#include <priv/mod/cpsw_clks.h>
#include <priv/core/enet_rm_priv.h>
#include <include/core/enet_utils.h>
#include <include/core/enet_osal.h>
#include <include/core/enet_soc.h>
#include <include/core/enet_per.h>
#include <include/per/cpsw.h>
#include <src/dma/udma/enet_udma_priv.h>
#include <soc/k3/cpsw_soc.h>
#include <priv/per/cpsw_priv.h>
#include <utils/include/enet_appsoc.h>
#include <drivers/hw_include/cslr_soc.h>
#include "ti_enet_config.h"
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
/* ========================================================================== */
/* Structure Declarations */
/* ========================================================================== */
/* ========================================================================== */
/* Function Declarations */
/* ========================================================================== */
static uint32_t EnetSoc_getMcuEnetControl(Enet_MacPort macPort,
uint32_t *modeSel);
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/* -------------------------------- CPSW 3G --------------------------------- */
const CpswSoc_Cfg gEnetSoc_cpsw3gSocCfg =
{
/* As per the clocking specification the mcu_sysclk0 is 1000MHz with
* fixed /3 divider. */
.cppiClkFreqHz = 320000000LLU,
.dmscDevId = TISCI_DEV_CPSW0,
.intrs =
{
{ /* EVNT_PEND - Event pending interrupt (CPTS) */
.intrId = CPSW_INTR_EVNT_PEND,
.coreIntNum = CSLR_R5FSS0_CORE0_INTR_CPSW0_EVNT_PEND_0,
.srcIdx = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
},
{ /* STATS_PEND - Statistics pending interrupt */
.intrId = CPSW_INTR_STATS_PEND0,
.coreIntNum = CSLR_R5FSS0_CORE0_INTR_CPSW0_STAT_PEND_0,
.srcIdx = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
},
{ /* MDIO_PEND - MDIO interrupt */
.intrId = CPSW_INTR_MDIO_PEND,
.coreIntNum = CSLR_R5FSS0_CORE0_INTR_CPSW0_MDIO_PEND_0,
.srcIdx = ENET_SOC_DIRECT_INTR_SRCIDX_INVALID,
},
},
.clocks =
{
.cppiClkId = TISCI_DEV_CPSW0_CPPI_CLK_CLK,
.rgmii250MHzClkId = TISCI_DEV_CPSW0_RGMII_MHZ_250_CLK,
.rgmii50MHzClkId = TISCI_DEV_CPSW0_RGMII_MHZ_50_CLK,
.rgmii5MHzClkId = TISCI_DEV_CPSW0_RGMII_MHZ_5_CLK,
},
.txChPeerThreadId = CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_OFFSET,
.rxChPeerThreadId = CSL_PSILCFG_DMSS_CPSW2_PSILS_THREAD_OFFSET,
.txChCount = CSL_PSILCFG_DMSS_CPSW2_PSILD_THREAD_CNT,
/* Note- Though CPSW supports 64 distinct flow Ids, there are only
* 8 policer/classifier so can effectively assign only 8 flow ids in CPSW3G */
.rxFlowCount = 8U,
};
/* CPSW_3G MAC port template */
#define ENET_SOC_CPSW3G_MACPORT(n) \
{ \
.enetMod = \
{ \
.name = "cpsw3G.macport" #n, \
.physAddr = (CSL_CPSW0_NUSS_BASE + CPSW_NU_OFFSET), \
.physAddr2 = (CSL_CPSW0_NUSS_BASE + CPSW_SGMII0_OFFSET(0U)), \
.features = (ENET_FEAT_BASE | \
CPSW_MACPORT_FEATURE_EST | \
CPSW_MACPORT_FEATURE_SGMII | \
CPSW_MACPORT_FEATURE_INTERVLAN), \
.errata = ENET_ERRATA_NONE, \
.open = &CpswMacPort_open, \
.rejoin = &CpswMacPort_rejoin, \
.ioctl = &CpswMacPort_ioctl, \
.close = &CpswMacPort_close, \
}, \
.macPort = ENET_MAC_PORT_ ## n, \
}
/* CPSW_3G MAC ports */
CpswMacPort_Obj gEnetSoc_cpsw3gMacObj[] =
{
ENET_SOC_CPSW3G_MACPORT(1),
ENET_SOC_CPSW3G_MACPORT(2),
};
/* CPSW 3G Peripheral */
Cpsw_Obj gEnetSoc_cpsw3g =
{
.enetPer =
{
.name = "cpsw3g",
.enetType = ENET_CPSW_3G,
.instId = 0U,
.magic = ENET_NO_MAGIC,
.physAddr = (CSL_CPSW0_NUSS_BASE + CPSW_NU_OFFSET),
.physAddr2 = (CSL_CPSW0_NUSS_BASE + CPSW_NUSS_OFFSET),
.features = (ENET_FEAT_BASE |
CPSW_FEATURE_EST |
CPSW_FEATURE_INTERVLAN),
.errata = ENET_ERRATA_NONE,
.initCfg = &Cpsw_initCfg,
.open = &Cpsw_open,
.rejoin = &Cpsw_rejoin,
.ioctl = &Cpsw_ioctl,
.poll = &Cpsw_poll,
.convertTs = NULL,
.periodicTick = &Cpsw_periodicTick,
.registerEventCb = NULL,
.unregisterEventCb = NULL,
.close = &Cpsw_close,
},
/* Host port module object */
.hostPortObj =
{
.enetMod =
{
.name = "cpsw3g.hostport",
.physAddr = (CSL_CPSW0_NUSS_BASE + CPSW_NU_OFFSET),
.features = ENET_FEAT_BASE,
.errata = ENET_ERRATA_NONE,
.open = &CpswHostPort_open,
.rejoin = &CpswHostPort_rejoin,
.ioctl = &CpswHostPort_ioctl,
.close = &CpswHostPort_close,
}
},
/* MAC port module objects */
.macPortObj = gEnetSoc_cpsw3gMacObj,
.macPortNum = ENET_ARRAYSIZE(gEnetSoc_cpsw3gMacObj),
/* ALE module object */
.aleObj =
{
.enetMod =
{
.name = "cpsw3g.ale",
.physAddr = (CSL_CPSW0_NUSS_BASE + CPSW_ALE_OFFSET),
.features = (ENET_FEAT_BASE |
CPSW_ALE_FEATURE_FLOW_PRIORITY |
CPSW_ALE_FEATURE_IP_HDR_WHITELIST),
.errata = ENET_ERRATA_NONE,
.open = &CpswAle_open,
.rejoin = &CpswAle_rejoin,
.ioctl = &CpswAle_ioctl,
.close = &CpswAle_close,
},
},
/* CPTS module object */
.cptsObj =
{
.enetMod =
{
.name = "cpsw3g.cpts",
.physAddr = (CSL_CPSW0_NUSS_BASE + CPSW_CPTS_OFFSET),
.features = ENET_FEAT_BASE,
.errata = ENET_ERRATA_NONE,
.open = &CpswCpts_open,
.rejoin = &CpswCpts_rejoin,
.ioctl = &CpswCpts_ioctl,
.close = &CpswCpts_close,
},
.hwPushCnt = 8U,
},
/* MDIO module object */
.mdioObj =
{
.enetMod =
{
.name = "cpsw3g.mdio",
.physAddr = (CSL_CPSW0_NUSS_BASE + CPSW_MDIO_OFFSET),
.features = (ENET_FEAT_BASE |
MDIO_FEATURE_CLAUSE45),
.errata = ENET_ERRATA_NONE,
.open = &Mdio_open,
.rejoin = &Mdio_rejoin,
.ioctl = &Mdio_ioctl,
.close = &Mdio_close,
},
},
/* Statistics module object */
.statsObj =
{
.enetMod =
{
.name = "cpsw3g.stats",
.physAddr = (CSL_CPSW0_NUSS_BASE + CPSW_NU_OFFSET),
.features = ENET_FEAT_BASE,
.errata = ENET_ERRATA_NONE,
.open = &CpswStats_open,
.rejoin = &CpswStats_rejoin,
.ioctl = &CpswStats_ioctl,
.close = &CpswStats_close,
},
},
/* RM module object */
.rmObj =
{
.enetMod =
{
.name = "cpsw3g.rm",
.physAddr = 0U,
.features = ENET_FEAT_BASE,
.errata = ENET_ERRATA_NONE,
.open = &EnetRm_open,
.rejoin = &EnetRm_rejoin,
.ioctl = &EnetRm_ioctl,
.close = &EnetRm_close,
},
},
};
/* ---------------------------- Enet Peripherals ---------------------------- */
Enet_Obj gEnetSoc_perObj[] =
{
/* CPSW_3G Enet driver/peripheral */
{
.enetPer = &gEnetSoc_cpsw3g.enetPer,
},
};
EnetUdma_DrvObj gEnetSoc_dmaObj[ENET_ARRAYSIZE(gEnetSoc_perObj)];
EnetUdma_DrvObjMemInfo gEnetSoc_dmaObjMemInfo =
{
.numObjs = ENET_ARRAYSIZE(gEnetSoc_dmaObj),
.drvObjMem = &gEnetSoc_dmaObj[0],
};
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
int32_t EnetSoc_init(void)
{
return ENET_SOK;
}
void EnetSoc_deinit(void)
{
}
EnetDma_Handle EnetSoc_getDmaHandle(Enet_Type enetType,
uint32_t instId)
{
EnetDma_Handle hDma = NULL;
switch (enetType)
{
case ENET_CPSW_3G:
if (instId == 0U)
{
hDma = &gEnetSoc_dmaObjMemInfo.drvObjMem[0U];
}
break;
default:
break;
}
EnetSoc_assert(hDma != NULL, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
return hDma;
}
Enet_Handle EnetSoc_getEnetHandleByIdx(uint32_t idx)
{
Enet_Handle hEnet = NULL;
if (idx < ENET_ARRAYSIZE(gEnetSoc_perObj))
{
hEnet = &gEnetSoc_perObj[idx];
}
EnetSoc_assert((hEnet != NULL), "Unsupported peripheral index (index=%u )\n", idx);
return hEnet;
}
Enet_Handle EnetSoc_getEnetHandle(Enet_Type enetType,
uint32_t instId)
{
Enet_Handle hEnet = NULL;
switch (enetType)
{
case ENET_CPSW_3G:
if (instId == 0U)
{
hEnet = &gEnetSoc_perObj[0U];
}
break;
default:
{
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
}
break;
}
EnetSoc_assert((hEnet != NULL), "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
return hEnet;
}
static bool EnetSoc_isValidEnetType(Enet_Type enetType)
{
bool validInstanceType = false;
if (enetType == ENET_CPSW_3G)
{
validInstanceType = true;
}
return validInstanceType;
}
uint32_t EnetSoc_getEnetNum(void)
{
return ENET_ARRAYSIZE(gEnetSoc_perObj);
}
uint32_t EnetSoc_getMacPortMax(Enet_Type enetType,
uint32_t instId)
{
uint32_t numPorts = 0U;
if ((enetType == ENET_CPSW_3G) && (instId == 0U))
{
numPorts = 2;
}
else
{
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
}
return numPorts;
}
uint32_t EnetSoc_isIpSupported(Enet_Type enetType,
uint32_t instId)
{
bool supported = false;
if ((enetType == ENET_CPSW_3G) && (0U == instId))
{
supported = true;
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet & instId type %d, %d\n", enetType, instId);
return supported;
}
uint32_t EnetSoc_getCoreId(void)
{
uint32_t coreId = CSL_CORE_ID_R5FSS0_0;
return coreId;
}
static uint32_t EnetSoc_getCoreDevId(void)
{
uint32_t coreDevId;
coreDevId = TISCI_DEV_R5FSS0_CORE0;
return coreDevId;
}
uint32_t EnetSoc_getClkFreq(Enet_Type enetType,
uint32_t instId,
uint32_t clkId)
{
uint32_t freq = 0U;
if (clkId == CPSW_CPPI_CLK)
{
if ((enetType == ENET_CPSW_3G) && (instId == 0U))
{
freq = gEnetSoc_cpsw3gSocCfg.cppiClkFreqHz;
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
}
else
{
EnetSoc_assert(false, "Invalid clk id %u\n", clkId);
}
return freq;
}
int32_t EnetSoc_setupIntrCfg(Enet_Type enetType,
uint32_t instId,
uint32_t intrId)
{
const EnetSoc_IntrConnCfg *socIntrs = NULL;
uint32_t numSocIntrs = 0U;
uint16_t coreDevId = EnetSoc_getCoreDevId();
uint16_t perDevId = 0U;
int32_t status = ENET_SOK;
if ((enetType == ENET_CPSW_3G) && (instId == 0U))
{
perDevId = gEnetSoc_cpsw3gSocCfg.dmscDevId;
socIntrs = gEnetSoc_cpsw3gSocCfg.intrs;
numSocIntrs = ENET_ARRAYSIZE(gEnetSoc_cpsw3gSocCfg.intrs);
}
else
{
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
status = ENET_EINVALIDPARAMS;
}
if (status == ENET_SOK)
{
status = EnetSocJ7x_setupIntrCfg(intrId, coreDevId, perDevId, socIntrs, numSocIntrs);
}
return status;
}
int32_t EnetSoc_releaseIntrCfg(Enet_Type enetType,
uint32_t instId,
uint32_t intrId)
{
const EnetSoc_IntrConnCfg *socIntrs = NULL;
uint32_t numSocIntrs = 0U;
uint16_t coreDevId = EnetSoc_getCoreDevId();
uint16_t perDevId = 0U;
int32_t status = ENET_SOK;
if ((enetType == ENET_CPSW_3G) && (instId == 0U))
{
perDevId = gEnetSoc_cpsw3gSocCfg.dmscDevId;
socIntrs = gEnetSoc_cpsw3gSocCfg.intrs;
numSocIntrs = ENET_ARRAYSIZE(gEnetSoc_cpsw3gSocCfg.intrs);
}
else
{
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
status = ENET_EINVALIDPARAMS;
}
if (status == ENET_SOK)
{
status = EnetSocJ7x_releaseIntrCfg(intrId, coreDevId, perDevId, socIntrs, numSocIntrs);
}
return status;
}
uint32_t EnetSoc_getIntrNum(Enet_Type enetType,
uint32_t instId,
uint32_t intrId)
{
const EnetSoc_IntrConnCfg *socIntrs = NULL;
uint32_t numSocIntrs = 0U;
uint32_t intrNum = 0U;
int32_t status = ENET_SOK;
if ((enetType == ENET_CPSW_3G) && (instId == 0U))
{
socIntrs = gEnetSoc_cpsw3gSocCfg.intrs;
numSocIntrs = ENET_ARRAYSIZE(gEnetSoc_cpsw3gSocCfg.intrs);
}
else
{
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
status = ENET_EINVALIDPARAMS;
}
if (status == ENET_SOK)
{
intrNum = EnetSocJ7x_getIntrNum(intrId, socIntrs, numSocIntrs);
}
return intrNum;
}
uint32_t EnetSoc_getIntrTriggerType(Enet_Type enetType,
uint32_t instId,
uint32_t intrId)
{
return ENETOSAL_ARM_GIC_TRIG_TYPE_LEVEL;
}
/* Stupid hack to workaround FAE board issues */
//#define ENET_MAC_ADDR_HACK (TRUE)
int32_t EnetSoc_getEFusedMacAddrs(uint8_t macAddr[][ENET_MAC_ADDR_LEN],
uint32_t *num)
{
#ifndef ENET_MAC_ADDR_HACK
CSL_main_ctrl_mmr_cfg0Regs *mmrRegs;
uint32_t val;
if (*num >= 1U)
{
mmrRegs = (CSL_main_ctrl_mmr_cfg0Regs *)(uintptr_t)CSL_CTRL_MMR0_CFG0_BASE;
val = CSL_REG32_RD(&mmrRegs->MAC_ID0);
macAddr[0][5] = (uint8_t)((val & 0x000000FFU) >> 0U);
macAddr[0][4] = (uint8_t)((val & 0x0000FF00U) >> 8U);
macAddr[0][3] = (uint8_t)((val & 0x00FF0000U) >> 16U);
macAddr[0][2] = (uint8_t)((val & 0xFF000000U) >> 24U);
val = CSL_REG32_RD(&mmrRegs->MAC_ID1);
macAddr[0][1] = (uint8_t)((val & 0x000000FFU) >> 0U);
macAddr[0][0] = (uint8_t)((val & 0x0000FF00U) >> 8U);
*num = 1U;
}
#else
macAddr[0][0] = 0xF4;
macAddr[0][1] = 0x84;
macAddr[0][2] = 0x4c;
macAddr[0][3] = 0xf9;
macAddr[0][4] = 0x4d;
macAddr[0][5] = 0x29;
*num = 1U;
#endif
return ENET_SOK;
}
uint32_t EnetSoc_getMacPortCaps(Enet_Type enetType,
uint32_t instId,
Enet_MacPort macPort)
{
uint32_t linkCaps = 0U;
switch (enetType)
{
case ENET_CPSW_3G:
if (macPort <= ENET_MAC_PORT_2)
{
linkCaps = (ENETPHY_LINK_CAP_HD10 | ENETPHY_LINK_CAP_FD10 |
ENETPHY_LINK_CAP_HD100 | ENETPHY_LINK_CAP_FD100 |
ENETPHY_LINK_CAP_FD1000);
}
break;
default:
EnetSoc_assert(false, "Invalid peripheral type: %u\n", enetType);
break;
}
return linkCaps;
}
int32_t EnetSoc_getMacPortMii(Enet_Type enetType,
uint32_t instId,
Enet_MacPort macPort,
EnetMacPort_Interface *mii)
{
EnetMac_LayerType *enetLayer = &mii->layerType;
EnetMac_SublayerType *enetSublayer = &mii->sublayerType;
uint32_t modeSel = CPSW_ENET_CTRL_MODE_RGMII;
int32_t status = ENET_EFAIL;
switch (enetType)
{
case ENET_CPSW_3G:
status = EnetSoc_getMcuEnetControl(macPort, &modeSel);
break;
default:
EnetSoc_assert(false, "Invalid peripheral type: %u\n", enetType);
break;
}
if (status == ENET_SOK)
{
switch (modeSel)
{
/* RMII */
case CPSW_ENET_CTRL_MODE_RMII:
*enetLayer = ENET_MAC_LAYER_MII;
*enetSublayer = ENET_MAC_SUBLAYER_REDUCED;
break;
/* RGMII */
case CPSW_ENET_CTRL_MODE_RGMII:
*enetLayer = ENET_MAC_LAYER_GMII;
*enetSublayer = ENET_MAC_SUBLAYER_REDUCED;
break;
default:
status = ENET_EINVALIDPARAMS;
break;
}
}
return status;
}
static uint32_t EnetSoc_getMcuEnetControl(Enet_MacPort macPort,
uint32_t *modeSel)
{
CSL_main_ctrl_mmr_cfg0Regs *regs =
(CSL_main_ctrl_mmr_cfg0Regs *)(uintptr_t)CSL_CTRL_MMR0_CFG0_BASE;
int32_t status = ENET_SOK;
switch (macPort)
{
case ENET_MAC_PORT_1:
*modeSel = CSL_FEXT(regs->ENET1_CTRL, MAIN_CTRL_MMR_CFG0_ENET1_CTRL_PORT_MODE_SEL);
break;
case ENET_MAC_PORT_2:
*modeSel = CSL_FEXT(regs->ENET2_CTRL, MAIN_CTRL_MMR_CFG0_ENET2_CTRL_PORT_MODE_SEL);
break;
default:
status = ENET_EINVALIDPARAMS;
break;
}
if (status == ENET_SOK)
{
switch (*modeSel)
{
case CPSW_ENET_CTRL_MODE_RMII:
case CPSW_ENET_CTRL_MODE_RGMII:
break;
default:
status = ENET_EINVALIDPARAMS;
break;
}
}
return status;
}
int32_t EnetSoc_validateQsgmiiCfg(Enet_Type enetType,
uint32_t instId)
{
return ENET_ENOTSUPPORTED;
}
int32_t EnetSoc_mapPort2QsgmiiId(Enet_Type enetType,
uint32_t instId,
Enet_MacPort portNum,
uint32_t *qsgmiiId)
{
return ENET_ENOTSUPPORTED;
}
uint32_t EnetSoc_getRxFlowCount(Enet_Type enetType,
uint32_t instId)
{
uint32_t rxFlowCount = 0U;
/* Get SoC array index */
if (enetType == ENET_CPSW_3G)
{
rxFlowCount = gEnetSoc_cpsw3gSocCfg.rxFlowCount;
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
return rxFlowCount;
}
uint32_t EnetSoc_getTxChPeerId(Enet_Type enetType,
uint32_t instId,
uint32_t chNum)
{
uint32_t peerChNum = 0U;
/* Get SoC array index */
if (enetType == ENET_CPSW_3G)
{
peerChNum = gEnetSoc_cpsw3gSocCfg.txChPeerThreadId;
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
/* Get PSI-L destination thread offset for Tx channel */
peerChNum = (peerChNum + chNum);
return peerChNum;
}
uint32_t EnetSoc_getRxChPeerId(Enet_Type enetType,
uint32_t instId,
uint32_t chIdx)
{
uint32_t peerChNum = 0U;
/* Get SoC array index */
if (enetType == ENET_CPSW_3G)
{
peerChNum = gEnetSoc_cpsw3gSocCfg.rxChPeerThreadId;
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
return peerChNum;
}
uint32_t EnetSoc_getTxChCount(Enet_Type enetType,
uint32_t instId)
{
uint32_t txChCount = 0U;
/* Get SoC array index */
if (enetType == ENET_CPSW_3G)
{
txChCount = gEnetSoc_cpsw3gSocCfg.txChCount;
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
return txChCount;
}
/*!
* \brief CPSW3G default configuration
*
* Note: If user wishes to change the Resource Partition the following
* things must be considered:
* 1. Sum of numTxCh allocated to each core should not exceed 8.
* 2. Sum of numRxFlows allocated to each core should not exceed 7 (not 8),
* as one Rx flow is reserved to the master core.
*
*/
static EnetRm_ResPrms gEnetAppRmDefCfg_3G =
{
.coreDmaResInfo =
{
[0] =
{
.coreId = CSL_CORE_ID_R5FSS0_0,
.numTxCh = ENET_SYSCFG_TX_CHANNELS_NUM, /* numTxCh */
.numRxFlows = (ENET_SYSCFG_RX_FLOWS_NUM + 1), /* numRxFlows. Need one additional flow for reserved flow */
.numMacAddress = 4U, /* numMacAddress */
},
},
.numCores = 1U,
};
const EnetRm_ResPrms *EnetAppRm_getResPartInfo(Enet_Type enetType)
{
const EnetRm_ResPrms *rmInitPrms = NULL;
switch (enetType)
{
case ENET_CPSW_3G:
{
rmInitPrms = &gEnetAppRmDefCfg_3G;
break;
}
default:
{
rmInitPrms = NULL;
}
}
return(rmInitPrms);
}
/* Cores IOCTL Privileges */
static const EnetRm_IoctlPermissionTable gEnetAppIoctlPermission_3G =
{
.defaultPermittedCoreMask = (ENET_BIT(CSL_CORE_ID_A53SS0_0) |
ENET_BIT(CSL_CORE_ID_R5FSS0_0) |
ENET_BIT(CSL_CORE_ID_R5FSS0_1) |
ENET_BIT(CSL_CORE_ID_R5FSS1_0) |
ENET_BIT(CSL_CORE_ID_R5FSS1_1)),
.numEntries = 0,
};
const EnetRm_IoctlPermissionTable *EnetAppRm_getIoctlPermissionInfo(Enet_Type enetType)
{
const EnetRm_IoctlPermissionTable *ioctlPerm = NULL;
switch (enetType)
{
case ENET_CPSW_3G:
{
ioctlPerm = &gEnetAppIoctlPermission_3G;
break;
}
default:
{
ioctlPerm = NULL;
break;
}
}
return(ioctlPerm);
}
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
#include <stdint.h>
#include <stdarg.h>
#include <drivers/sciclient.h>
#include <drivers/hw_include/cslr_soc.h>
#include <hw_include/cslr_icss.h>
#include <priv/mod/cpsw_clks.h>
#include <enet.h>
#include <soc/k3/cpsw_soc.h>
#include <enet_cfg.h>
#include <priv/mod/mdio_priv.h>
#include <priv/core/enet_rm_priv.h>
#include <include/core/enet_utils.h>
#include <include/core/enet_osal.h>
#include <include/core/enet_soc.h>
#include <include/core/enet_per.h>
#include <include/per/icssg.h>
#include <priv/per/icssg_priv.h>
#include <soc/k3/icssg_soc.h>
#include <src/dma/udma/enet_udma_priv.h>
#pragma clang section rodata=".icssfw"
#include <networking/enet/core/src/per/firmware/icssg/dualmac/RX_PRU_SLICE0_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/dualmac/RX_PRU_SLICE1_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/dualmac/RTU0_SLICE0_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/dualmac/RTU0_SLICE1_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/dualmac/TX_PRU_SLICE0_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/dualmac/TX_PRU_SLICE1_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/switch/RX_PRU_SLICE0_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/switch/RX_PRU_SLICE1_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/switch/RTU0_SLICE0_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/switch/RTU0_SLICE1_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/switch/TX_PRU_SLICE0_bin.h>
#include <networking/enet/core/src/per/firmware/icssg/switch/TX_PRU_SLICE1_bin.h>
#pragma clang section rodata=""
#include "ti_enet_config.h"
/* ========================================================================== */
/* Global Variables */
/* ========================================================================== */
/*DUAL MAC MODE*/
/*
* ICSSG Port buffer pool memory:
* - Dual-MAC: Not needed
*/
#define ICSSG_PORT_POOL_TOTAL_SIZE (0U)
/*
* ICSSG Host buffer pool memory:
* - Dual-MAC:
* Gigabit Support: No of pools based on QOS level and 8kB each
* 100M Support: No of pools based on QOS level and 4kB each
*/
#define ICSSG_DUALMAC_HOST_POOL_SIZE ((ENET_SYSCFG_ENABLE_GIGABIT) ? ENET_UTILS_ALIGN((8 * 1024U),ICSSG_CACHELINE_ALIGNMENT) : ENET_UTILS_ALIGN((4 * 1024U),ICSSG_CACHELINE_ALIGNMENT))
#define ICSSG_DUALMAC_HOST_POOL_TOTAL_SIZE (ICSSG_DUALMAC_HOST_BUFFER_POOL_NUM_CFG * ICSSG_DUALMAC_HOST_POOL_SIZE)
#define ICSSG_HOST_POOL_TOTAL_SIZE (ICSSG_DUALMAC_HOST_POOL_TOTAL_SIZE)
/*
* ICSSG Host egress queue memory:
* - Dual-MAC:
* Gigabit Support: 2 queues of (6kB + 2kB) each
* 100M Support: 2 queues of (3kB + 2kB) each
*/
#define ICSSG_DUALMAC_HOST_QUEUE_SIZE ((ENET_SYSCFG_ENABLE_GIGABIT) ? ENET_UTILS_ALIGN((8 * 1024U),ICSSG_CACHELINE_ALIGNMENT) : ENET_UTILS_ALIGN((5 * 1024U),ICSSG_CACHELINE_ALIGNMENT))
#define ICSSG_DUALMAC_HOST_QUEUE_TOTAL_SIZE ((ICSSG_DUALMAC_HOST_EGRESS_QUEUE_NUM * ICSSG_DUALMAC_HOST_QUEUE_SIZE) + ENET_UTILS_ALIGN(ICSSG_HOST_EGRESS_BUFFER_PADDING,ICSSG_CACHELINE_ALIGNMENT))
#define ICSSG_HOST_QUEUE_TOTAL_SIZE (ICSSG_DUALMAC_HOST_QUEUE_TOTAL_SIZE)
#define ICSSG_PRE_QUEUE_TOTAL_SIZE ((ENET_SYSCFG_PREMPTION_ENABLE) ? (ICSSG_DUALMAC_HOST_QUEUE_TOTAL_SIZE) : 0)
/* --------------------------------- ICSS-G --------------------------------- */
/* ICSSG1 memories */
static uint8_t gEnetSoc_icssg1HostPoolMem_0[ICSSG_HOST_POOL_TOTAL_SIZE]
__attribute__ ((aligned (ICSSG_CACHELINE_ALIGNMENT)));
static uint8_t gEnetSoc_icssg1HostQueueMem_0[ICSSG_HOST_QUEUE_TOTAL_SIZE]
__attribute__ ((aligned (ICSSG_CACHELINE_ALIGNMENT)));
static uint8_t gEnetSoc_icssg1ScratchMem_0[ICSSG_SCRATCH_BUFFER_SIZE]
__attribute__ ((aligned (ICSSG_CACHELINE_ALIGNMENT)));
static Icssg_FwPoolMem gEnetSoc_Icssg1_0_FwPoolMem[] =
{
[0] =
{
.portBufferPoolMem = NULL,
.portBufferPoolSize = 0U,
.portBufferPoolNum = 0U,
.hostBufferPoolMem = gEnetSoc_icssg1HostPoolMem_0,
.hostBufferPoolSize = ICSSG_DUALMAC_HOST_POOL_SIZE,
.hostBufferPoolNum = ICSSG_DUALMAC_HOST_BUFFER_POOL_NUM_CFG,
.hostEgressQueueMem = gEnetSoc_icssg1HostQueueMem_0,
.hostEgressQueueSize = ICSSG_DUALMAC_HOST_QUEUE_SIZE,
.hostEgressPreQueueMem = NULL,
.hostEgressPreQueueSize = ICSSG_PRE_QUEUE_TOTAL_SIZE,
.hostEgressQueueNum = ICSSG_DUALMAC_HOST_EGRESS_QUEUE_NUM,
.scratchBufferMem = gEnetSoc_icssg1ScratchMem_0,
.scratchBufferSize = ICSSG_SCRATCH_BUFFER_SIZE,
},
};
/* PRU_ICSSG 0 */
Icssg_Pruss gEnetSoc_PruIcssg0 =
{
.instance = ICSSG_PRUSS_ID_0,
.initialized = false,
.iep0InUse = false,
};
/* PRU_ICSSG 1 */
Icssg_Pruss gEnetSoc_PruIcssg1 =
{
.instance = ICSSG_PRUSS_ID_1,
.initialized = false,
.iep0InUse = false,
};
/* ICSSG1 Dual-MAC Port 1 (ENET_ICSSG_DUALMAC, 2) */
static Icssg_Obj gEnetSoc_icssg1DMacp1 =
{
.enetPer =
{
.name = "icssg1-1",
.enetType = ENET_ICSSG_DUALMAC,
.instId = 2U,
.magic = ENET_NO_MAGIC,
.physAddr = CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE,
.physAddr2 = 0U,
.features = ENET_FEAT_BASE,
.errata = ENET_ERRATA_NONE,
.initCfg = &Icssg_initCfg,
.open = &Icssg_open,
.close = &Icssg_close,
.rejoin = &Icssg_rejoin,
.ioctl = &Icssg_ioctl,
.poll = &Icssg_poll,
.convertTs = &Icssg_convertTs,
.periodicTick = &Icssg_periodicTick,
.registerEventCb = &Icssg_registerEventCb,
.unregisterEventCb = &Icssg_unregisterEventCb,
},
/* Shared between ICSSG1 Port 1 and Port 2 objects */
.pruss = &gEnetSoc_PruIcssg1,
/* Dual-MAC firmware for slice 0 */
.fw =
{
{
.pru = RX_PRU_SLICE0_b00_DMac,
.pruSize = sizeof(RX_PRU_SLICE0_b00_DMac),
.rtu = RTU0_SLICE0_b00_DMac,
.rtuSize = sizeof(RTU0_SLICE0_b00_DMac),
.txpru = TX_PRU_SLICE0_b00_DMac,
.txpruSize = sizeof(TX_PRU_SLICE0_b00_DMac)
},
},
/* TimeSync module object */
.timeSyncObj =
{
.enetMod =
{
.name = "icssg1-1.timesync",
.physAddr = CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_PR1_IEP0_SLV_REGS_BASE,
.physAddr2 = CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE,
.features = ENET_FEAT_BASE,
.errata = ENET_ERRATA_NONE,
.open = &IcssgTimeSync_open,
.rejoin = &IcssgTimeSync_rejoin,
.ioctl = &IcssgTimeSync_ioctl,
.close = &IcssgTimeSync_close,
},
},
/* MDIO module object */
.mdioObj =
{
.enetMod =
{
.name = "icssg1-1.mdio",
.physAddr = CSL_PRU_ICSSG1_PR1_MDIO_V1P7_MDIO_BASE,
.features = MDIO_FEATURE_CLAUSE45,
.errata = ENET_ERRATA_NONE,
.open = &Mdio_open,
.rejoin = &Mdio_rejoin,
.ioctl = &Mdio_ioctl,
.close = &Mdio_close,
},
},
/* Stats module object */
.statsObj =
{
.enetMod =
{
.name = "icssg1-1.stats",
.physAddr = CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE,
.physAddr2 = 0,
.features = ENET_FEAT_BASE,
.errata = ENET_ERRATA_NONE,
.open = &IcssgStats_open,
.rejoin = &IcssgStats_rejoin,
.ioctl = &IcssgStats_ioctl,
.close = &IcssgStats_close,
},
},
/* Tas module object */
.tasObj =
{
{
.enetMod =
{
.name = "icssg1-1.tas",
.physAddr = CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE,
.physAddr2 = CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE + CSL_ICSS_G_RAM_SLV_RAM_REGS_BASE,
.features = ENET_FEAT_BASE,
.errata = ENET_ERRATA_NONE,
.open = &IcssgTas_open,
.rejoin = &IcssgTas_rejoin,
.ioctl = &IcssgTas_ioctl,
.close = &IcssgTas_close,
},
},
},
/* RM module object */
.rmObj =
{
.enetMod =
{
.name = "icssg1-1.rm",
.physAddr = 0U,
.features = ENET_FEAT_BASE,
.errata = ENET_ERRATA_NONE,
.open = &EnetRm_open,
.rejoin = &EnetRm_rejoin,
.ioctl = &EnetRm_ioctl,
.close = &EnetRm_close,
},
},
};
/* ---------------------------- Enet Peripherals ---------------------------- */
Enet_Obj gEnetSoc_perObj[] =
{
/* CPSW_3G Enet driver/peripheral */
{
.enetPer = NULL,
},
/* ICSSG0 Dual-MAC Port 1 Enet driver/peripheral */
{
.enetPer = NULL,
},
{
.enetPer = NULL,
},
{
/* ICSSG1 Dual-MAC Port 1 Enet driver/peripheral */
.enetPer = &gEnetSoc_icssg1DMacp1.enetPer,
},
{
.enetPer = NULL,
},
{
.enetPer = NULL,
},
{
.enetPer = NULL,
},
};
EnetUdma_DrvObj gEnetSoc_dmaObj[1U];
/* ICSSG1 Dual-MAC DMA SoC data: 4 TX channels and 9 RX flows per slice */
const IcssgSoc_Cfg gEnetSoc_icssg1DMacSocCfg[ICSSG_MAC_PORT_MAX] =
{
{
.dmscDevId = TISCI_DEV_PRU_ICSSG1,
.txChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_OFFSET,
.rxChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_OFFSET,
.txChCount = ICSSG_DUALMAC_TX_CH_NUM,
.rxFlowCount = ICSSG_DUALMAC_RX_FLOW_NUM,
},
{
.dmscDevId = TISCI_DEV_PRU_ICSSG1,
.txChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_OFFSET +
ICSSG_DUALMAC_TX_CH_NUM,
.rxChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_OFFSET +
1U,
.txChCount = ICSSG_DUALMAC_TX_CH_NUM,
.rxFlowCount = ICSSG_DUALMAC_RX_FLOW_NUM,
}
};
/* ICSSG1 Switch DMA SoC data: 4 TX channels and 9 RX flows */
const IcssgSoc_Cfg gEnetSoc_icssg1SwtSocCfg =
{
.dmscDevId = TISCI_DEV_PRU_ICSSG1,
.txChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G1_PSILD_THREAD_OFFSET,
.rxChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G1_PSILS_THREAD_OFFSET,
.txChCount = ICSSG_SWITCH_TX_CH_NUM,
.rxFlowCount = ICSSG_SWITCH_RX_FLOW_NUM,
};
/* ICSSG0 Dual-MAC DMA SoC data: 4 TX channels and 9 RX flows per slice */
const IcssgSoc_Cfg gEnetSoc_icssg0DMacSocCfg[ICSSG_MAC_PORT_MAX] =
{
{
.dmscDevId = TISCI_DEV_PRU_ICSSG0,
.txChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_OFFSET,
.rxChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_OFFSET,
.txChCount = ICSSG_DUALMAC_TX_CH_NUM,
.rxFlowCount = ICSSG_DUALMAC_RX_FLOW_NUM,
},
{
.dmscDevId = TISCI_DEV_PRU_ICSSG0,
.txChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_OFFSET +
ICSSG_DUALMAC_TX_CH_NUM,
.rxChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_OFFSET +
1U,
.txChCount = ICSSG_DUALMAC_TX_CH_NUM,
.rxFlowCount = ICSSG_DUALMAC_RX_FLOW_NUM,
},
};
/* ICSSG0 Switch DMA SoC data: 4 TX channels and 9 RX flows */
const IcssgSoc_Cfg gEnetSoc_icssg0SwtSocCfg =
{
.dmscDevId = TISCI_DEV_PRU_ICSSG0,
.txChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G0_PSILD_THREAD_OFFSET,
.rxChPeerThreadId = CSL_PSILCFG_DMSS_ICSS_G0_PSILS_THREAD_OFFSET,
.txChCount = ICSSG_SWITCH_TX_CH_NUM,
.rxFlowCount = ICSSG_SWITCH_RX_FLOW_NUM,
};
const Icssg_FwPoolMem *Icssq_FwPoolMemInfo[2][4] =
{
[0] = {
[0] = NULL,
[1] = NULL,
[2] = &gEnetSoc_Icssg1_0_FwPoolMem[0],
[3] = NULL,
},
[1] = {
[0] = NULL,
[1] = NULL,
[2] = NULL,
[3] = NULL,
},
};
/* ------------------------------- DMA objects ------------------------------ */
EnetUdma_DrvObjMemInfo gEnetSoc_dmaObjMemInfo =
{
.numObjs = ENET_ARRAYSIZE(gEnetSoc_dmaObj),
.drvObjMem = &gEnetSoc_dmaObj[0],
};
/* ========================================================================== */
/* Function Definitions */
/* ========================================================================== */
extern Icssg_Pruss gEnetSoc_PruIcssg0;
extern Icssg_Pruss gEnetSoc_PruIcssg1;
extern EnetUdma_DrvObjMemInfo gEnetSoc_dmaObjMemInfo;
int32_t EnetSoc_init(void)
{
memset(gEnetSoc_dmaObjMemInfo.drvObjMem, 0,
gEnetSoc_dmaObjMemInfo.numObjs * sizeof(*(gEnetSoc_dmaObjMemInfo.drvObjMem)));
gEnetSoc_PruIcssg0.lock = EnetOsal_createMutex();
EnetSoc_assert((gEnetSoc_PruIcssg0.lock != NULL),
"Failed to create PRUICSSG0's mutex\n");
gEnetSoc_PruIcssg1.lock = EnetOsal_createMutex();
EnetSoc_assert((gEnetSoc_PruIcssg1.lock != NULL),
"Failed to create PRUICSSG1's mutex\n");
return ENET_SOK;
}
void EnetSoc_deinit(void)
{
gEnetSoc_PruIcssg1.initialized = false;
EnetOsal_deleteMutex(gEnetSoc_PruIcssg1.lock);
gEnetSoc_PruIcssg1.lock = NULL;
gEnetSoc_PruIcssg0.initialized = false;
EnetOsal_deleteMutex(gEnetSoc_PruIcssg0.lock);
gEnetSoc_PruIcssg0.lock = NULL;
}
EnetDma_Handle EnetSoc_getDmaHandle(Enet_Type enetType,
uint32_t instId)
{
EnetDma_Handle hDma = NULL;
switch (enetType)
{
case ENET_ICSSG_DUALMAC:
switch (instId)
{
case 2:
hDma = &gEnetSoc_dmaObjMemInfo.drvObjMem[0U];
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
break;
default:
break;
}
EnetSoc_assert(hDma != NULL, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
return hDma;
}
Enet_Handle EnetSoc_getEnetHandleByIdx(uint32_t idx)
{
Enet_Handle hEnet = NULL;
if (idx < ENET_ARRAYSIZE(gEnetSoc_perObj))
{
hEnet = &gEnetSoc_perObj[idx];
}
EnetSoc_assert((hEnet != NULL), "Unsupported peripheral index (index=%u )\n", idx);
return hEnet;
}
Enet_Handle EnetSoc_getEnetHandle(Enet_Type enetType,
uint32_t instId)
{
Enet_Handle hEnet = NULL;
switch (enetType)
{
case ENET_CPSW_3G:
if (instId == 0U)
{
hEnet = &gEnetSoc_perObj[0U];
}
break;
case ENET_ICSSG_DUALMAC:
switch (instId)
{
case 0:
hEnet = &gEnetSoc_perObj[1U];
break;
case 1:
hEnet = &gEnetSoc_perObj[2U];
break;
case 2:
hEnet = &gEnetSoc_perObj[3U];
break;
case 3:
hEnet = &gEnetSoc_perObj[4U];
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
break;
case ENET_ICSSG_SWITCH:
switch (instId)
{
case 0:
hEnet = &gEnetSoc_perObj[5U];
break;
case 1:
hEnet = &gEnetSoc_perObj[6U];
break;
case 2:
hEnet = &gEnetSoc_perObj[7U];
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
break;
default:
{
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
}
break;
}
EnetSoc_assert((hEnet != NULL), "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
return hEnet;
}
static bool EnetSoc_isValidEnetType(Enet_Type enetType)
{
bool validInstanceType = false;
if ((enetType == ENET_ICSSG_DUALMAC)|| (enetType == ENET_ICSSG_SWITCH))
{
validInstanceType = true;
}
return validInstanceType;
}
uint32_t EnetSoc_getEnetNum(void)
{
return ENET_ARRAYSIZE(gEnetSoc_perObj);
}
uint32_t EnetSoc_getMacPortMax(Enet_Type enetType,
uint32_t instId)
{
uint32_t numPorts = 0U;
if (enetType == ENET_ICSSG_DUALMAC)
{
numPorts = 1U;
}
else if (enetType == ENET_ICSSG_SWITCH)
{
numPorts = 2U;
}
else
{
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
}
return numPorts;
}
uint32_t EnetSoc_isIpSupported(Enet_Type enetType,
uint32_t instId)
{
bool supported = false;
if (((enetType == ENET_ICSSG_DUALMAC) && (instId < 3U)) ||
((enetType == ENET_ICSSG_SWITCH) && (instId < 3U)))
{
supported = true;
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet & instId type %d, %d\n", enetType, instId);
return supported;
}
uint32_t EnetSoc_getCoreId(void)
{
uint32_t coreId = CSL_CORE_ID_R5FSS0_0;
return coreId;
}
uint32_t EnetSoc_getClkFreq(Enet_Type enetType,
uint32_t instId,
uint32_t clkId)
{
uint32_t freq = 0U;
if (clkId == CPSW_CPPI_CLK)
{
if ((enetType == ENET_ICSSG_DUALMAC)|| (enetType == ENET_ICSSG_SWITCH))
{
//TODO: Freq is hard coded here.
freq = 320000000LLU;
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
}
else
{
EnetSoc_assert(false, "Invalid clk id %u\n", clkId);
}
return freq;
}
uint32_t EnetSoc_getIntrTriggerType(Enet_Type enetType,
uint32_t instId,
uint32_t intrId)
{
return ENETOSAL_ARM_GIC_TRIG_TYPE_LEVEL;
}
/* Stupid hack to workaround FAE board issues */
//#define ENET_MAC_ADDR_HACK (TRUE)
int32_t EnetSoc_getEFusedMacAddrs(uint8_t macAddr[][ENET_MAC_ADDR_LEN],
uint32_t *num)
{
#ifndef ENET_MAC_ADDR_HACK
CSL_main_ctrl_mmr_cfg0Regs *mmrRegs;
uint32_t val;
if (*num >= 1U)
{
mmrRegs = (CSL_main_ctrl_mmr_cfg0Regs *)(uintptr_t)CSL_CTRL_MMR0_CFG0_BASE;
val = CSL_REG32_RD(&mmrRegs->MAC_ID0);
macAddr[0][5] = (uint8_t)((val & 0x000000FFU) >> 0U);
macAddr[0][4] = (uint8_t)((val & 0x0000FF00U) >> 8U);
macAddr[0][3] = (uint8_t)((val & 0x00FF0000U) >> 16U);
macAddr[0][2] = (uint8_t)((val & 0xFF000000U) >> 24U);
val = CSL_REG32_RD(&mmrRegs->MAC_ID1);
macAddr[0][1] = (uint8_t)((val & 0x000000FFU) >> 0U);
macAddr[0][0] = (uint8_t)((val & 0x0000FF00U) >> 8U);
*num = 1U;
}
#else
macAddr[0][0] = 0xF4;
macAddr[0][1] = 0x84;
macAddr[0][2] = 0x4c;
macAddr[0][3] = 0xf9;
macAddr[0][4] = 0x4d;
macAddr[0][5] = 0x29;
*num = 1U;
#endif
return ENET_SOK;
}
uint32_t EnetSoc_getMacPortCaps(Enet_Type enetType,
uint32_t instId,
Enet_MacPort macPort)
{
uint32_t linkCaps = 0U;
switch (enetType)
{
case ENET_ICSSG_DUALMAC:
case ENET_ICSSG_SWITCH:
if (macPort <= ENET_MAC_PORT_2)
{
linkCaps = (ENETPHY_LINK_CAP_HD10 | ENETPHY_LINK_CAP_FD10 |
ENETPHY_LINK_CAP_HD100 | ENETPHY_LINK_CAP_FD100 |
ENETPHY_LINK_CAP_FD1000);
}
break;
default:
EnetSoc_assert(false, "Invalid peripheral type: %u\n", enetType);
break;
}
return linkCaps;
}
int32_t EnetSoc_getMacPortMii(Enet_Type enetType,
uint32_t instId,
Enet_MacPort macPort,
EnetMacPort_Interface *mii)
{
return ENET_ENOTSUPPORTED;
}
int32_t EnetSoc_validateQsgmiiCfg(Enet_Type enetType,
uint32_t instId)
{
return ENET_ENOTSUPPORTED;
}
int32_t EnetSoc_mapPort2QsgmiiId(Enet_Type enetType,
uint32_t instId,
Enet_MacPort portNum,
uint32_t *qsgmiiId)
{
return ENET_ENOTSUPPORTED;
}
uint32_t EnetSoc_getRxFlowCount(Enet_Type enetType,
uint32_t instId)
{
uint32_t rxFlowCount = 0U;
if (enetType == ENET_ICSSG_DUALMAC)
{
switch (instId)
{
case 0:
rxFlowCount = gEnetSoc_icssg0DMacSocCfg[0].rxFlowCount;
break;
case 1:
rxFlowCount = gEnetSoc_icssg0DMacSocCfg[1].rxFlowCount;
break;
case 2:
rxFlowCount = gEnetSoc_icssg1DMacSocCfg[0].rxFlowCount;
break;
case 3:
rxFlowCount = gEnetSoc_icssg1DMacSocCfg[1].rxFlowCount;
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
}
else if (enetType == ENET_ICSSG_SWITCH)
{
switch (instId)
{
case 0:
rxFlowCount = gEnetSoc_icssg0SwtSocCfg.rxFlowCount;
break;
case 1:
rxFlowCount = gEnetSoc_icssg1SwtSocCfg.rxFlowCount;
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
return rxFlowCount;
}
uint32_t EnetSoc_getTxChPeerId(Enet_Type enetType,
uint32_t instId,
uint32_t chNum)
{
uint32_t peerChNum = 0U;
if (enetType == ENET_ICSSG_DUALMAC)
{
switch (instId)
{
case 0:
peerChNum = gEnetSoc_icssg0DMacSocCfg[0].txChPeerThreadId;
break;
case 1:
peerChNum = gEnetSoc_icssg0DMacSocCfg[1].txChPeerThreadId;
break;
case 2:
peerChNum = gEnetSoc_icssg1DMacSocCfg[0].txChPeerThreadId;
break;
case 3:
peerChNum = gEnetSoc_icssg1DMacSocCfg[1].txChPeerThreadId;
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
}
else if (enetType == ENET_ICSSG_SWITCH)
{
switch (instId)
{
case 0:
peerChNum = gEnetSoc_icssg0SwtSocCfg.txChPeerThreadId;
break;
case 1:
peerChNum = gEnetSoc_icssg1SwtSocCfg.txChPeerThreadId;
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
/* Get PSI-L destination thread offset for Tx channel */
peerChNum = (peerChNum + chNum);
return peerChNum;
}
uint32_t EnetSoc_getRxChPeerId(Enet_Type enetType,
uint32_t instId,
uint32_t chIdx)
{
uint32_t peerChNum = 0U;
if (enetType == ENET_ICSSG_DUALMAC)
{
switch (instId)
{
case 0:
peerChNum = gEnetSoc_icssg0DMacSocCfg[0].rxChPeerThreadId;
break;
case 1:
peerChNum = gEnetSoc_icssg0DMacSocCfg[1].rxChPeerThreadId;
break;
case 2:
peerChNum = gEnetSoc_icssg1DMacSocCfg[0].rxChPeerThreadId;
break;
case 3:
peerChNum = gEnetSoc_icssg1DMacSocCfg[1].rxChPeerThreadId;
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
}
else if (enetType == ENET_ICSSG_SWITCH)
{
EnetSoc_assert(((chIdx == 0U) || (chIdx == 1U)), "Invalid channel index %u\n", chIdx);
switch (instId)
{
case 0:
peerChNum = gEnetSoc_icssg0SwtSocCfg.rxChPeerThreadId + chIdx;
break;
case 1:
peerChNum = gEnetSoc_icssg1SwtSocCfg.rxChPeerThreadId + chIdx;
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
return peerChNum;
}
uint32_t EnetSoc_getTxChCount(Enet_Type enetType,
uint32_t instId)
{
uint32_t txChCount = 0U;
if (enetType == ENET_ICSSG_DUALMAC)
{
switch (instId)
{
case 0:
txChCount = gEnetSoc_icssg0DMacSocCfg[0].txChCount;
break;
case 1:
txChCount = gEnetSoc_icssg0DMacSocCfg[1].txChCount;
break;
case 2:
txChCount = gEnetSoc_icssg1DMacSocCfg[0].txChCount;
break;
case 3:
txChCount = gEnetSoc_icssg1DMacSocCfg[1].txChCount;
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
}
else if (enetType == ENET_ICSSG_SWITCH)
{
switch (instId)
{
case 0:
txChCount = gEnetSoc_icssg0SwtSocCfg.txChCount;
break;
case 1:
txChCount = gEnetSoc_icssg1SwtSocCfg.txChCount;
break;
default:
EnetSoc_assert(false, "Invalid peripheral (eneType=%u instId=%u)\n", enetType, instId);
break;
}
}
EnetSoc_assert((EnetSoc_isValidEnetType(enetType) == true), "Invalid Enet type %d\n", enetType);
return txChCount;
}
bool EnetSoc_isCoreAllowed(Enet_Type enetType,
uint32_t instId,
uint32_t coreId)
{
return true;
}
/*!
* \brief ICSSG default configuration
* Note: If user wishes to change the Resource Partition the following
* things must be considered:
* 1. Sum of numTxCh allocated to each core should not exceed 8.
* 2. Sum of numRxFlows allocated to each core should not exceed 10 (not 64),
* as one Rx flow is reserved to the master core.
*
*/
static EnetRm_ResPrms gEnetAppRmDefCfg_iccsgDMac =
{
.coreDmaResInfo =
{
[0] =
{
.coreId = CSL_CORE_ID_R5FSS0_0,
.numTxCh = ENET_SYSCFG_TX_CHANNELS_NUM, /* numTxCh */
.numRxFlows = ENET_SYSCFG_RX_FLOWS_NUM, /* numRxFlows */
.numMacAddress = 1U,
},
},
.numCores = 1U,
};
static EnetRm_ResPrms gEnetAppRmDefCfg_iccsgSwt =
{
.coreDmaResInfo =
{
[0] =
{
.coreId = CSL_CORE_ID_R5FSS0_0,
.numTxCh = ENET_SYSCFG_TX_CHANNELS_NUM, /* numTxCh */
.numRxFlows = ENET_SYSCFG_RX_FLOWS_NUM, /* numRxFlows */
.numMacAddress = 1U,
},
},
.numCores = 1U,
};
const EnetRm_ResPrms *EnetAppRm_getResPartInfo(Enet_Type enetType)
{
const EnetRm_ResPrms *rmInitPrms = NULL;
switch (enetType)
{
case ENET_ICSSG_DUALMAC:
{
rmInitPrms = &gEnetAppRmDefCfg_iccsgDMac;
break;
}
case ENET_ICSSG_SWITCH:
default:
{
rmInitPrms = &gEnetAppRmDefCfg_iccsgSwt;
break;
}
}
return(rmInitPrms);
}
/* Cores IOCTL Privileges */
static const EnetRm_IoctlPermissionTable gEnetAppIoctlPermission_iccsg =
{
.defaultPermittedCoreMask = (ENET_BIT(CSL_CORE_ID_A53SS0_0) |
ENET_BIT(CSL_CORE_ID_R5FSS0_0) |
ENET_BIT(CSL_CORE_ID_R5FSS0_1)),
.numEntries = 0,
};
const EnetRm_IoctlPermissionTable *EnetAppRm_getIoctlPermissionInfo(Enet_Type enetType)
{
const EnetRm_IoctlPermissionTable *ioctlPerm = NULL;
switch (enetType)
{
case ENET_ICSSG_DUALMAC:
case ENET_ICSSG_SWITCH:
{
ioctlPerm = &gEnetAppIoctlPermission_iccsg;
break;
}
default:
{
ioctlPerm = NULL;
break;
}
}
return(ioctlPerm);
}
