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器件型号：DRA821U 工具与软件：
你(们)好、
我们在使两个1000BASE-T1接口在定制电路板上正常工作时遇到了问题。 下面是这两种接口的方框图。 我还在下面附上了我们的器件树配置。 我的问题：
1. 您是否支持使用 SDK 10的第45条器件、我们看到以下文章指出 SDK 9不支持第45条？ https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1285073/dra821u-how-to-enable-cpsw5g-linux-native-ethernet-for-sgmii-rmii-on-dra821
2.如果没有、我们需要做些什么改变才能使第45条第22条生效？
我们的两个接口的器件树：
&wkup_pmx2 {
eth1_reset_pins_default: eth1-reset-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x80, PIN_INPUT, 7) /* (C20) WKUP_GPIO0_10 */
>;
};
};
&main_pmx0 {
mdio0_pins_default: mdio0-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
>;
};
eth0_reset_pins_default: eth0-reset-default-pins {
pinctrl-single,pins = <
J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
>;
};
};
&serdes_ln_ctrl {
idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
<J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_QSGMII_LANE2>;
};
&serdes_refclk {
clock-frequency = <100000000>;
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
};
serdes0_qsgmii_link: phy@2 {
reg = <2>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_SGMII>;
resets = <&serdes_wiz0 3>, <&serdes_wiz0 4>;
};
};
&{/} {
aliases {
ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
};
};
&cpsw0 {
status = "okay";
};
&cpsw0_port1 {
status = "okay";
phy-handle = <&cpsw5g_phy0>;
phy-mode = "sgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 1>, <&serdes0_qsgmii_link>;
phy-names = "portmode", "serdes-phy";
};
&cpsw0_port2 {
status = "okay";
phy-handle = <&cpsw5g_phy0>;
phy-mode = "sgmii";
mac-address = [00 00 00 00 00 00];
phys = <&cpsw0_phy_gmii_sel 2>, <&serdes0_qsgmii_link>;
phy-names = "portmode", "serdes-phy";
};
&cpsw5g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins_default>;
reset-gpios = <
&wkup_gpio0 10 GPIO_ACTIVE_LOW
&main_gpio0 55 GPIO_ACTIVE_LOW
>;
reset-post-delay-us = <120000>;
#address-cells = <1>;
#size-cells = <0>;
cpsw5g_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
cpsw5g_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <1>;
};
};
