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器件型号:TIDA-01604 50Hz 频率的方波脉冲将根据以下所示的输入 PWM 模式被馈送到 GPIO、同时还会附加代码。问题出在脉冲的上升沿和下降沿。 如何解决此问题
#include "F28x_Project.h" void InitEPwmTimer(void); interrupt void xint1_isr(void); void main(void) { InitSysCtrl(); // Disable WD,init PLL,enable Peripheral Clocks DINT; // Disable CPU interrupts /*Initialize the PIE control registers to their default state. The default state is all PIE interrupts disabled and flags are cleared*/ InitPieCtrl(); // Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000; // Reset Interrupt Enable Register IFR = 0x0000; // Reset Interrupt Flag Register InitPieVectTable(); EALLOW; // This is needed to write to EALLOW protected registers PieVectTable.XINT1_INT = &xint1_isr; EDIS; // This is needed to disable write to EALLOW protected registers PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block PieCtrlRegs.PIEIER1.bit.INTx4 = 1; // Enable PIE Gr InitEPwmTimer(); // For this example, only initialize the EPwm Timers IER |= M_INT1; // Timer 0, ADC // Enable CPU Interrupt 1 EINT; // Enable Global interrupt INTM ERTM; // Enable Global real-time interrupt DBGM EALLOW; GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0; // GPIO GpioCtrlRegs.GPBDIR.bit.GPIO32 = 0; // input GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 0; // XINT1 Synch to SYSCLKOUT only EDIS; GPIO_SetupXINT1Gpio(32); XintRegs.XINT1CR.bit.POLARITY = 3; // Enable XINT1 and XINT2 // XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1 // EALLOW; GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // GPIO GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // output EDIS; while(1) { if(GpioDataRegs.GPBDAT.bit.GPIO32 == 1) // Data Register for this pin--Here rising edge is detected -this code works for Positive half cycle { EALLOW; EPwm1Regs.TZFRC.bit.OST = 1; // Force a one shot trip EPwm1Regs.TZCTL.bit.TZA = 3; // Do nothing EPwm1Regs.TZCTL.bit.TZB = 3; // Do nothing EPwm3Regs.TZFRC.bit.OST = 1; // Force a one shot trip EPwm3Regs.TZCTL.bit.TZA = 3; // Do nothing EPwm3Regs.TZCTL.bit.TZB = 3; // Do nothing EPwm2Regs.TZFRC.bit.OST = 1; // Force a one shot trip EPwm2Regs.TZCTL.bit.TZA = 1; // Force EPWM2A to a high state EPwm2Regs.TZCTL.bit.TZB =1; //Force EPWM2B to a high state EPwm4Regs.TZFRC.bit.OST = 1; // Force a one shot trip EPwm4Regs.TZCTL.bit.TZA = 1; // Force EPWM2A to a high state EPwm4Regs.TZCTL.bit.TZB =1; //Force EPWM2B to a high state EDIS; EPwm2Regs.TBCTR = 0X0000; EPwm4Regs.TBCTR = 0X0000; EPwm1Regs.CMPA.bit.CMPA = 5000; EPwm1Regs.CMPB.bit.CMPB = 5000; EPwm3Regs.CMPA.bit.CMPA = 5000; EPwm3Regs.CMPB.bit.CMPB = 5000; } else if (GpioDataRegs.GPBDAT.bit.GPIO32 == 0) //Here falling edge is detected -this code works for Negative half cycle { EPwm1Regs.TBCTR = 0X0000; EPwm3Regs.TBCTR = 0X0000; EALLOW; EPwm2Regs.TZFRC.bit.OST = 1; // Force a one shot trip EPwm2Regs.TZCTL.bit.TZA = 3; // Do nothing EPwm2Regs.TZCTL.bit.TZB =3; // Do nothing EPwm4Regs.TZFRC.bit.OST = 1; // Force a one shot trip EPwm4Regs.TZCTL.bit.TZA = 3; // Do nothing EPwm4Regs.TZCTL.bit.TZB =3; // Do nothing EPwm1Regs.TZFRC.bit.OST = 1; // Force a one shot trip EPwm1Regs.TZCTL.bit.TZA = 1; // Force EPWM1A to a high state EPwm1Regs.TZCTL.bit.TZB = 1; // Force EPWM1B to a high state EPwm3Regs.TZFRC.bit.OST = 1; // Force a one shot trip EPwm3Regs.TZCTL.bit.TZA = 1; // Force EPWM1A to a high state EPwm3Regs.TZCTL.bit.TZB = 1; // Force EPWM1B to a high state EDIS; EPwm2Regs.CMPA.bit.CMPA =5000; EPwm2Regs.CMPB.bit.CMPB = 5000; EPwm4Regs.CMPA.bit.CMPA =5000; EPwm4Regs.CMPB.bit.CMPB = 5000; } } }