TMS320F28379D 如何采用EPWM中的数字比较器DC和trip zone 来实现对PWM信号的同步更新？

感觉你的理解没错，但是顺序有点反了。个人认为根据原文翻译来说：
数字比较事件DCAEVT1/2或DCBEVT1/2，是由TZDCSEL寄存器选择的DCAH/DCAL和DCBH/DCBL信号组合成的。而DCAH/DCAL和DCBH/DCBL的信号源是由DCTRIPSEL寄存器选择的，可以是TZ输入脚也可以是模拟比较CMPSSx信号。
通俗地讲，DC单元的输入信号可以来自两个源，一是TZ信号，二是芯片集成的模拟比较器的输出CMPSSx信号，它们最终进入DC子模块后可以根据你的配置生成DC事件，进而触发EPWM的trip(可能是置高，拉低，翻转或不动作)。
关于你说的eCAP捕获延时的问题，我需要再查找一些参考。

感谢 Green的解答，我还有一个疑问，我有两路ePWM2和ePWM3分别对应有两路TZ信号(外部GPIO进来的脉冲信号)，TZ1对应ePWM2和TZ2对应ePWM3, TZ1和TZ2通过Digital Compare各自产生一个DCAEVT1.sync分别去同步各个模块，即将计数器清零。

但是我发现有几个问题：

1. TZ1的信号可以同步ePWM2的计数器，但TZ2无法同步ePWM3的计数器；
2. 当TZ1同步ePWM2的计数器的时候，同时也将ePWM3的计数器也清零了，但ePWM3并没有继承ePWM2的时钟，因为EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; 难道每个PWM模块产生的同步信号会同步所有模块？
3. 对于ePWM2和ePWM3,如果我想移相180°，需要将PHSEN使能，TBPHS设置移相角，还是否必须要将TBCTL.bit.SYNCOSEL设置为TB_SYNC_IN吗，通过测试我发现是不需要的，如果不同步，那ePWM2和ePWM3又是如何做到能够准备移相180°呢

附上相关代码如下：


EPwm2Regs.TBPRD = (Uint16)(TLBDC_PER); //PWM period
EPwm2Regs.TBPHS.bit.TBPHS = 0;//(Uint16)(0.5f*EPwm2Regs.TBPRD);//No phase shift
EPwm2Regs.TBCTL.bit.FREE_SOFT = 2; //Free run
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //System clock out / 1
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;//TB_SYNC_IN;//TB_CTR_ZERO;//TB_SYNC_IN;//TB_CTR_ZERO; //Send synchronization signal when counter = 0
EPwm2Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;//TB_SHADOW; //Using shadow register for PWM period
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;//TB_DISABLE;//TB_DISABLE; //Master, don't need load phase register
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;//TB_COUNT_UPDOWN; //TB_COUNT_UP;//Up-down mode

/* Counter compare register initialization */
EPwm2Regs.CMPA.bit.CMPA = TLBDC_CMPA(0);//TLBDC_CMPA(0.3);//cmpa=zkb*prd(s1),zkb=pi_out
EPwm2Regs.CMPB.bit.CMPB = TLBDC_CMPB(0);//TLBDC_CMPB(0.3);//phase=180; zkb'=pi_out,cmpb=(1-zkb')*prd=(1-pi_out)*prd (s2,pass a not logic->s3)
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;//Load new compare value when counter = period
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;//CC_CTR_ZERO;//Load new compare value when counter = zero

/* Action qualifier register initialization */
EPwm2Regs.AQCTLA.bit.ZRO = AQ_CLEAR;//AQ_SET; // Set PWM1A on Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; //AQ_CLEAR; // Clear PWM1A on event A,
EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;//
EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B,
EPwm2Regs.AQCTLB.bit.PRD = AQ_SET;//AQ_CLEAR;//

EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;//DBA_RED_DBB_FED;//DBB_RED_DBA_FED;//s5=1,s4=0
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//DBB_ENABLE;//DB_DISABLE;//DBB_ENABLE;// s1=0,s0=1(Q3)->0(Q2)
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;//DB_ACTV_LOC;//DB_ACTV_HI;//DB_ACTV_LO;//0x00;//DB_ACTV_HIC;// s3=1,s2=0->1, Active Hi complementary
EPwm2Regs.DBFED = 0x05;//INV_DEAD_CYCLE;// FED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBRED = 0x02;//INV_DEAD_CYCLE;// RED = INV_DEAD_CYCLE TBCLKs
EPwm2Regs.DBCTL.bit.OUTSWAP = 0x00;//0x03;

//add soca
EPwm2Regs.ETSEL.bit.SOCAEN=ET_ENABLE;//ET_DISABLE;//enable
EPwm2Regs.ETSEL.bit.SOCASEL=ET_CTR_PRDZERO;//ET_CTR_PRDZERO;
EPwm2Regs.ETPS.bit.SOCAPRD=ET_1ST;//divide frequency, page69/117.
//1 1 2 3-Generate the EPWMxSOCA pulse on the first second third event:
//2 Once the SOCA pulse is generated, the ETPS[SOCACNT] bits will automatically be cleared.
EPwm2Regs.ETSEL.bit.SOCBEN=ET_ENABLE;//ET_DISABLE;//ET_ENABLE;//enable
EPwm2Regs.ETSEL.bit.SOCBSEL=ET_CTR_PRDZERO;//ET_CTR_ZERO;
EPwm2Regs.ETPS.bit.SOCBPRD=ET_1ST;//divide frequency
//3 Generate the EPWMxSOCA pulse on the first event: ETPS[SOCACNT] = 0,1
EPwm2Regs.ETSEL.bit.INTEN=ET_DISABLE;
EPwm2Regs.ETPS.bit.INTPRD=ET_DISABLE;

// Define an event (DCAEVT1) based on TZ1 and TZ2
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_TZ1; // DCAH = TZ1
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI;//TZ_DCAH_LOW;//TZ_DCAL_HI_DCAH_LOW;

EPwm2Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1; //DCAEVT1 =DCAEVT1(not filtered)
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;//DC_EVT_SYNC;//DC_EVT_ASYNC;//DC_EVT_SYNC;// // Take async path

EPwm2Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high
EPwm2Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;//TZ_FORCE_LO; // EPWM1B will go low

EPwm2Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high

EPwm2Regs.DCACTL.bit.EVT1SYNCE = 1;


EPwm3Regs.TBPRD = (Uint16)(TLBDC_PER); //PWM period
EPwm3Regs.TBPHS.bit.TBPHS = 0;//(Uint16)(0.5f*EPwm2Regs.TBPRD);//No phase shift
EPwm3Regs.TBCTL.bit.FREE_SOFT = 2; //Free run
// EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; //Counter up after synchronization
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; //System clock out / 1
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //System clock out / 1
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;//TB_CTR_ZERO;//TB_SYNC_IN;//TB_CTR_ZERO; //Send synchronization signal when counter = 0
EPwm3Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;//TB_SHADOW; //Using shadow register for PWM period
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;//TB_DISABLE;//TB_DISABLE; //Master, don't need load phase register
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;//TB_COUNT_UPDOWN; //TB_COUNT_UP;//Up-down mode
// Counter compare register initialization
EPwm3Regs.CMPA.bit.CMPA = 0;//TLBDC_CMPA(0.3);//cmpa=zkb*prd(s1),zkb=pi_out
EPwm3Regs.CMPB.bit.CMPB = 0;//TLBDC_CMPB(0.3);//phase=180; zkb'=pi_out,cmpb=(1-zkb')*prd=(1-pi_out)*prd (s2,pass a not logic->s3)
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE;//CC_SHADOW;//Using shadow register for compare
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;//Load new compare value when counter = period
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD;//CC_CTR_ZERO;//Load new compare value when counter = zero
// Action qualifier register initialization
EPwm3Regs.AQCTLA.bit.ZRO = AQ_CLEAR;//AQ_SET; // Set PWM1A on Zero
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;//AQ_CLEAR; // Clear PWM1A on event A, // up count
EPwm3Regs.AQCTLA.bit.PRD = AQ_CLEAR;//

EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET; // Set PWM1B on Zero
EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM1B on event B,
EPwm3Regs.AQCTLB.bit.PRD = AQ_SET;//AQ_CLEAR;//

EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;//DBA_RED_DBB_FED;//DBB_RED_DBA_FED;//s5=1,s4=0
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;//DBB_ENABLE;//DB_DISABLE;//DBB_ENABLE;// s1=0,s0=1(Q3)->0(Q2)
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;//DB_ACTV_LOC;//DB_ACTV_HI;//DB_ACTV_LO;//0x00;//DB_ACTV_HIC;// s3=1,s2=0->1, Active Hi complementary
EPwm3Regs.DBFED = 0x05;//INV_DEAD_CYCLE;// FED = INV_DEAD_CYCLE TBCLKs
EPwm3Regs.DBRED = 0x02;//INV_DEAD_CYCLE;// RED = INV_DEAD_CYCLE TBCLKs
EPwm3Regs.DBCTL.bit.OUTSWAP = 0x00;//0x03;

//add soca
EPwm3Regs.ETSEL.bit.SOCAEN=ET_DISABLE;//enable
EPwm3Regs.ETSEL.bit.SOCASEL=ET_CTR_PRDZERO;//ET_CTR_PRDZERO;
EPwm3Regs.ETPS.bit.SOCAPRD=ET_1ST;//divide frequency, page69/117.
//1 1 2 3-Generate the EPWMxSOCA pulse on the first second third event:
//2 Once the SOCA pulse is generated, the ETPS[SOCACNT] bits will automatically be cleared.
EPwm3Regs.ETSEL.bit.SOCBEN=ET_DISABLE;//enable
EPwm3Regs.ETSEL.bit.SOCBSEL=ET_CTR_PRDZERO;//ET_CTR_ZERO;
EPwm3Regs.ETPS.bit.SOCBPRD=ET_1ST;//divide frequency
//3 Generate the EPWMxSOCA pulse on the first event: ETPS[SOCACNT] = 0,1
EPwm3Regs.ETSEL.bit.INTEN=ET_DISABLE;
EPwm3Regs.ETPS.bit.INTPRD=ET_DISABLE;

// Define an event (DCAEVT1) based on TZ1 and TZ2
EPwm3Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TZ2;

EPwm3Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_HI;

EPwm3Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1;
EPwm3Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;

EPwm3Regs.TZCTL.bit.TZA = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high
EPwm3Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;//TZ_FORCE_LO; // EPWM1B will go low

EPwm3Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE;//TZ_FORCE_HI; // EPWM1A will go high

EPwm3Regs.DCACTL.bit.EVT1SYNCE = 1;

你好，外部信号不是可以直接通过XBAR进行触发吗？为什么还要通过比较器或者TZ的方式呢？