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EALLOW; SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // Enable Clock to the ADC AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; // Comparator shares the internal BG reference of the ADC, must be powered even if ADC is unused DELAY_US(1000); // Delay for Power Up SysCtrlRegs.PCLKCR3.bit.COMP1ENCLK = 1; // Enable clock to the Comparator 1 block Comp1Regs.COMPCTL.bit.COMPDACEN = 1; // Power up Comparator 1 locally Comp1Regs.COMPCTL.bit.COMPSOURCE = 0; // Connect the inverting input to the internal Comp1Regs.DACCTL.bit.FREE_SOFT = 2; /* Emulation mode behavior, stop immediately */ Comp1Regs.DACCTL.bit.DACSOURCE = 1; Comp1Regs.COMPCTL.bit.QUALSEL = 0; // Comparator output must be active for 4 consecutive clocks before resetting the RAMP Comp1Regs.DACCTL.bit.RAMPSOURCE = 0; EPwm1Regs.HRPCTL.bit.PWMSYNCSEL = 1; // PWM SYNC generated at CTR = ZRO for synchronizing internal ramp Comp1Regs.COMPCTL.bit.CMPINV = 0; // Comparator Output passed Comp1Regs.RAMPDECVAL_SHDW = 20; Comp1Regs.RAMPMAXREF_SHDW = 20000;
