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TMS320F28374D: ADC时钟配置问题

Part Number: TMS320F28374D

最近我在使用ADC时,对ADCCLK的配置存在一些疑问,请各位大佬帮忙解答一下,谢谢!

28374D主频为200MHz,配置ADC分频时,当Input Clock = 200MHz时,ADCCTL2寄存器描述ADCCLK最大可到200MHz(0000 ADCCLK = Input Clock / 1.0),但数据手册中描述,28374D配置12位ADC,可配置最大ADCCLK只有50MHz,所以应该以哪个数据作为ADCCLK最大值参考,如果最大ADCCLK为50MHz,是否意味着PRESCALE的1--3.5倍分频的配置都是失效的