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F28035CPU与CLA共享RAM变量初始化问题

user1880609
Intellectual 655 points


专家你好：我现用的F28035芯片，里面有两个共享信息RAM,分别是Cla1ToCpuMsgRAM与CpuToCla1MsgRAM，当我在shared.c(共享)文件中的Cla1ToCpuMsgRAM区块中定义变量时初始化，在CLA中调用这个变量时并不是这个初始化的值而是随机值；同样在CpuToCla1MsgRAM区块中定义变量时初始化，在主程序中调用这个变量时得到的也不是初始化的值，这是为什么？谢谢！

  • 0
    TI__Guru 60308 points

    RUILONG

    请问你是如何初始化这个变量的？

    请注意下面关于变量初始化的地方：

    CLA的C编译器不支持全局变量的直接赋值。需要在任务中去把初始值赋给这个变量。

    CLA C compiler does not support:
    Initialized global and static data

      int x;      // valid

      int x=5;    // not valid

    Initialized variables need to be manually handled by an initialization task
     
    Eric
  • 0 回复 Eric Ma
    Intellectual 655 points
    你好：再请教一个F28035的问题
    我现在这有一段发波程序如下：

    //PWM1的配置
    EALLOW;

    // TB
    EPwm1Regs.TBPRD = 300; 
    EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module

    //CC
    EPwm1Regs.CMPA.half.CMPA = 150; // Set 50% fixed duty for EPWM1A
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

    //AQ
    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM1A
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    //DB
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; //EPWM1A is the source for both delay.
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
    EPwm1Regs.DBFED = 18; // FED = 10 TBCLKs initially
    EPwm1Regs.DBRED = 18; // RED = 10 TBCLKs initially

    //ET
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
    EPwm1Regs.ETSEL.bit.INTEN = 0; // Disable INT
    EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event

    //PWM2的配置

    // TB
    EPwm2Regs.TBPRD = 300;
    EPwm2Regs.TBPHS.half.TBPHS = 225; // Set Phase register to PWM_PRD_USE_MIN/4 initially
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Asymmetrical mode
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through

    //CC
    EPwm2Regs.CMPA.half.CMPA = 150; // Set 50% fixed duty EPWM2A
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero

    //AQ
    EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // set actions for EPWM2A
    EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    //DB
    EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; // EPWM1A is the source for both delay.
    EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
    EPwm2Regs.DBFED = 18; // FED = 10 TBCLKs initially
    EPwm2Regs.DBRED = 18; // RED = 10 TBCLKs initially

    //ET
    EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Enable INT on Zero event
    EPwm2Regs.ETSEL.bit.INTEN = 0; // Disable INT
    EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event

    EDIS;

    这段程序的本意是配置EPWM1与EPWM2相位相差90°，当我使能EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;EPwm2Regs.TBPHS.half.TBPHS = 225; EPWM1发波正常而EPWM2没有发波或发波延迟很长时间，而且在频率大范围跳变时EPWM1发波正常，

    而EPWM2发波异常（恒高或恒低），经分析是在频率跳变时，在同步事件产生时（即EPWM1的TBCTR=0时刻），EPWM2的TBCTR直接加载TBPHS的值（TBPHS无SHADOW寄存器），而TBPRD的值仍为上一次加载值，导致后续TBCTR向上计数一直达不到TBPRD的值而产生不了TBCTR=0的事件，后续一直加载不了TBPRD的计算更新值，导致恒高或恒低电平。

    当我不使能EPWM2的TBPHS时EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;或者使能TBPHSEPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE,但EPwm2Regs.TBPHS.half.TBPHS = 0; EPWM1与EPMW2同相位同时发波正常，请问这是什么原因？谢谢！