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MSP430FR6989 ADC12TOVIFG 问题

Other Parts Discussed in Thread: MSP430FR6989, MSP-EXP430FR6989

大家好:

我们采用 MSP430FR6989 进行多通道采样,出现 ADC12TOVIFG, 导致采样结果不正确:

ADC 设置如下:

      多通道序列模式 ADC12CONSEQ_1

      ADC12MSC ADC12SHP 

     12 位采样精度

     TA0.1 作为采样触发

     采样频率 4k

     同时采样 5 个通道

代码如下:     

#include <msp430.h>

#define ADC_CHANNEL 5
static short ADC_SampleResult[ADC_CHANNEL] = {0};

int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop WDT

PJSEL0 |= BIT4 /*| BIT5 | BIT6 | BIT7*/;

FRCTL0 = FRCTLPW | NWAITS_1;

CSCTL0_H = CSKEY_H;

CSCTL1 = DCORSEL | DCOFSEL_4; // 设置DCO在低频模式 16MHz
CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK; // 设置 ACLK = XT1, SMCLK = DCO, MCLK = XT2
CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;

CSCTL4 |= LFXTDRIVE_3;
CSCTL4 &= ~(LFXTOFF);

do
{
CSCTL5 &= ~(LFXTOFFG); // Clear XT1 XT2 fault flag
SFRIFG1 &= ~OFIFG;
}while (SFRIFG1 & OFIFG);

CSCTL0_H = 0;

// 4 个 ADC 采样通道
P1SEL0 |= BIT0 | BIT1 | BIT2 | BIT3;
P1SEL1 |= BIT0 | BIT1 | BIT2 | BIT3;

// Configure ADC12
ADC12CTL0 = ADC12SHT0_4 | ADC12ON | ADC12MSC; // Sampling time, ADC12 on
ADC12CTL1 = ADC12SHP | ADC12SHS_1 | ADC12CONSEQ_1; // Use sampling timer
ADC12CTL2 |= ADC12RES_2; // 12-bit conversion results

ADC12MCTL0 = ADC12VRSEL_1 | ADC12INCH_0; // Channel2 ADC input select; Vref=VREF buffered
ADC12MCTL1 = ADC12VRSEL_1 | ADC12INCH_1;
ADC12MCTL2 = ADC12VRSEL_1 | ADC12INCH_2;
ADC12MCTL3 = ADC12VRSEL_1 | ADC12INCH_3;
ADC12MCTL4 = ADC12VRSEL_1 | ADC12INCH_4 | ADC12EOS;


ADC12IER0 = ADC12IE4;
ADC12IER2 = ADC12TOVIE | ADC12OVIE;

REFCTL0 |= REFVSEL_2 | REFON;

TA0CCR0 = 7; // TA0 4K 采样频率

TA0CCR1 = 1;
TA0CCTL1 |= OUTMOD_2; // TBCCR0 toggle (ON period = ~230us)

ADC12CTL0 |= ADC12ENC;
TA0CTL = TASSEL__ACLK | MC__UP | TACLR; // ACLK, up mode

// 输出 TA0.1
P1SEL0 |= BIT6;
P1SEL1 |= BIT6;

P1DIR |= BIT6;
P4DIR |= BIT2 | BIT3;
PM5CTL0 &= ~LOCKLPM5;

while (1) {
__low_power_mode_3();
}
}

#pragma vector = ADC12_VECTOR
__interrupt void ADC_IsrCallback(void)
{
switch(__even_in_range(ADC12IV, ADC12IV_ADC12RDYIFG))
{
case ADC12IV_NONE: break; // Vector 0: No interrupt
case ADC12IV_ADC12OVIFG:
break; // Vector 2: ADC12MEMx Overflow
case ADC12IV_ADC12TOVIFG:
P4OUT |= BIT3;
__delay_cycles(1);
P4OUT &= ~BIT3;
break; // Vector 4: Conversion time overflow
case ADC12IV_ADC12HIIFG: break; // Vector 6: ADC12BHI
case ADC12IV_ADC12LOIFG: break; // Vector 8: ADC12BLO
case ADC12IV_ADC12INIFG: break; // Vector 10: ADC12BIN
case ADC12IV_ADC12IFG0: break; // Vector 12: ADC12MEM0 Interrupt
case ADC12IV_ADC12IFG1: break; // Vector 14: ADC12MEM1
case ADC12IV_ADC12IFG2: break; // Vector 16: ADC12MEM2
case ADC12IV_ADC12IFG3: break; // Vector 18: ADC12MEM3
case ADC12IV_ADC12IFG4: // Vector 20: ADC12MEM4
ADC12CTL0 &= ~ADC12ENC;
ADC12CTL0 |= ADC12ENC;

P4OUT |= BIT2;
ADC_SampleResult[0] = ADC12MEM0;
ADC_SampleResult[1] = ADC12MEM1;
ADC_SampleResult[2] = ADC12MEM2;
ADC_SampleResult[3] = ADC12MEM3;
ADC_SampleResult[4] = ADC12MEM4;

P4OUT &= ~BIT2;
break;

case ADC12IV_ADC12IFG5: break; // Vector 22: ADC12MEM5
case ADC12IV_ADC12IFG6: break; // Vector 24: ADC12MEM6
case ADC12IV_ADC12IFG7: break; // Vector 26: ADC12MEM7
case ADC12IV_ADC12IFG8: break; // Vector 28: ADC12MEM8
case ADC12IV_ADC12IFG9: break; // Vector 30: ADC12MEM9
case ADC12IV_ADC12IFG10: break; // Vector 32: ADC12MEM10
case ADC12IV_ADC12IFG11: break; // Vector 34: ADC12MEM11
case ADC12IV_ADC12IFG12: break; // Vector 36: ADC12MEM12
case ADC12IV_ADC12IFG13: break; // Vector 38: ADC12MEM13
case ADC12IV_ADC12IFG14: break; // Vector 40: ADC12MEM14
case ADC12IV_ADC12IFG15: break; // Vector 42: ADC12MEM15
case ADC12IV_ADC12IFG16: break; // Vector 44: ADC12MEM16
case ADC12IV_ADC12IFG17: break; // Vector 46: ADC12MEM17
case ADC12IV_ADC12IFG18: break; // Vector 48: ADC12MEM18
case ADC12IV_ADC12IFG19: break; // Vector 50: ADC12MEM19
case ADC12IV_ADC12IFG20: break; // Vector 52: ADC12MEM20
case ADC12IV_ADC12IFG21: break; // Vector 54: ADC12MEM21
case ADC12IV_ADC12IFG22: break; // Vector 56: ADC12MEM22
case ADC12IV_ADC12IFG23: break; // Vector 58: ADC12MEM23
case ADC12IV_ADC12IFG24: break; // Vector 60: ADC12MEM24
case ADC12IV_ADC12IFG25: break; // Vector 62: ADC12MEM25
case ADC12IV_ADC12IFG26: break; // Vector 64: ADC12MEM26
case ADC12IV_ADC12IFG27: break; // Vector 66: ADC12MEM27
case ADC12IV_ADC12IFG28: break; // Vector 68: ADC12MEM28
case ADC12IV_ADC12IFG29: break; // Vector 70: ADC12MEM29
case ADC12IV_ADC12IFG30: break; // Vector 72: ADC12MEM30
case ADC12IV_ADC12IFG31: break; // Vector 74: ADC12MEM31
case ADC12IV_ADC12RDYIFG: break; // Vector 76: ADC12RDY
default: break;
}
}

在 100s 的监测时间内,出现了多次 ADC12IV_ADC12TOVIFG,由于我们是交流 3 相同步采样(3 个不同的设备分别采样),出现这种情况时将会导致采样数据不正确。

如下的逻辑分析仪图形:

第一行为 ADC 中断输出 P4.2

第二行为 ADC12IV_ADC12TOVIFG 中断输出  P4.3

第三行为 TA0.1 输出 P1.6

可以看到,在出现 ADC12IV_ADC12TOVIFG 时,会出现一个采样点的数据丢失

请问一下,上述问题是如何造成的?

减少采样通道至 2 个通道或减少采样周期时间至 8 个 ADCCLK, 出现的次数变少,但并不能杜绝。

根据手册 5M 的 MODSOC,  5 个采样通道的总时间为 5 x (14 + 32) = 230 个 ADCCLK.   这个时间不到  对于 4k 的采样频率,每个采样间隔为 250us, 的一半,理论上应该不会出现才对。

不知道是不是我理解不正确或者是设置的问题, 请指正。谢谢