This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP432E401Y的清除中断标志位API函数的寄存器操作

Other Parts Discussed in Thread: MSP432WARE

我在使用MSP432的定时器触发SPI通信的中断中,设置通信频率为1M,但是实际测试通信频率达不到1M,测试发现在中断中调用API函数花费过多时间,我想操作寄存器来代替API函数,但是NVIC的寄存器实在是难于理解。

可以的话,希望能解答一下 MAP_TimerIntClear(TIMER2_BASE, TIMER_TIMB_TIMEOUT)函数的寄存器操作

  • 关于MAP_TimerIntClear,可以参考下面的链接。抱歉,目前并没有给出相关的API源码。

    software-dl.ti.com/.../group__timer__api.html

    在更早的MSP432WARE内有MSP432P系列的寄存器操作代码,您可以参考一下

    www.ti.com/.../MSP432WARE
  • 那请问一下,我在操作NVIC的寄存器时,编译器上显示的寄存器名字怎么和数据手册上得到完全不同,这对我进行寄存器操作造成了很大的麻烦,编译器上显示的寄存器如下图

  • 图片中对应的是core_cm4.h的以下代码,您可以给下面的定义来赋值的

    /**
      \ingroup    CMSIS_core_register
      \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
      \brief      Type definitions for the NVIC Registers
      @{
     */
    
    /**
      \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
     */
    typedef struct
    {
      __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
            uint32_t RESERVED0[24U];
      __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
            uint32_t RSERVED1[24U];
      __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
            uint32_t RESERVED2[24U];
      __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
            uint32_t RESERVED3[24U];
      __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
            uint32_t RESERVED4[56U];
      __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
            uint32_t RESERVED5[644U];
      __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
    }  NVIC_Type;