其他微控制器论坛 - 最近的话题

MSPM0-SDK: MSPM0G3507 串口DMA进行不定长数据收发

biza inc — Wed, 06 May 2026 15:28:32 GMT

Part Number: MSPM0-SDK

HI，我在基于MSPM0G3507的串口+DMA实现不定长数据的收发，由于MSPM0G3507的寄存器特殊性，当使用DMA时，因为DMA及时半空FIFO所以超时中断无法触发，如果引入定时器轮询会浪费外设的同时效率不高，频繁的接收中断也会拉低CPU的效率。

我看到并参考：https://e2e.ti.com/support/microcontrollers/msp-low-power-microcontrollers-group/msp430/f/msp-low-power-microcontroller-forum/1220244/faq-uart-rx-ms-level-timeout-realization-based-on-event-for-mspm0?tisearch=e2e-sitesearch&keymatch=UART%20timeout%20MSPM0 来进行设计，但是发现偶尔会出现字节多收，理论上此拓扑应该能行的通，但是我试验多次，发现一旦数据多了还是会多收字节，表现为DMASZ的数量跟实际发送不一致。

对于MSPM0G3507的架构特殊性，我严重怀疑TI的芯片设计是否有用过串口。

此问题依然存在，最后我只能使用串口中断+超时中断，使用仅仅4字深的FIFO来接收数据。

各位如果有更好的建议，还请让我知道，谢谢！

RE: MSPM0-SDK: MSPM0G3507 串口DMA进行不定长数据收发

Taylor — Wed, 06 May 2026 22:57:03 GMT

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

TIDM-02013: 需要定制两套TIDM-02013电源模块。

Bo Zhao — Fri, 01 May 2026 03:10:08 GMT

Part Number: TIDM-02013

我们想要两套TIDM-02013进行学习，查找你们商城没有成品进行购卖的，不知道能否定制两套。

RE: TIDM-02013: 需要定制两套TIDM-02013电源模块。

Lydia — Fri, 01 May 2026 04:08:21 GMT

TIDM-02013 不对外销售。

TIDM-02013: Issues of Relay Closing and Overcurrent Protection Triggering on the Circuit Board Caused by Driver Loss in the PFC Stage

Wang Xuesong — Tue, 10 Mar 2026 12:32:14 GMT

Part Number: TIDM-02013

Hello,

I am currently validating Experiment 3 of the PFC stage, with TTPLPFC_ac_cur_ref_pu set to 0.02.

The boost routine initiates when TTPLPFC_vBus_sensed_Volts > 110 V.

At no-load condition:

TTPLPFC_vBus_sensed_Volts can rise to 175 V; however, gate drive loss occurs as the input AC voltage enters its positive half-cycle.
With a 500 Ω load:

TTPLPFC_vBus_sensed_Volts can boost up to 135 V, but after maintaining this level for a few seconds, it begins to decline, eventually dropping below 110 V.

Throughout this process, the input AC voltage remains stable at 78 V.
Relay closing during boost:

Closing the relay during the boost phase triggers overcurrent protection (OCP) on the PCB.

Consequently, the relay remained open in all the aforementioned tests. Freewheeling was implemented via a bypassed thermistor, with each power-on duration strictly controlled within 10 seconds.
Waveform analysis & query:

From the measured waveforms, a definite phase difference between the voltage and current is still observable.

Is it feasible to eliminate this phase discrepancy and achieve phase alignment by adjusting the compensation capacitor?

I look forward to your prompt reply.

RE: TIDM-02013: Issues of Relay Closing and Overcurrent Protection Triggering on the Circuit Board Caused by Driver Loss in the PFC Stage

Links — Wed, 29 Apr 2026 07:05:55 GMT

Clarifications Needed

Before diving in, a few details from your posts would help refine this further:

When you say "driver loss," are the gate signals completely absent during portions of the cycle, or are they intermittent/degraded in amplitude?
At what specific input voltage threshold does the pulse dropping begin? You mention 200V — does it start gradually or appear suddenly?
What is the actual measured value of TTPLPFC_ac_cur_ref_pu when you observe it becoming "excessively large" in Experiment 4? Knowing the number helps determine how far the PI output is overshooting.
What load condition are you running during the 200V and Experiment 4 tests — no-load, 500Ω, or something else?

You are dealing with three interrelated problems, and the root cause traces back to current loop PI gain mismatch and voltage loop output saturation. Here's the breakdown:

1. Current Loop Ki Is Too Aggressive — This Is Causing Pulse Dropping

Your current loop gains are:

Kp = 0.3, Ki = 0.03

The reference design's Compensation Designer shows recommended values of Kp ≈ 0.35, Ki ≈ 0.0019 [1]. Your Ki is roughly 16× too high. At 200V input, the larger current demand causes the integrator to wind up rapidly, saturating the duty cycle output and dropping pulses. This directly explains why:

The driver works at startup (low voltage, small error) but fails as voltage increases
PWM before and after isolators is identical (the MCU is commanding the dropout, not the hardware)
Zero-crossing tracking is fine (PLL is not the issue)

Immediate action: Reduce TTPLPFC_GI_PI_KI from 0.03 to approximately 0.002 and retest [1].

2. The Very Small Current Reference (0.02 PU) Compounds the Problem

With TTPLPFC_ac_cur_ref_pu = 0.02, the inductor current ripple at 200V input is likely comparable to or larger than the commanded reference. The current loop literally cannot regulate — it's trying to control near-zero current against a large ripple [2].

Immediate action: Temporarily increase TTPLPFC_ac_cur_ref_pu to 0.1–0.2 to test whether pulse dropping improves. This isolates whether the near-zero reference is the issue [2].

3. Voltage Loop Output Formula and Saturation (Experiment 4)

Your formula question:

TTPLPFC_ac_cur_ref_pu = TTPLPFC_gv_out * TTPLPFC_vBusAvg_pu / TTPLPFC_vRmsAvg_pu

This structure is correct based on the reference design's closed voltage-and-current loop implementation (Lab 4) [3]. The problem isn't the formula — it's that TTPLPFC_gv_out grows excessively because:

The voltage error persists (vBus hasn't reached target)
The PI integrator accumulates without adequate anti-windup
The multiplication by TTPLPFC_vBusAvg_pu then amplifies the already-large PI output

This is why clamping at 1.0 still produces distortion — the fundamental issue is upstream in the PI compensator

Regarding the smoothing factor (0.000528): This value creates a very slow averaging filter. Your proposed modification to use TTPLPFC_vBus_sensedFiltered_notch2 directly instead of TTPLPFC_vBusAvg_pu could improve transient response, but it must be validated carefully — the notch-filtered signal may carry more ripple, which would modulate the current reference and cause distortion of a different kind [4].

Regarding using TTPLPFC_sine_mains.vRms instead of TTPLPFC_vRmsAvg_pu: This substitution bypasses the averaging and uses a more responsive RMS value. It's worth testing, but the same caution applies — ensure the signal is sufficiently clean.

4. ADC Clipping — Must Be Ruled Out

At 200V input, the scaled ADC input signals are larger. If the Hall sensor output exceeds 3.3V (the C2000 ADC reference), the sampled current values will clip, corrupting the feedback and destabilizing the loop [2].

Immediate action: Capture raw ADC counts for the current channels during the 200V distorted operation. Values pegged at 0 or 4095 (for 12-bit ADC) confirm clipping [2].

5. Relay and OCP — Secondary Issue

As previously noted, do not attempt relay closing until the PFC stage is stable. The OCP triggering is a symptom of the unstable control loop, not a separate problem [2].

Recommended Action Priority

Priority	Action
Critical	Reduce current loop Ki from 0.03 to ~0.002
Critical	Verify ADC inputs don't clip at 200V (check raw counts for 0 or 4095)
High	Increase `TTPLPFC_ac_cur_ref_pu` to 0.1–0.2 temporarily to test controllability
High	Verify anti-windup is implemented on both PI controllers
High	Confirm 100pF filter caps (C211, C204) are populated on Hall sensor outputs
Medium	Validate voltage loop PI gains (Kp=0.6, Ki=0.0001) using SFRA and Compensation Designer [5]
Medium	Test the `TTPLPFC_vBus_sensedFiltered_notch2` substitution only after current loop is stable
Low	Verify output capacitor C185 (220µF/160V) is populated — undersized capacitance worsens vBus instability

Key Insight

The duty cycle in this design is calculated as [1]:

duty1PU = ((ac_cur_meas - ac_cur_ref_inst) * Gi + ac_vol_sensed) / vBus_sensed

Both DC bus voltage and AC voltage feedforward are built into this equation. When the current loop saturates (due to excessive Ki or ADC clipping), the duty cycle calculation breaks down, producing the exact symptoms you're seeing — pulse dropping, waveform distortion, and vBus instability. Fix the current loop first, then tune the voltage loop.

To help refine these recommendations further, it would be helpful to know:

Actual ADC voltage measurements at the current sensing pins when input is at 200V (to confirm or rule out clipping)
Raw ADC count values during distorted operation
Whether the 100pF filter capacitors (C211, C204) are populated
Whether output capacitor C185 (220µF/160V) is populated on the board
Real-time CCS watch window values of TTPLPFC_ac_cur_ref_pu and duty cycle output as input voltage ramps to 200V
Whether the duty cycle is hitting TTPLPFC_DUTY_MAX during pulse loss
SFRA sweep results to validate loop stability margins with your current PI gains
Scope capture of Hall sensor output during 200V input to check for noise

RE: TIDM-02013: Voltage distortion across the switching transistor under sub-resonant operation

Lydia — Mon, 27 Apr 2026 00:04:30 GMT

Hi,

This is a reasonable phenomenon. Let's say Ch4 is PWM_sr_2_bottom and Ch3 is Vds. PWM_sr_2_bottom turns off first. Then current go negative, and the body diode goes through a reverse recovery process. After the body diode is recovered, it can block a positive Vds. This is the time when Vds rises. But the Vds does not fully increase to Vout to let SR_2_top body diode conducts. Therefore, it continues resonance until PWM_sr_2_top (Ch1) turns on.

TIDM-02013: Voltage distortion across the switching transistor under sub-resonant operation

Wang Xuesong — Tue, 07 Apr 2026 11:32:27 GMT

Part Number: TIDM-02013

Dear expert.

When the frequency is below 400 kHz, the voltage Vds across the secondary-side switches exhibits sudden rises and falls. As the frequency decreases, the peak values of these sudden changes become larger. What is this related to? Is this a normal phenomenon?

Purple waveform: drain-source voltage Vds across the switching transistor.

Blue waveform: secondary-side current.

RE: TIDM-02013: Issues of Relay Closing and Overcurrent Protection Triggering on the Circuit Board Caused by Driver Loss in the PFC Stage

Wang Xuesong — Thu, 23 Apr 2026 11:37:47 GMT

#define TTPLPFC_GI_PI_KP (float) 0.3
#define TTPLPFC_GI_PI_KI (float) 0.03
#define TTPLPFC_GV_PI_KP (float) 0.6
#define TTPLPFC_GV_PI_KI (float) 0.0001

I am currently unable to identify the root cause of driver loss when the input voltage increases during current loop operation.

Are the voltage loop parameters properly validated and verified?

During Experiment 4, I observed that the voltage loop output TTPLPFC_ac_cur_ref_pu became excessively large,

resulting in severe distortion of the input voltage and current waveforms.

I added a clamping limit to restrict TTPLPFC_ac_cur_ref_pu ≤ 1.0,

but the experimental results showed that this limit was still too large.

Furthermore, limiting the output amplitude does not appear to be an effective solution to the fundamental problem of excessive voltage loop output.

Should the voltage loop output be calculated and structured using this formula?
TTPLPFC_ac_cur_ref_pu = TTPLPFC_gv_out * TTPLPFC_vBusAvg_pu / TTPLPFC_vRmsAvg_pu;

Is the smoothing factor 0.000528 too small in TTPLPFC_EMAVG_MACRO(TTPLPFC_vBus_sensedFiltered_notch2, TTPLPFC_vBusAvg_pu, (float32_t)0.000528);
Can the code be adjusted to TTPLPFC_ac_cur_ref_pu = TTPLPFC_gv_out * TTPLPFC_vBus_sensedFiltered_notch2 / TTPLPFC_sine_mains.vRms;

RE: TIDM-02013: Issues of Relay Closing and Overcurrent Protection Triggering on the Circuit Board Caused by Driver Loss in the PFC Stage

Links — Wed, 22 Apr 2026 01:31:15 GMT

Thank you for the update and the additional diagnostic information — this is very helpful in narrowing down the root cause.

The fact that:

The PWM signals before and after the isolation chips are identical, and
The waveforms track well at the zero-crossing point

...strongly suggests the PLL and gate driver hardware are functioning correctly. You're right to focus attention on the sampling or current loop as the likely culprit. Here are my thoughts:

1. Pulse Dropping at High Input Voltage — Current Loop Saturation Suspect:

When the input voltage is increased to 200V, the current loop demand increases significantly. If the current loop compensator is not properly tuned, or if the current reference exceeds the modulator's capability, pulse dropping can occur.

Can you monitor TTPLPFC_ac_cur_ref_pu in real-time via CCS watch window as you increase the input voltage to 200V? We want to verify the reference isn't saturating or behaving erratically.
What are your current loop PI gains (Kp and Ki)? If Ki is too aggressive, integrator windup at higher voltage levels could be causing the modulator output to clip, resulting in dropped pulses.
Is there any clamping applied to the duty cycle output in the firmware? Check whether the duty cycle is hitting its maximum limit (TTPLPFC_DUTY_MAX or equivalent) during the distortion period. If the duty cycle is being clamped, this would directly explain the pulse loss.

2. ADC Sampling Integrity at Higher Voltages:

At 200V input, the scaled ADC input signals are larger. If the gain scaling or the ADC input range is not configured correctly, the sampled values could be clipping at the ADC input, which would corrupt the current feedback and destabilize the loop.

Please verify the ADC input voltage on the current sensing pins does not exceed 3.3V (or the VREFHI of your C2000 device) when the input is at 200V. Calculate the expected sensor output voltage at 200V input using your Hall sensor gain and the voltage divider network.
Check whether TTPLPFC_IL1_OFFSET_PU and TTPLPFC_IL2_OFFSET_PU are still accurate at 200V. The offset you calibrated at no-load/no-input may shift under higher operating conditions if there is any thermal drift in the Hall sensors.
Can you capture the raw ADC counts for the current channels in CCS during the distorted operation? Look for any values pegged at 0 or 4095 (for a 12-bit ADC), which would confirm clipping.

3. Current Sensing Bandwidth & Noise:

At higher switching frequencies and input voltages, noise on the current sensing lines becomes more problematic.

Are the 100pF filter capacitors (C211 & C204) populated on your board? As I mentioned previously, missing these could cause noise-induced instability in the current feedback, which would worsen at higher voltages and power levels.
Can you capture a scope waveform of the Hall sensor output (IAC_PH1_SENSOR or IAC_PH2_SENSOR) during the 200V input condition? We are looking for any high-frequency noise spikes that may be corrupting the ADC samples.

4. Inductor Current vs. Reference Mismatch:

With TTPLPFC_ac_cur_ref_pu set to 0.02 (a very small reference value), at 200V input the inductor current ripple alone may be comparable to or larger than the commanded reference. This could make the current loop unable to regulate properly, as the controller is essentially trying to command near-zero current against a large ripple.

Consider temporarily increasing TTPLPFC_ac_cur_ref_pu to a higher value (e.g., 0.1 or 0.2) and observe whether the pulse dropping and distortion improve. This will help confirm whether the issue is related to operating near the boundary of the current loop's controllable range.

Summary of Recommended Next Steps:

Priority	Action
High	Monitor `TTPLPFC_ac_cur_ref_pu` and duty cycle output in CCS at 200V
High	Verify ADC input voltages do not exceed reference voltage at 200V
High	Capture raw ADC counts during distorted operation to check for clipping
Medium	Confirm C211 & C204 are populated
Medium	Try increasing `TTPLPFC_ac_cur_ref_pu` to rule out near-zero reference issues
Medium	Share current PI gain values (Kp, Ki) for review

Please provide the scope captures and CCS data when available. The combination of the ADC clipping check and the PI gain review will most likely identify the root cause.

RE: TIDM-02013: Issues of Relay Closing and Overcurrent Protection Triggering on the Circuit Board Caused by Driver Loss in the PFC Stage

Wang Xuesong — Tue, 21 Apr 2026 12:54:24 GMT

TTPLPFC_duty1_pu = (TTPLPFC_gi1_out + TTPLPFC_gi1_out_ff_scale*(TTPLPFC_ac_vol_sensed_pu *
(float32_t)TTPLPFC_VAC_MAX_SENSE /
TTPLPFC_VDCBUS_MAX_SENSE)-
TTPLPFC_inductor_voltage_drop_feedforward)/
(TTPLPFC_vBus_sensed_pu);

I revised the current loop code according to the aforementioned formula. At low input voltage, the input current can track the voltage well. However, when the input voltage is increased, the current becomes distorted, and the driver waveform of the PH2 branch is observed to be missing. In addition, when measuring the waveforms of the two low-side switches, the arrival of the PH2 branch driver seems to affect the PH1 branch driver. Although this does not impair the driving capability of the switching transistors, it is clearly an abnormal phenomenon.

My questions are:

Why does the input current distortion occur when the input voltage exceeds 150 V, and the distortion becomes more severe as the voltage increases?
Why is the driver signal interfered by the other branch?

RE: TIDM-02013: Issues of Relay Closing and Overcurrent Protection Triggering on the Circuit Board Caused by Driver Loss in the PFC Stage

Wang Xuesong — Mon, 20 Apr 2026 13:18:20 GMT

Currently in Experiment 3: The driver operates normally at startup. When the input voltage is increased to 200 V, the driver begins to lose pulses, and the input voltage and current waveforms become distorted.

The PWM waveforms generated by the DSP before the driver isolators are identical to those after the isolators, indicating that the problem is not caused by the isolation chips or the circuits after them.

The input voltage and current waveforms track well at the zero-crossing point, so it can be inferred that the phase-locked loop (PLL) is not the cause.

Is the problem related to sampling or the current loop?

RE: TIDM-02013: Issues of Relay Closing and Overcurrent Protection Triggering on the Circuit Board Caused by Driver Loss in the PFC Stage

Links — Fri, 17 Apr 2026 08:07:22 GMT

Thanks for providing the schematics! This clarifies a lot. I've been reviewing them, and I have some additional thoughts and questions.

1. vBus Voltage Instability & Dropping Voltage:

Looking at the schematic, the output capacitor (C188, 10uF 25V) looks undersized for a PFC stage, especially given the potential for voltage spikes during switching. This is a prime suspect in the vBus voltage instability. A small capacitor will have difficulty holding the voltage during the boost phase and is more susceptible to ripple.

What is the actual datasheet of the 10uF capacitor (C188) used? We need to know its ESR and ripple current rating.
The schematic shows a 220uF/160V capacitor (C185) in parallel. Is this capacitor populated on your board? If not, adding it back in is a crucial first step.
Can you measure the ripple voltage on the vBus? A scope capture of the vBus voltage during the boost phase would be very useful.
What is the voltage rating of C188 and C185? Verify that your capacitors are rated to at least 200V.

2. Phase Difference & Current Sensing:

You were spot on in identifying the swapped current sensing connections! I'm glad you corrected the ADC assignments in CCS.

Following the CCS correction and verifying the hardware connections, are you still seeing the reduced drive cycle (1/8 duty cycle)? This is the most important question at this point. If the corrected mapping hasn't resolved this, it points to a deeper issue in the current loop or driver.
Looking at the schematic, R149 and R132 are both 3.48kΩ. Are these values accurate and consistent on your board? A mismatch in these resistors would cause an imbalance in the current sensing.
The Hall effect sensors (IAC_PH1_SENSOR, IAC_PH2_SENSOR) have 100pF caps (C211 & C204) to ground. Are these caps populated? Missing these could cause instability in the current sensing.

3. Gate Drive & Switching (Regarding the 1/8 cycle issue):

The gate drive circuitry around the GaN FETs looks relatively standard, but a few things are worth checking.

You mention gate drive loss in the positive half-cycle initially. Is the issue only happening in the positive half-cycle, even with the correctly mapped current sensing?
Can you measure the voltage on the gate drive signals (TTPLPFC_HIGH_FREQ_PH1_H and TTPLPFC_HIGH_FREQ_PH2_H) during the operation? This will help determine if the driver is actually attempting to turn on the FETs.
Is the bootstrap capacitor (C187) functioning properly? This capacitor is used to provide the voltage to drive the high-side FET.

4. Relay Closing & OCP:

Let’s hold off on further relay testing until we resolve the vBus instability and the drive cycle issue. Attempting to close the relay with an unstable PFC stage will continue to trigger OCP.

To help us understand the situation further:

Please provide the exact part number of the GaN FETs being used.
Please share a screenshot of your CCS current loop configuration settings (Kp, Ki, etc.).

I anticipate the undersized output capacitor is a major contributing factor here. Let's focus on verifying that and getting the drive cycles working correctly.

RE: TDA4VM: Inquiry About Online Debugging Support for DCCSetup_2023_10_10.exe and Alternative ISP Tuning Tools

Eirwen — Wed, 15 Apr 2026 02:23:46 GMT

感谢您对TI产品的关注！关于您的咨询，我看您在英文E2E与我们的工程师Gang在沟通。那这边的帖子我就关闭了。有疑问请继续与Gang直接沟通。

TDA4VM: Inquiry About Online Debugging Support for DCCSetup_2023_10_10.exe and Alternative ISP Tuning Tools

tang yuanzheng — Fri, 10 Apr 2026 02:46:47 GMT

Part Number: TDA4VM

Hi TI Team,

I’m currently working with the TDA4VM ISP pipeline and using the DCCSetup_2023_10_10.exe tool to generate DCC configuration files for image tuning.

I have two questions:

Does DCCSetup_2023_10_10.exe support online (real-time) debugging?
Specifically, can I adjust ISP parameters (e.g., GLBCE, noise reduction, color correction) in real time while the system is running, and see the changes reflected immediately in the output video stream?
Are there other recommended tools or methods for online ISP tuning on TDA4VM?
I’ve heard about the TI Image Tuning Tool (ITT) and ti_tuning_app, but I’m not sure if they are compatible with this version of DCCSetup or the latest Processor SDK (e.g., PSDK 8.x or 9.x). Could you please clarify the current best practice for real-time ISP parameter tuning?

Any guidance or documentation links would be greatly appreciated!

Best regards,
Shenzhen Jueming Artificial Intelligence Co., Ltd.

RE: TDA4VM: Inquiry About Online Debugging Support for DCCSetup_2023_10_10.exe and Alternative ISP Tuning Tools

Eirwen — Fri, 10 Apr 2026 02:57:48 GMT

Hello, we have received your case and the investigation will take some time. Thank you for your patience.

RE: TIDM-02013: Voltage distortion across the switching transistor under sub-resonant operation

Lydia — Wed, 08 Apr 2026 00:06:19 GMT

Hello, we have received your case and the investigation will take some time. Thank you for your patience.

RE: TIDM-02013: Issues of Relay Closing and Overcurrent Protection Triggering on the Circuit Board Caused by Driver Loss in the PFC Stage

Wang Xuesong — Tue, 07 Apr 2026 11:34:31 GMT

Hello, Sorry to bother you again. Could you please help me solve this problem? I cannot figure out where the issue lies.

RE: TMS320C6713B: tms320c6713 dsk gerber

Taylor — Thu, 02 Apr 2026 08:22:37 GMT

搜这个文件名就行

TMS320C6713B: tms320c6713 dsk gerber

LI LI — Thu, 02 Apr 2026 07:46:06 GMT

Part Number: TMS320C6713B

你好。我现在正基于TMS320C6713 DSK 开发板进行TMS320C6713的应用。需要gerber文件进行参考。

RE: TMS320C6713B: tms320c6713 dsk gerber

LI LI — Thu, 02 Apr 2026 08:18:08 GMT

网上的其他链接如何搜索能否给个提示

RE: TMS320C6713B: tms320c6713 dsk gerber

LI LI — Thu, 02 Apr 2026 08:14:50 GMT

网上的其他链接如何搜索能否给一个提示

RE: TMS320C6713B: tms320c6713 dsk gerber

Taylor — Thu, 02 Apr 2026 08:05:12 GMT

TMS320C6713B是一款较老的芯片，支持有限，下面链接提到的6713_dsk_gerber.pdf已经失效，

TMS320C6713B: PCB guidelines for ZDP BGA 272 package - Processors forum - Processors - TI E2E support forums

网上还有其他链接有这个文件，但并不是官方提供，您可以搜一下

RE: TMS320C6713B: tms320c6713 dsk gerber

Taylor — Thu, 02 Apr 2026 07:47:11 GMT

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: TIDM-02013: Issues of Relay Closing and Overcurrent Protection Triggering on the Circuit Board Caused by Driver Loss in the PFC Stage

Wang Xuesong — Sat, 28 Mar 2026 03:32:06 GMT

Is it because the connected load is too small?

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Catalan	Hmong Daw	Romanian
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Chinese Traditional	Indonesian	Slovak
Czech	Italian	Slovenian
Danish	Japanese	Spanish
Dutch	Klingon	Swedish
English	Korean	Thai
Estonian	Latvian	Turkish
Finnish	Lithuanian	Ukrainian
French	Malay	Urdu
German	Maltese	Vietnamese
Greek	Norwegian	Welsh
Haitian Creole	Persian

Arabic	Hebrew	Polish
Bulgarian	Hindi	Portuguese
Catalan	Hmong Daw	Romanian
Chinese Simplified	Hungarian	Russian
Chinese Traditional	Indonesian	Slovak
Czech	Italian	Slovenian
Danish	Japanese	Spanish
Dutch	Klingon	Swedish
English	Korean	Thai
Estonian	Latvian	Turkish
Finnish	Lithuanian	Ukrainian
French	Malay	Urdu
German	Maltese	Vietnamese
Greek	Norwegian	Welsh
Haitian Creole	Persian

Arabic	Hebrew	Polish
Bulgarian	Hindi	Portuguese
Catalan	Hmong Daw	Romanian
Chinese Simplified	Hungarian	Russian
Chinese Traditional	Indonesian	Slovak
Czech	Italian	Slovenian
Danish	Japanese	Spanish
Dutch	Klingon	Swedish
English	Korean	Thai
Estonian	Latvian	Turkish
Finnish	Lithuanian	Ukrainian
French	Malay	Urdu
German	Maltese	Vietnamese
Greek	Norwegian	Welsh
Haitian Creole	Persian