1.黃色:Q8 DFET VGS電壓
3.粉紅色: MCU 3.3V電源
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Parallel FET oscillation. Some FETs will work well when connected directly in parallel, some need some gate isolation to avoid oscillation. As one FET turns off it sheds load to another which then dumps its load back to the others which results in a high frequency oscillation which can result in large voltages and damage. When this is described in industry literature, it is often recommended to use a small individual gate resistance perhaps 10% of the total resistance or a ferrite bead to isolate the gates to suppress the oscillation. This allows the gates to receive about the same drive signal but have enough isolation to prevent oscillation. In several designs where we have used the CSD FETs in parallel we needed to use beads or small resistors to prevent oscillation. Check your design/schematic, inspect the gate signals during switching. Note that a probe on a gate can alter the circuit. When providing isolation it is good to follow the guideline to maintain most of the drive resistance as a common value so the FETs switch at the same time. If completely separate resistances are used from the driver component tolerances could allow the parallel FET to turn off at different times resulting in the last FET to switch off to have the full short circuit load, that FET might be overstressed in that situation and fail.