C6655 DSP 主频配置

Lingcon M

Expert 1608 points

Other Parts Discussed in Thread: TMS320C6655

Hello Shine Zhang，

请教一个关于C6655 DSP 主频配置问题：

C6655 的主频是需要自己写驱动来配置吗（配置PLLD ，PLLM等）？

根据C6655 datasheet，如Figure 6-3. Main PLL and PLL Controller，

CORECLK(N|P)的输入一般是多少？

哪儿能下载到已经配置好CPU主频的gel文件，

我到TI CCS的安装路径下，只看到了C6657L 的gel文件，没发现c6655的gel 文件！

非常感谢！

BRS，

Meng

7 年多前

0 Shine 7 年多前

TI__Guru**** 357097 points

在数据手册第41页上的时序要求，所以CORECLKIN的输入频率范围40MHz~312.5MHz。
1 tc(CORCLKN) Cycle time _ CORECLKN cycle time 3.2 25 ns
1 tc(CORECLKP) Cycle time _ CORECLKP cycle time 3.2 25 ns

http://www.ti.com/lit/ds/symlink/tms320c6655.pdf

主频的配置可以参考C:\ti\ccsv6\ccs_base\emulation\boards\evmc6657l\gel，具体PLL寄存器的值要根据你板子的输入时钟频率做相应的修改。各个system clock的要求参考手册6.6.1.1 Internal Clocks and Maximum Operating Frequencies

0 Lingcon M 7 年多前回复 Shine

Expert 1608 points

Hello Shine Zhang，

谢谢您的回复。

也就是说C6655 能直接用C6657L的gel文件，只要设置符合C6655 的主频以及DDR时钟频率？

如果两者gel可以通用的话，C6655 各个memory的地址与C6657的各个memory地址范围及大小都一样，

我的理解有没有偏差。

非常感谢！

BRS，

Meng

0 Shine 7 年多前回复 Lingcon M

TI__Guru**** 357097 points

对，只是C6655比C6657少一个core，所以core1 L1, L2这部分在c6655 memory map上是reserved的。

0 Lingcon M 7 年多前回复 Shine

Expert 1608 points

Hello Shine Zhang，

我用了一下一下C6657L的 gel文件加载，并通过仿真器连接C6655 内核，

连接成功，但是load program，code 不能go main（）。

如下为加载gel的信息：

程序出现好多次下列信息，

DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed

我怀疑不能go main的原因是 DDR3初始化失败，我们用的DDR3 size 是 1GB，这个问题如何解决？

另外，第一次加载gel 文件时，出现DNUM没有定义

然后我在gel 文件头部，添加了#define DNUM 0 ，这种直接添加的方式对不？

C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: C6657L GEL file Ver is 1.006
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=12, md=4!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1200.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 400.0 MHz, SYSCLK5 = 240.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 18.75 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output: ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^EERROOORRRR: Convergence Error****************************
C66xx_0: GEL Output: IFRDY bit is SET: DDR3 Interface Ready
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: PLL and DDR3 Initialization failed ...
C66xx_0: GEL Output: configSGMIISerdes Setup... Begin
C66xx_0: GEL Output: SGMII SERDES has been configured.
C66xx_0: GEL Output: Enabling EDC ...
C66xx_0: GEL Output: L1P error detection logic is enabled.
C66xx_0: GEL Output: L2 error detection/correction logic is enabled.
C66xx_0: GEL Output: MSMC error detection/correction logic is enabled.
C66xx_0: GEL Output: Enabling EDC ...Done
C66xx_0: GEL Output: Global Default Setup... Done.
C66xx_0: GEL Output: Invalidate All Cache...
C66xx_0: GEL Output: Invalidate All Cache... Done.
C66xx_0: GEL Output: GEL Reset...
C66xx_0: GEL Output: GEL Reset... Done.
C66xx_0: GEL Output: Disable all EDMA3 interrupts and events.

非常感谢！

BRS，

Meng

0 Shine 7 年多前回复 Lingcon M

TI__Guru**** 357097 points

DDR3的配置需要根据你板子上的DDR3做参数调整。

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C6655 DSP 主频配置