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自制板的DDR3初始化

在自制的6678板子上测试DDR3,用的是KeyStone_STK_V1.1里的的memory_test例程,自制板子中多了一块用来ECC的DDR3,它在ck线的最后一个,与EVM上的ECC位置(在中间)不同,测量了自制板子的DQS和CK的线长之后,使用提供的DDR3 PHY Calc V10直接转换成WRLVL和GATELVE值,并更新到memory_test中的leveling参数,测试fail;log如下:

[C66xx_0] JTAG ID= 0x1009e02f. This is C6678/TCI6608 device, version variant = 1.
DEVSTAT= 0x0000d400. big endian, No boot or EMIF16(NOR FLASH) or UART boot, PLL configuration implies the input clock for core is 80MHz.
SmartReflex VID= 60, required core voltage= 1.084V.
Die ID= 0x1800b007, 0x040467a7, 0x00000000, 0x73da0021
Device speed grade = 1000MHz.
Enable Exception handling...
Initialize DSP main clock = 100.00MHz/1x10 = 1000MHz
check the if the DDR3 registers are mapped. If not, map it
get dsp_board_type...
DSP_Board_Type:C6678_EVM
DDR ECC is disabled.
======================== EVM_DDR_Init cycle:0 ========================
Initialize DDR speed = 66.67MHzx/1x20 = 1333.333MTS
uiRev=0x10000000
initial vale for leveling
PROJECT leveling configuration.
gpDDR_regs->SDRAM_REF_CTRL = 0X80005161,0x00005162

TIME1 = 0X0EF167F3,0X1113783C

TIME2 = 0X204E7FDA,0X30717FE3

TIME3 = 0X559F849F,0X559F86AF

gpDDR_regs->DDR_PHY_CTRL_1 = 0X0010010C,0X0010010F

gpDDR_regs->ZQ_CONFIG = 0X70073DBB,0X70073214

gpDDR_regs->SDRAM_REF_CTRL = 0X00005161,0X0000516

gpDDR_regs->SDRAM_CONFIG = 0X63062A32,0X63062A32

gpDDR_regs->SDRAM_REF_CTRL = 0X00001458,0X00001450

DDR3 leveling pass, STATUS=0XC0000004.
uirev=268435456,before KeyStone_DDR_read_incremental_leveling
Memory pattern filling Test fails at 0x80000000, Write 0x0000000000000000, Readback 0xf6fefbfef7dffffe
Read data at address 0x80000000 8 times again, get: 0xf6fefbfef7dffffe, 0xf6fefbfef7dffffe, 0xf6fefbfef7dffffe, 0xf6fefbfef7dffffe, 0xf6fefbfef7dffffe, 0xf6fefbfef7dffffe, 0xf6fefbfef7dffffe, 0xf6fefbfef7dffffe
Write 0 again and read back 0xf6fefbfef7dffffe, write 0xffffffffffffffff again and read back 0xf6fefbfef7dffffe
Memory pattern filling Test fails at 0x80000008, Write 0x0000000000000000, Readback 0x9b0504e027dfb125
Read data at address 0x80000008 8 times again, get: 0x9b0504e027dfb125, 0x9b0504e027dfb125, 0x9b0504e027dfb125, 0x9b0504e027dfb125, 0x9b0504e027dfb125, 0x9b0504e027dfb125, 0x9b0504e027dfb125, 0x9b0504e027dfb125
Write 0 again and read back 0x9b0504e027dfb125, write 0xffffffffffffffff again and read back 0x9b0504e027dfb125

针对这个测试fail,我有以下问题,还请帮忙解答一下,谢谢:

1,自制板上的DDR是K4B2G1646C,EVM上的DDR是K4B2G1646Q,在自制板测试失败后,想对比一下EVM的初始化配置,发现EVM板DQS测量出的线长与所使用的EXCEL中的数值一致,但是EXCEL中CK的线长与测量的线长都不一致。测量出来的CK线长比EXCEL中的线长要小200~300mil不等的数值,请问为什么EVM的测试还是可以通过呢?

2,EVM的ECC位置在第三,自制板子的ECC位置在第五,请问DDR3 PHY Calc v10可以应用在这种情况下吗?如果可以,在使用上需不需要做出什么样的改变?