由于春节假期,帖子审批以及工程师回复将会有所延迟,敬请谅解.

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TMS320C6678: DDR初始化后读写数据异常

Part Number: TMS320C6678

ti工程师,您好。

背景:我代码是使用pdk库中的ddr初始化示例流程,按照板卡自身的layout布线参数及颗粒手册,通过PHY电子表格得出参数后进行替换,运行状态为板卡DDR初始化后读写数据异常。

随后通过修改DDR_TERM参数从RZQ/6修改为RZQ/4后,有明显改善;

我想问的问题是:

1、通过修改DDR_TERM参数从RZQ/6修改为RZQ/4后,有明显改善,能反推出可疑问题点在哪方面?(硬件外部RZQ参考电阻为240欧)

2、SDCFG寄存器中,DDR_TERM的配置依据是什么呢?

3、SDCFG寄存器中,DYN_ODT内部动态终端电阻的配置依据是什么,为何官方都是失能它?

4、SDCFG寄存器中,drive length配置依据是什么,为何官方使用RZQ/7?

5、DDR初始化后都要进行leveling,那6678的ddr 控制器的leveling是采用的硬件自动leveing还是也需要进行software leveing?

  • 1. 2,3请参考下面的帖子,跟您的问题类似。
    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1039956/tms320c6678-ddr_term-configuration

    DDR_TERM,DYN_ODT这两个参数和RZQ有关,C6678的RZQ是PTV15引脚,接45.3 ohm。可以看一下下面的应用文档。
    https://www.ti.com/lit/an/sprabi1c/sprabi1c.pdf

    4.  我的理解是用drive strength使用来控制信号驱动能力,RZQ/7这个是TI给的建议值。

    5. 是通过software leveling,请看下面的文档。
    https://www.ti.com/lit/an/sprabl2e/sprabl2e.pdf


  • A: "1. 2,3请参考下面的帖子,跟您的问题类似。 "  这个帖子也是我们问的,其中的回答说道对方(ti工程师)并不清楚,没有太多参考意义。所以能以您的理解再解答一下吗?

    B:“”“是通过software leveling,请看下面的文档。”  我说的software leveling是指的通过软件代码计算leveling值,最后写入RATIO斜率寄存器。类似官方推荐的AM335X这个片子,提供了官方的software leveling Tool。然后sprable.pdf中说明c6678是通过控制 寄存器来启用c6678的硬件训练吧,我看手册的理解是这样的,不知道理解对不对,跟您确认一下。  

    DDR不稳定问题已经困扰已久,麻烦工程师再解答一下吧 感谢!

  • 1. 我的理解是DDR_TERM,DYN_ODT这两个参数和RZQ有关,具体要根据pcb板子的走线阻抗来试。

    2. 可以这么理解。另外,是通过spreadsheet来计算leveling的值,然后配置到PHY register。

  • 麻烦再继续解答下我的疑惑:

    根据ti pdk库下提供的示例程序关于ddr3初始化接口,以下红色部分我执行后,发现DDR3_REG_CONFIG_23中得4个RATIO值并没有发生改变,理应levleing完成之后,这个寄存器应该会更新程训练得到的最优值吧? 而且 红色部分执行后,不管延时等待与否,levleing complete都显示已经完成,完全不会出现超时的情况,看起来就行levleing 是无效的一样?

    void ddr3_setup_auto_lvl_1333()
    {
    //int i,TEMP,startlo, stoplo,starthi, stophi;
    int TEMP;
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;

    /* Wait for PLL to lock = min 500 ref clock cycles.
    With refclk = 100MHz, = 5000 ns = 5us */
    sleep_timer(1000);

    /***************** 3.2 DDR3 PLL Configuration ************/
    /* Done before */

    /**************** 3.0 Leveling Register Configuration ********************/
    /* Using partial automatic leveling due to errata */

    /**************** 3.3 Leveling register configuration ********************/
    DDR3_CONFIG_REG_0 &= ~(0x007FE000); // clear ctrl_slave_ratio field
    DDR3_CONFIG_REG_0 |= 0x00200000; // set ctrl_slave_ratio to 0x100
    DDR3_CONFIG_REG_12 |= 0x08000000; // Set invert_clkout = 1
    DDR3_CONFIG_REG_0 |= 0xF; // set dll_lock_diff to 15

    //From 4.2.1 Executing Partial Automatic Leveling -- Start
    DDR3_CONFIG_REG_23 |= 0x00000200; //Set bit 9 = 1 to use forced ratio leveling for read DQS
    //From 4.2.1 Executing Partial Automatic Leveling -- End

    //Values with invertclkout = 1
    /**************** 3.3 Partial Automatic Leveling ********************/
    /*DATA0_WRLVL_INIT_RATIO = 0x78;
    DATA1_WRLVL_INIT_RATIO = 0x76;
    DATA2_WRLVL_INIT_RATIO = 0x72;
    DATA3_WRLVL_INIT_RATIO = 0x76;
    DATA4_WRLVL_INIT_RATIO = 0x69;
    DATA5_WRLVL_INIT_RATIO = 0x69;
    DATA6_WRLVL_INIT_RATIO = 0x5B;
    DATA7_WRLVL_INIT_RATIO = 0x60;
    DATA8_WRLVL_INIT_RATIO = 0x00;

    DATA0_GTLVL_INIT_RATIO = 0xAF;
    DATA1_GTLVL_INIT_RATIO = 0xB1;
    DATA2_GTLVL_INIT_RATIO = 0xA3;
    DATA3_GTLVL_INIT_RATIO = 0xA0;
    DATA4_GTLVL_INIT_RATIO = 0x9B;
    DATA5_GTLVL_INIT_RATIO = 0x9B;
    DATA6_GTLVL_INIT_RATIO = 0x98;
    DATA7_GTLVL_INIT_RATIO = 0x92;
    DATA8_GTLVL_INIT_RATIO = 0x00; */

    //Do a PHY reset. Toggle DDR_PHY_CTRL_1 bit 15 0->1->0
    DDR_DDRPHYC &= ~(0x00008000);
    DDR_DDRPHYC |= (0x00008000);
    DDR_DDRPHYC &= ~(0x00008000);

    /***************** 3.4 Basic Controller and DRAM Configuration ************/
    DDR_SDRFC = 0x0000c34; // enable configuration

    /* DDR_SDTIM1 = 0x1113783C; */
    TEMP = 0;
    TEMP |= 0x8 << 25; // T_RP bit field 28:25
    TEMP |= 0x8 << 21; // T_RCD bit field 24:21
    TEMP |= 0x9 << 17; // T_WR bit field 20:17
    TEMP |= 0x17 << 12; // T_RAS bit field 16:12
    TEMP |= 0x20 << 6; // T_RC bit field 11:6
    TEMP |= 0x7 << 3; // T_RRD bit field 5:3
    TEMP |= 0x4; // T_WTR bit field 2:0
    DDR_SDTIM1 = 0x0AAAE4E2; //TEMP;

    /* DDR_SDTIM2 = 0x30717FE3; */
    TEMP = 0;
    TEMP |= 0x3 << 28; // T_XP bit field 30:28
    TEMP |= 0x71 << 16; // T_XSNR bit field 24:16
    TEMP |= 0x1ff << 6; // T_XSRD bit field 15:6
    TEMP |= 0x4 << 3; // T_RTP bit field 5:3
    TEMP |= 0x3; // T_CKE bit field 2:0
    DDR_SDTIM2 = 0x206B7FDA;//TEMP;

    /* DDR_SDTIM3 = 0x559F86AF; */
    TEMP = 0;
    TEMP |= 0x5 << 28; // T_PDLL_UL bit field 31:28 (fixed value)
    TEMP |= 0x5 << 24; // T_CSTA bit field 27:24 (fixed value)
    TEMP |= 0x4 << 21; // T_CKESR bit field 23:21
    TEMP |= 0x3f << 15; // T_ZQCS bit field 20:15
    TEMP |= 0x6a << 4; // T_RFC bit field 12:4
    TEMP |= 0xf; // T_RAS_MAX bit field 3:0 (fixed value)
    DDR_SDTIM3 = 0x557F867F; //TEMP;

    DDR_DDRPHYC = 0x0010010F;

    DDR_ZQCFG = 0x70073214;

    DDR_PMCTL = 0x0;

    DDR_SDRFC = 0x0000c34; // enable configuration

    /* DDR_SDCFG = 0x63062A32; */
    /* New value with DYN_ODT disabled and SDRAM_DRIVE = RZQ/7 //0x63222A32; // last config write DRAM init occurs */
    TEMP = 0;
    TEMP |= 0x3 << 29; // SDRAM_TYPE bit field 31:29 (fixed value)
    TEMP |= 0x0 << 27; // IBANK_POS bit field 28:27
    TEMP |= 0x3 << 24; // DDR_TERM bit field 26:24
    TEMP |= 0x0 << 21; // DYN_ODT bit field 22:21
    TEMP |= 0x1 << 18; // SDRAM_DRIVE bit field 19:18
    TEMP |= 0x2 << 16; // CWL bit field 17:16
    TEMP |= 0x0 << 14; // NM bit field 15:14
    TEMP |= 0xA << 10; // CL bit field 13:10
    TEMP |= 0x4 << 7; // ROWSIZE bit field 9:7
    TEMP |= 0x3 << 4; // IBANK bit field 6:4
    TEMP |= 0x0 << 3; // EBANK bit field 3:3
    TEMP |= 0x2; // PAGESIZE bit field 2:0
    DDR_SDCFG = 0x63072B33;//TEMP;

    //Wait 600us for HW init to complete
    sleep_timer(100000);

    DDR_SDRFC = 0x0000c34; //0x00001450; //Refresh rate = (7.8*666MHz)

    /**************** 4.2.1 Executing Partial Automatic Leveling ********************/

    DDR_RDWR_LVL_RMP_CTRL = 0x80000000; //enable full leveling

    DDR_RDWR_LVL_CTRL = 0x80000000; //Trigger full leveling - This ignores read DQS leveling result and uses ratio forced value

    //(0x34) instead
    //Wait for min 1048576 DDR clock cycles for leveling to complete = 1048576 * 1.5ns = 1572864ns = 1.57ms.
    //Actual time = ~10-15 ms
    sleep_timer(100000);
    //GEL_TextOut("\nDDR3 initialization is complete.\n");
    }