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TDA4VM: Interrupted registration and use of HW mailbox based on IPC

quansheng zhu
Prodigy 10 points
Part Number: TDA4VM

int32_t Ipc_setCoreEventId(uint32_t selfId, Ipc_MbConfig* cfg, uint32_t intrCnt)

/* Allocate the last 5 interrupts for IPC. Note that the IR allocation is
* static so this needs to be carefully set. Currently first interrupt is
* used by UDMA and middle one's are used by other modules like CPSW9G so
* we are using last 5 as a safe option.
*/

There are two questions.

1. The above functions are the functions to get the interrupt configuration call. The content annotated in the function is the mailbox for IPC. Can only the last five interrupts be used? I understand that there are 12 HW mailboxes, each with four interrupts? Isn't there 48 interrupts in total?

2. By looking at the sdk-rtos-0800 code, I can see that there is a pair of vring between each pair of processors. Finally, the maibox distinguishes the sending or receiving direction of vring by sending 0 or 1.

Can there only be one pair of vring between a pair of processors?

Please help to answer, thank you.

  • 0
    TI__Guru* 81370 points

    Hi we have got your problem and ask help from the e2e, please expect the response. Thanks!

  • 0 回复 Cherry Zhou
    TI__Guru* 81370 points

    Hello,

    Sorry for the delay in response.

    1. Yes, there are 12 Mailbox clusters with 4 interrupts each, resulting in a total of 48 interrupts. These are the total number of interrupts generated out from the Mailbox IP, and are shared between all the R5F, DSP and A72 processors. There are also not enough separate interrupts to use between all the different pairs of processors, so the IPC communication on some processors use the same interrupt but different Mailbox FIFOs for IPC.

    You can refer to the g_Ipc_MailboxInfo variable in <RTOS SDK>/<pdk>/packages/ti/drv/ipc/soc/V1/ipc_soc.c file for the Mailbox assignments between different processors on TDA4VM. The data follows <Rx mbox-data> and <Tx mbox-data>.

    2. Correct. Each vring pair forms the base IPC transport between a pair of processors. It is possible to support multiple vrings technically, but TI SDK is designed to support only a single pair.

    Is the question w.r.t IPC between two remote processors or between a A72 Linux and a remote processor?     

    Thanks,

    Cherry

  • +1
    Prodigy 10 points

    I'm sorry to be delayed by some things.

    /* Allocate the last 5 interrupts for IPC. Note that the IR allocation is
    * static so this needs to be carefully set. Currently first interrupt is
    * used by UDMA and middle one's are used by other modules like CPSW9G so
    * we are using last 5 as a safe option.
    */

    The previous answer still didn't explain that the comment said that only the last five interrupts can be allocated to IPC. Why is there 48 interrupts and the comment said that only the last five interrupts can be allocated? What are these five interruptions? What does it have to do with the 48 interruptions.

  • +1 回复 quansheng zhu
    TI__Guru* 81370 points

    Hi,

    48 interrupts are the overall interrupts coming out of Mailbox IP. They are not all connected to the same remote processor (none of the other remoteprocs will get Mailbox interrupts if so), and are distributed between all the A72, R5F, C66x and C71x DSP processors.

    Ideally, you would need 1 interrupt each from each of the other remote processors a processor is talking to. You typically have 1 MCU Lockstep R5F + 4 Main Split R5Fs + 3 DSPs + 1 SMP A72 for a total of 9 processors, and would typically need 8 interrupts if using dedicated interrupts for each remote processor.

    We don't have enough interrupts to allocate exclusively (9 * 8 = 72), so some interrupts are shared. RTOS cores use 5 interrupts to talk to 8 other processors using different FIFOs. I hope this makes it clear.

    Hope this is helpful!

    Thanks,

    Cherry