首先，感谢各位看帖，关于CPU引脚的配置，我针对代码有一些疑问。
我看到不管是xload还是uboot，都有对cpu引脚寄存器的配置。如下：
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))
这个首先DIS了引脚内部PU/PD的功能，后面又跟了一个PTD，这个是不是多此一举？我看到引脚配置工具里面也只有可以单选的。
还有cpu手册里面的几个概念：
5. BALL RESET STATE: The state of the terminal at reset (power up).
– 0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor.
– 1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor.
– Z: High-impedance
– L: High-impedance with an active pulldown resistor
– H: High-impedance with an active pullup resistor
6. BALL RESET REL. STATE: The state of the terminal at reset release.
– 0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor.
– 1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor.
– Z: High-impedance
– L: High-impedance with an active pulldown resistor
– H : High-impedance with an active pullup resistor
上面这个两个reset state分别指的是什么呢？
像上面图中的sdrc_d0这种引脚，显示ball reset state 为L，ball reset rel. state为Z，我该怎么理解？或者说我该如何根据这些数据配置uboot或者xload里面的引脚寄存器？假设外设接到了DDR2的数据总线。
问题很简单，都是一些基本概念，还望不要鄙视我。
有知道的，请指教一下吧。闹了好久也不是十分的理解。
谢谢了！