设备树配置如下
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
/ {
compatible = "ti,am642-evm", "ti,am642";
model = "Texas Instruments AM642 EVM";
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x100000>;
no-map;
};
main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa2100000 0x00 0xf00000>;
no-map;
};
main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3000000 0x00 0x100000>;
no-map;
};
main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa3100000 0x00 0xf00000>;
no-map;
};
mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4000000 0x00 0x100000>;
no-map;
};
mcu_m4fss_memory_region: m4f-memory@a4100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa4100000 0x00 0xf00000>;
no-map;
};
rtos_ipc_memory_region: ipc-memories@a5000000 {
reg = <0x00 0xa5000000 0x00 0x00800000>;
alignment = <0x1000>;
no-map;
};
};
evm_12v0: fixedregulator-evm12v0 {
/* main DC jack */
compatible = "regulator-fixed";
regulator-name = "evm_12v0";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-always-on;
regulator-boot-on;
};
vsys_5v0: fixedregulator-vsys5v0 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vsys_3v3: fixedregulator-vsys3v3 {
/* output of LM5140 */
compatible = "regulator-fixed";
regulator-name = "vsys_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&evm_12v0>;
regulator-always-on;
regulator-boot-on;
};
vdd_mmc1: fixed-regulator-sd {
/* TPS2051BD */
compatible = "regulator-fixed";
regulator-name = "vdd_mmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
enable-active-high;
vin-supply = <&vsys_3v3>;
};
vddb: fixedregulator-vddb {
compatible = "regulator-fixed";
regulator-name = "vddb_3v3_display";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_3v3>;
regulator-always-on;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_light_pins_default>;
run {
label = "run";
gpios = <&main_gpio0 57 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "run";
};
bf {
label = "bf";
gpios = <&main_gpio0 61 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "bf";
};
sf {
label = "sf";
gpios = <&main_gpio0 46 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "sf";
};
stop {
label = "stop";
gpios = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "stop";
};
};
display_74hc595pw {
compatible = "ct-74hc595pw";
pinctrl-names = "default";
pinctrl-0 = <&display_74hc595pw_pins_default>;
disp_clk = <&main_gpio1 44 GPIO_ACTIVE_LOW>;
disp_dat = <&main_gpio1 45 GPIO_ACTIVE_LOW>;
disp_rst = <&main_gpio1 46 GPIO_ACTIVE_LOW>;
disp_oe = <&main_gpio1 42 GPIO_ACTIVE_LOW>;
};
di_do {
compatible = "ct_di_do";
pinctrl-names = "default";
pinctrl-0 = <&di_do_pins_default>;
di0 = <&main_gpio0 34 GPIO_ACTIVE_LOW>;
di1 = <&main_gpio0 42 GPIO_ACTIVE_LOW>;
di2 = <&main_gpio0 41 GPIO_ACTIVE_LOW>;
di3 = <&main_gpio0 36 GPIO_ACTIVE_LOW>;
do0 = <&main_gpio0 31 GPIO_ACTIVE_LOW>;
do1 = <&main_gpio0 35 GPIO_ACTIVE_LOW>;
do2 = <&main_gpio0 38 GPIO_ACTIVE_LOW>;
do3 = <&main_gpio0 37 GPIO_ACTIVE_LOW>;
};
ct_at88sc {
pinctrl-names = "default";
pinctrl-0 = <&at88sc_pins_default>;
compatible = "ct,at88sc";
at88sc_gpio_scl = <&main_gpio0 43 GPIO_ACTIVE_LOW>;
at88sc_gpio_sda = <&main_gpio0 44 GPIO_ACTIVE_LOW>;
};
transceiver1: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
};
transceiver2: can-phy1 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
max-bitrate = <5000000>;
};
icssg0_eth: icssg0-eth {
compatible = "ti,am642-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&pru_icssg0_mii_g_rt_pins_default>;
sram = <&oc_sram>;
ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
mii-g-rt = <&icssg0_mii_g_rt>;
mii-rt = <&icssg0_mii_rt>;
iep = <&icssg0_iep0>, <&icssg0_iep1>;
interrupt-parent = <&icssg0_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
<&main_pktdma 0xc101 15>, /* egress slice 0 */
<&main_pktdma 0xc102 15>, /* egress slice 0 */
<&main_pktdma 0xc103 15>, /* egress slice 0 */
<&main_pktdma 0xc104 15>, /* egress slice 1 */
<&main_pktdma 0xc105 15>, /* egress slice 1 */
<&main_pktdma 0xc106 15>, /* egress slice 1 */
<&main_pktdma 0xc107 15>, /* egress slice 1 */
<&main_pktdma 0x4100 15>, /* ingress slice 0 */
<&main_pktdma 0x4101 15>, /* ingress slice 1 */
<&main_pktdma 0x4102 0>, /* mgmnt rsp slice 0 */
<&main_pktdma 0x4103 0>; /* mgmnt rsp slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1",
"rxmgm0", "rxmgm1";
icssg0_emac0: ethernet-mii0 {
phy-handle = <&icssg0_phy0>;
phy-mode = "mii";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
icssg0_emac1: ethernet-mii1 {
phy-handle = <&icssg0_phy1>;
phy-mode = "mii";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
icssg1_eth: icssg1-eth {
compatible = "ti,am642-icssg-prueth";
pinctrl-names = "default";
pinctrl-0 = <&pru_icssg1_mii_g_rt_pins_default>;
sram = <&oc_sram>;
ti,prus = <&pru1_0>, <&rtu1_0>, <&tx_pru1_0>, <&pru1_1>, <&rtu1_1>, <&tx_pru1_1>;
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
"ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";
ti,pruss-gp-mux-sel = <2>, /* MII mode */
<2>,
<2>,
<2>, /* MII mode */
<2>,
<2>;
mii-g-rt = <&icssg1_mii_g_rt>;
mii-rt = <&icssg1_mii_rt>;
iep = <&icssg1_iep0>, <&icssg1_iep1>;
interrupt-parent = <&icssg1_intc>;
interrupts = <24 0 2>, <25 1 3>;
interrupt-names = "tx_ts0", "tx_ts1";
dmas = <&main_pktdma 0xc200 15>, /* egress slice 0 */
<&main_pktdma 0xc201 15>, /* egress slice 0 */
<&main_pktdma 0xc202 15>, /* egress slice 0 */
<&main_pktdma 0xc203 15>, /* egress slice 0 */
<&main_pktdma 0xc204 15>, /* egress slice 1 */
<&main_pktdma 0xc205 15>, /* egress slice 1 */
<&main_pktdma 0xc206 15>, /* egress slice 1 */
<&main_pktdma 0xc207 15>, /* egress slice 1 */
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
<&main_pktdma 0x4201 15>, /* ingress slice 1 */
<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1",
"rxmgm0", "rxmgm1";
icssg1_emac0: ethernet-mii0 {
status = "disabled";
fixed-link;
};
icssg1_emac1: ethernet-mii1 {
phy-handle = <&cpsw3g_phy1>;
phy-mode = "mii";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};
&main_r5fss0_core0 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
memory-region = <&main_r5fss0_core0_dma_memory_region>,
<&main_r5fss0_core0_memory_region>;
};
&main_r5fss0_core1 {
mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
memory-region = <&main_r5fss0_core1_dma_memory_region>,
<&main_r5fss0_core1_memory_region>;
};
&main_r5fss1_core0 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
memory-region = <&main_r5fss1_core0_dma_memory_region>,
<&main_r5fss1_core0_memory_region>;
};
&main_r5fss1_core1 {
mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
memory-region = <&main_r5fss1_core1_dma_memory_region>,
<&main_r5fss1_core1_memory_region>;
};
&mcu_m4fss {
mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
memory-region = <&mcu_m4fss_dma_memory_region>,
<&mcu_m4fss_memory_region>;
};
&main_pmx0 {
main_mmc1_pins_default: main-mmc1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
>;
};
main_uart0_pins_default: main-uart0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
>;
};
main_uart1_pins_default: main-uart1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01a4, PIN_INPUT, 7) /* (U1) PRG0_PRU0_GPO17.GPIO1_17 */
AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
>;
};
main_uart2_pins_default: main-uart2-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01a8, PIN_INPUT, 7) /* (V1) PRG0_PRU0_GPO18.GPIO1_18 */
AM64X_IOPAD(0x0238, PIN_INPUT, 3) /* (B16) UART0_CTSn.UART2_RXD */
AM64X_IOPAD(0x023c, PIN_OUTPUT, 3) /* (A16) UART0_RTSn.UART2_TXD */
>;
};
main_uart3_pins_default: main-uart3-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01ac, PIN_INPUT, 7) /* (W1) PRG0_PRU0_GPO19.GPIO1_19 */
AM64X_IOPAD(0x0248, PIN_INPUT, 4) /* (D16) UART1_CTSn.UART3_RXD */
AM64X_IOPAD(0x024c, PIN_OUTPUT, 4) /* (E16) UART1_RTSn.UART3_TXD */
>;
};
main_uart5_pins_default: main-uart5-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0084, PIN_INPUT, 2) /* (P16) GPMC0_ADVn_ALE.UART5_RXD */
AM64X_IOPAD(0x0088, PIN_OUTPUT, 2) /* (R18) GPMC0_OEn_REn.UART5_TXD */
>;
};
main_uart6_pins_default: main-uart6-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x020c, PIN_INPUT, 5) /* (C13) SPI0_CS1.UART6_RXD */
AM64X_IOPAD(0x0220, PIN_OUTPUT, 5) /* (D14) SPI1_CS1.UART6_TXD */
>;
};
main_spi0_pins_default: main-spi0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
>;
};
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0260, PIN_OUTPUT, 0) /* (A18) I2C0_SCL */
AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */
>;
};
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
>;
};
mdio_pins_default: mdio-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x015c, PIN_OUTPUT_PULLUP, 4) /* (Y6) PRG1_MDIO0_MDC.MDIO0_MDC */
AM64X_IOPAD(0x0158, PIN_INPUT_PULLUP, 4) /* (AA6) PRG1_MDIO0_MDIO.MDIO0_MDIO */
>;
};
cpsw_rmii1_pins_default: cpsw_rmii1_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0154, PIN_INPUT, 5) /* (V12) PRG1_PRU1_GPO19.RMII1_CRS_DV */
AM64X_IOPAD(0x0124, PIN_INPUT, 5) /* (V15) PRG1_PRU1_GPO7.RMII1_RXD0 */
AM64X_IOPAD(0x012c, PIN_INPUT, 5) /* (V14) PRG1_PRU1_GPO9.RMII1_RXD1 */
AM64X_IOPAD(0x00dc, PIN_INPUT, 5) /* (U15) PRG1_PRU0_GPO9.RMII1_RX_ER */
AM64X_IOPAD(0x0130, PIN_OUTPUT, 5) /* (W14) PRG1_PRU1_GPO10.RMII1_TXD0 */
AM64X_IOPAD(0x014c, PIN_OUTPUT, 5) /* (AA14) PRG1_PRU1_GPO17.RMII1_TXD1 */
AM64X_IOPAD(0x0150, PIN_OUTPUT, 5) /* (Y13) PRG1_PRU1_GPO18.RMII1_TX_EN */
AM64X_IOPAD(0x00e0, PIN_INPUT, 5) /* (U14) PRG1_PRU0_GPO10.RMII_REF_CLK */
>;
};
icssg0_mdio_pins_default: icssg0_mdio_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
>;
};
pru_icssg0_mii_g_rt_pins_default: pru_icssg0_mii_g_rt_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x01a0, PIN_INPUT, 1) /* (U4) PRG0_PRU0_GPO16.PR0_MII_MT0_CLK */
AM64X_IOPAD(0x019c, PIN_OUTPUT, 0) /* (T5) PRG0_PRU0_GPO15.PR0_MII0_TXEN */
AM64X_IOPAD(0x0198, PIN_OUTPUT, 0) /* (V4) PRG0_PRU0_GPO14.PR0_MII0_TXD3 */
AM64X_IOPAD(0x0194, PIN_OUTPUT, 0) /* (R6) PRG0_PRU0_GPO13.PR0_MII0_TXD2 */
AM64X_IOPAD(0x0190, PIN_OUTPUT, 0) /* (AA3) PRG0_PRU0_GPO12.PR0_MII0_TXD1 */
AM64X_IOPAD(0x018c, PIN_OUTPUT, 0) /* (Y3) PRG0_PRU0_GPO11.PR0_MII0_TXD0 */
AM64X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA2) PRG0_PRU0_GPO4.PR0_MII0_RXDV */
AM64X_IOPAD(0x0178, PIN_INPUT, 1) /* (T3) PRG0_PRU0_GPO6.PR0_MII_MR0_CLK */
AM64X_IOPAD(0x016c, PIN_INPUT, 1) /* (V2) PRG0_PRU0_GPO3.PR0_MII0_RXD3 */
AM64X_IOPAD(0x0168, PIN_INPUT, 1) /* (U2) PRG0_PRU0_GPO2.PR0_MII0_RXD2 */
AM64X_IOPAD(0x0188, PIN_INPUT, 1) /* (AA5) PRG0_PRU0_GPO10.PR0_MII0_CRS */
AM64X_IOPAD(0x0174, PIN_INPUT, 1) /* (R3) PRG0_PRU0_GPO5.PR0_MII0_RXER */
AM64X_IOPAD(0x0164, PIN_INPUT, 1) /* (R4) PRG0_PRU0_GPO1.PR0_MII0_RXD1 */
AM64X_IOPAD(0x0160, PIN_INPUT, 1) /* (Y1) PRG0_PRU0_GPO0.PR0_MII0_RXD0 */
AM64X_IOPAD(0x0184, PIN_INPUT, 1) /* (W6) PRG0_PRU0_GPO9.PR0_MII0_COL */
AM64X_IOPAD(0x01f0, PIN_INPUT, 1) /* (AA4) PRG0_PRU1_GPO16.PR0_MII_MT1_CLK */
AM64X_IOPAD(0x01ec, PIN_OUTPUT, 0) /* (U5) PRG0_PRU1_GPO15.PR0_MII1_TXEN */
AM64X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (U6) PRG0_PRU1_GPO14.PR0_MII1_TXD3 */
AM64X_IOPAD(0x01e4, PIN_OUTPUT, 0) /* (T6) PRG0_PRU1_GPO13.PR0_MII1_TXD2 */
AM64X_IOPAD(0x01e0, PIN_OUTPUT, 0) /* (Y4) PRG0_PRU1_GPO12.PR0_MII1_TXD1 */
AM64X_IOPAD(0x01dc, PIN_OUTPUT, 0) /* (W4) PRG0_PRU1_GPO11.PR0_MII1_TXD0 */
AM64X_IOPAD(0x01c0, PIN_INPUT, 1) /* (W3) PRG0_PRU1_GPO4.PR0_MII1_RXDV */
AM64X_IOPAD(0x01c8, PIN_INPUT, 1) /* (R5) PRG0_PRU1_GPO6.PR0_MII_MR1_CLK */
AM64X_IOPAD(0x01bc, PIN_INPUT, 1) /* (T4) PRG0_PRU1_GPO3.PR0_MII1_RXD3 */
AM64X_IOPAD(0x01b8, PIN_INPUT, 1) /* (V3) PRG0_PRU1_GPO2.PR0_MII1_RXD2 */
AM64X_IOPAD(0x01d8, PIN_INPUT, 1) /* (V6) PRG0_PRU1_GPO10.PR0_MII1_CRS */
AM64X_IOPAD(0x01c4, PIN_INPUT, 1) /* (P4) PRG0_PRU1_GPO5.PR0_MII1_RXER */
AM64X_IOPAD(0x01b4, PIN_INPUT, 1) /* (W2) PRG0_PRU1_GPO1.PR0_MII1_RXD1 */
AM64X_IOPAD(0x01b0, PIN_INPUT, 1) /* (Y2) PRG0_PRU1_GPO0.PR0_MII1_RXD0 */
AM64X_IOPAD(0x01d4, PIN_INPUT, 1) /* (Y5) PRG0_PRU1_GPO9.PR0_MII1_COL */
>;
};
icssg1_mdio_pins_default: icssg1_mdio_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x015c, PIN_OUTPUT_PULLUP, 0) /* (Y6) PRG1_MDIO0_MDC */
AM64X_IOPAD(0x0158, PIN_INPUT_PULLUP, 0) /* (AA6) PRG1_MDIO0_MDIO */
>;
};
pru_icssg1_mii_g_rt_pins_default: pru_icssg1_mii_g_rt_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0148, PIN_INPUT, 1) /* (Y10) PRG1_PRU1_GPO16.PR1_MII_MT1_CLK */
AM64X_IOPAD(0x0144, PIN_OUTPUT, 0) /* (Y11) PRG1_PRU1_GPO15.PR1_MII1_TXEN */
AM64X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AA11) PRG1_PRU1_GPO14.PR1_MII1_TXD3 */
AM64X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (U10) PRG1_PRU1_GPO13.PR1_MII1_TXD2 */
AM64X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (V10) PRG1_PRU1_GPO12.PR1_MII1_TXD1 */
AM64X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AA10) PRG1_PRU1_GPO11.PR1_MII1_TXD0 */
AM64X_IOPAD(0x0118, PIN_INPUT, 1) /* (W12) PRG1_PRU1_GPO4.PR1_MII1_RXDV */
AM64X_IOPAD(0x0120, PIN_INPUT, 1) /* (U11) PRG1_PRU1_GPO6.PR1_MII_MR1_CLK */
AM64X_IOPAD(0x0114, PIN_INPUT, 1) /* (Y12) PRG1_PRU1_GPO3.PR1_MII1_RXD3 */
AM64X_IOPAD(0x0110, PIN_INPUT, 1) /* (AA12) PRG1_PRU1_GPO2.PR1_MII1_RXD2 */
AM64X_IOPAD(0x011c, PIN_INPUT, 1) /* (AA13) PRG1_PRU1_GPO5.PR1_MII1_RXER */
AM64X_IOPAD(0x010c, PIN_INPUT, 1) /* (V11) PRG1_PRU1_GPO1.PR1_MII1_RXD1 */
AM64X_IOPAD(0x0108, PIN_INPUT, 1) /* (W11) PRG1_PRU1_GPO0.PR1_MII1_RXD0 */
/*AM64X_IOPAD(0x0130, PIN_INPUT, 1)*/ /* (W14) PRG1_PRU1_GPO10.PR1_MII1_CRS */
/*AM64X_IOPAD(0x012c, PIN_INPUT, 1)*/ /* (V14) PRG1_PRU1_GPO09.PR1_MII1_COL */
>;
};
main_usb0_pins_default: main-usb0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
main_mcan0_pins_default: main-mcan0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
>;
};
main_mcan1_pins_default: main-mcan1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
>;
};
led_light_pins_default: led_light-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x00bc, PIN_OUTPUT, 7) /* (U8) PRG1_PRU0_GPO1.GPIO0_46 */
AM64X_IOPAD(0x00c4, PIN_OUTPUT, 7) /* (V8) PRG1_PRU0_GPO3.GPIO0_48 */
AM64X_IOPAD(0x00e8, PIN_OUTPUT, 7) /* (U9) PRG1_PRU0_GPO12.GPIO0_57 */
AM64X_IOPAD(0x00f8, PIN_OUTPUT, 7) /* (V9) PRG1_PRU0_GPO16.GPIO0_61 */
>;
};
at88sc_pins_default: at88sc_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x00b0, PIN_OUTPUT, 7) /* (P19) GPMC0_CSn2.GPIO0_43 */
AM64X_IOPAD(0x00b4, PIN_OUTPUT, 7) /* (R21) GPMC0_CSn3.GPIO0_44 */
>;
};
display_74hc595pw_pins_default: display_74hc595pw_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x007c, PIN_OUTPUT, 7) /* (R17) GPMC0_CLK.GPIO0_31 */
AM64X_IOPAD(0x008c, PIN_INPUT, 7) /* (T21) GPMC0_WEn.GPIO0_34 */
AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) /* (P17) GPMC0_BE0n_CLE.GPIO0_35 */
AM64X_IOPAD(0x0094, PIN_INPUT, 7) /* (T19) GPMC0_BE1n.GPIO0_36 */
AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
AM64X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (Y18) GPMC0_WAIT1.GPIO0_38 */
AM64X_IOPAD(0x00a8, PIN_INPUT, 7) /* (R19) GPMC0_CSn0.GPIO0_41 */
AM64X_IOPAD(0x00ac, PIN_INPUT, 7) /* (R20) GPMC0_CSn1.GPIO0_42 */
>;
};
di_do_pins_default: di_do_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0208, PIN_INPUT, 7) /* (D12) SPI0_CS0.GPIO1_42 */
AM64X_IOPAD(0x0210, PIN_INPUT, 7) /* (D13) SPI0_CLK.GPIO1_44 */
AM64X_IOPAD(0x0214, PIN_INPUT, 7) /* (A13) SPI0_D0.GPIO1_45 */
AM64X_IOPAD(0x0218, PIN_INPUT, 7) /* (A14) SPI0_D1.GPIO1_46 */
>;
};
main_spi1_pins_default: main_spi1_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
AM64X_IOPAD(0x021c, PIN_INPUT, 0) /* (B14) SPI1_CS0 */
AM64X_IOPAD(0x0228, PIN_INPUT, 0) /* (B15) SPI1_D0 */
AM64X_IOPAD(0x022c, PIN_INPUT, 0) /* (A15) SPI1_D1 */
>;
};
power_cut_pins_default: power_cut_pins_default {
pinctrl-single,pins = <
AM64X_IOPAD(0x00fc, PIN_INPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
>;
};
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
/* main_uart1 is reserved for firmware usage */
&main_uart1 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
status = "okay";
linux,rs485-enabled-at-boot-time;
/*rs485-rts-active-low; */
rs485-rts-delay = <10 10>;
rts-gpios = <&main_gpio1 17 GPIO_ACTIVE_HIGH>; /* 8250_omap.c */
};
&main_uart2 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart2_pins_default>;
status = "okay";
linux,rs485-enabled-at-boot-time;
/*rs485-rts-active-low;*/
rs485-rts-delay = <10 10>;
rts-gpios = <&main_gpio1 18 GPIO_ACTIVE_HIGH>;
};
&main_uart3 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart3_pins_default>;
status = "okay";
linux,rs485-enabled-at-boot-time;
/*rs485-rts-active-low;*/
rs485-rts-delay = <10 10>;
rts-gpios = <&main_gpio1 19 GPIO_ACTIVE_HIGH>;
};
&main_uart4 {
status = "disabled";
};
&main_uart5 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart5_pins_default>;
status = "okay";
};
&main_uart6 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart6_pins_default>;
status = "okay";
};
&mcu_uart0 {
status = "disabled";
};
&mcu_uart1 {
status = "disabled";
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
};
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <100000>;
ds1337: rtc@68 {
compatible = "ti,ds1337";
reg = <0x68>;
};
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
status = "reserved";
};
&mcu_i2c0 {
status = "disabled";
};
&mcu_i2c1 {
status = "disabled";
};
&mcu_spi0 {
status = "disabled";
};
&mcu_spi1 {
status = "disabled";
};
&main_spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi1_pins_default>;
spidev@0 {
pinctrl-names = "default";
/*pinctrl-0 = <&power_cut_pins_default>;*/
spi-max-frequency = <24000000>;
reg = <0>;
compatible = "ct,mr25h10";
power_cut_irq = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
};
};
&sdhci0 {
/* emmc */
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
disable-wp;
};
&sdhci1 {
/* SD/MMC */
vmmc-supply = <&vdd_mmc1>;
pinctrl-names = "default";
bus-width = <4>;
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
no-1-8-v;
};
&usbss0 {
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins_default
&cpsw_rmii1_pins_default>;
cpts@3d000 {
ti,pps = <7 1>;
};
};
&cpsw_port1 {
phy-mode = "rmii";
phy-handle = <&cpsw3g_phy0>;
rmii-clock-ext; /*added for rmii */
};
&cpsw_port2 {
status = "disabled";
};
&cpsw3g_mdio {
cpsw3g_phy0: ethernet-phy@0 {
reg = <2>;
tx-internal-delay-ps = <250>;
rx-internal-delay-ps = <2000>;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
tx-internal-delay-ps = <250>;
rx-internal-delay-ps = <2000>;
};
};
#define TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val)
×ync_router {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpts_pps>;
/* Example of the timesync routing */
mcu_cpts_pps: mcu-cpts-pps {
pinctrl-single,pins = <
/* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */
TS_OFFSET(37, 22)
/* pps [cpts genf1] in22 -> out25 [SYNC1_OUT pin] */
TS_OFFSET(25, 22)
>;
};
};
&mailbox0_cluster2 {
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster3 {
status = "disabled";
};
&mailbox0_cluster4 {
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
ti,mbox-rx = <2 0 2>;
ti,mbox-tx = <3 0 2>;
};
};
&mailbox0_cluster5 {
status = "disabled";
};
&mailbox0_cluster6 {
mbox_m4_0: mbox-m4-0 {
ti,mbox-rx = <0 0 2>;
ti,mbox-tx = <1 0 2>;
};
};
&mailbox0_cluster7 {
status = "disabled";
};
&serdes_ln_ctrl {
idle-states = <AM64_SERDES0_LANE0_PCIE0>;
status = "disabled";
};
&serdes0 {
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_PCIE>;
resets = <&serdes_wiz0 1>;
};
};
&pcie0_rc {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
status = "disabled";
};
&pcie0_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <1>;
status = "disabled";
};
&tscadc0 {
/* ADC is reserved for R5 usage */
status = "disabled";
};
&main_mcan0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan0_pins_default>;
phys = <&transceiver1>;
};
&main_mcan1 {
pinctrl-names = "default";
pinctrl-0 = <&main_mcan1_pins_default>;
phys = <&transceiver2>;
};
&icssg0_mdio {
pinctrl-names = "default";
pinctrl-0 = <&icssg0_mdio_pins_default>;
icssg0_phy0: ethernet-phy@2 {
reg = <0x2>;
tx-internal-delay-ps = <250>;
rx-internal-delay-ps = <2000>;
};
icssg0_phy1: ethernet-phy@3 {
reg = <0x3>;
tx-internal-delay-ps = <250>;
rx-internal-delay-ps = <2000>;
};
};
RS485方向控制引脚未使用UART rts引脚，而是使用其他引脚。
测试RS485通讯，读写切换时，使用示波器测量RS485方向引脚，发现其一直未高电平。读写数据错误。
请问目前的驱动RS485方向引脚只能为UART rts引脚吗？
SDK版本：08.06.00.42
