处理器论坛 - 最近的话题

MSPM0G3507: MSP-GANG Programmer

x w — Mon, 12 Oct 2026 05:35:14 GMT

Part Number: MSPM0G3507

项目用到MSPM0G3507单片机，想要读取下Flash代码段是否与烧写的HEX文件一致。使用MSP-GANG Programmer进行读取，若是从地址0x00000开始，一下子读取128k，则发现读取到的代码后面64k部分是乱的。如果分别从地址0x00000、0x10000开始分两次读取，每次读取64k，读取到的代码与烧写文件是一致的。这种情况是不是因为MSP-GANG Programmer对代码读取缓冲做的不够导致的，有点像缓冲溢出的问题？如果MSP-GANG Programmer缓冲不够的话，那么最大一次性能准确地读取多少字节代码？

MSPM0L1105: MSPM0L1105 BSL的三个疑问。

X HS — Mon, 12 Oct 2026 04:06:36 GMT

Part Number: MSPM0L1105
Other Parts Discussed in Thread: MSPM0L1306

Hi,

我们正在使用MSPM0L1105做BSL，然后我们查看了文档(User's Guide MSPM0 引导加载程序 )，结合我们项目的需求，我们有三个疑问需要帮忙。

1、ROM BSL可以做到BSL烧录时保留部分地址数据不更改吗？因为项目要求部分数据是不可更改的。

2、MSPM0L1105可以做完全基于闪存的BSL吗？我们有想用闪存BSL的想法，但是文档里描述是这样的：

也就是MSPM9Lx系列没有闪存BSL支持，但是例程“bsl_uart_flash_interface_LP_MSPM0L1306_nortos_ticlang”中使用了闪存的，所以我们这边迷茫了，我们这个型号可以用闪存BSL吗？

3、使用闪存BSL的话，我该怎么通过软件方式进入闪存BSL？

TMS570LC4357: 是否支持1Gbit SDR SDRAM

Hui Cao22 — Mon, 12 Oct 2026 03:47:24 GMT

Part Number: TMS570LC4357

是否可以通过EMIF支持访问1Gbit SDR SDRAM？

TI是否有做过1Gbit的匹配测试？

MSPM0G3507: 请帮忙发一下tida010265的MSPM0的代码，谢谢

guotao liu — Sat, 10 Oct 2026 08:48:13 GMT

Part Number: MSPM0G3507

Tida010265 里面有 daughter board ，使用mspm0 ,但是这个代码我找不到。

还有我想申请一块Tida010250的板子，要怎么申请

TMS320F28377D: TI的工程师你好，我想咨询一下28377D的高速SPI最快速率能达到多少？

xiongyy — Fri, 09 Oct 2026 08:04:32 GMT

Part Number: TMS320F28377D

如图所示，我看手册上面写只能达到40MHz，但是我记得中文手册说能达到50MHz吗？
然后我还想咨询一下配置高速SPI有没有什么需要注意的地方？是只有图上的GPIO口能配置为高速SPI吗？感谢

TMS320F28388S: Implementation of EnDat 2.2 Using F28388S

zhan soong — Fri, 09 Oct 2026 06:24:34 GMT

Part Number: TMS320F28388S
Other Parts Discussed in Thread: C2000WARE

I am developing a motor control application using the TMS320F28388S microcontroller. I need to implement an EnDat 2.2 absolute encoder master interface.

I have been trying to use the PM_endat22_lib.lib library that is typically provided for the F2837x series. However, I encountered a fundamental compatibility issue:

My project uses the EABI output format (--abi=eabi), as required for F28388S.

The available PM_endat22_lib.lib is compiled in TI-COFF format.

The linker reports: warning #10373-D: library contains TI-COFF object files which are incompatible with the ELF output file.

As a result, all EnDat22 functions (PM_endat22_setupPeriph, PM_endat22_setFreq, PM_endat22_setupCommand, PM_endat22_startOperation, PM_endat22_receiveData, CheckCRC, etc.) remain unresolved.

I have searched the C2000Ware MotorControl SDK 6.00.00.00 and found only documentation (e.g., TIDUDE3A, SPRU135) and reference designs, but no EABI-compatible library or source code for the EnDat22 protocol stack. I also checked the TI E2E forums and found related discussions, but no definitive solution for F28388S.

My request:

Is there an EABI-compatible version of the PM_endat22_lib.lib library available for the F28388S?

If not, can TI provide the source code of the EnDat22 library so I can recompile it for EABI?

If neither is available, is there any migration guide or recommended approach to port the EnDat22 protocol stack from F2837x to F28388S?

Are there any alternative solutions (e.g., a different library, a reference design with source, or a third-party protocol stack) that TI recommends for EnDat 2.2 on F28388S?

I understand that the F28388S has a CLB (Configurable Logic Block) that can be used to implement custom serial interfaces. I am willing to implement the protocol manually if necessary, but I would greatly appreciate any official library or source code to accelerate development and ensure reliability.

Our project was successfully implemented on the F28379S, but now due to CAN FD requirements we need to switch to the F28388S. However, because I previously developed using the EnDat22 library for the F28379D, and I personally do not know how to configure the CLB for EnDat22, I can only use the lib library. For this reason, I used the same pins as the F28379D example.

DRA821U-Q1: DRA821U-Q1 的PCIE，能否从serdes lane2开始绑定

?? ? — Wed, 23 Sep 2026 11:58:47 GMT

Part Number: DRA821U-Q1

目前硬件设计

SERDES0 RX0/TX0 |--> to sgmii
SERDES0 RX1/TX1 |--> 浮空
SERDES0 RX2/TX2 |--> to PCIE 1lane
SERDES0 RX3/TX3 |--> to sgmii
设备树启用PCIE并绑定Lane2，linux 内核出现panic
[0.119956] rtc-rx8581 1-0051: setting system clock to 2026-09-23T16:12:04 UTC (1790179924)
[0.120030] omap_i2c 2010000.i2c: bus 1 rev0.12 at 400 kHz
[0.120195] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 137 domain created
[0.120289] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 131 domain created
[0.120380] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 213 domain created
[0.120547] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 209 created
[0.123282] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
[0.123288] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[0.123291] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[0.126753] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211
[0.126761] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[0.126763] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[0.127232] printk: console [ttyS2] disabled
[0.127268] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 251, base_baud = 3000000) is a 8250
[0.127411] printk: console [ttyS2] printing thread started
[0.127424] printk: console [ttyS2] enabled
[0.128242] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 252, base_baud = 3000000) is a 8250
[0.129724] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[0.163822] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[0.170262] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver Microchip KSZ9131 Gigabit PHY
[0.170267] davinci_mdio c000f00.mdio: phy[2]: device c000f00.mdio:02, driver Microchip KSZ9131 Gigabit PHY
[0.170270] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F Gigabit Ethernet
[0.170293] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
[0.170392] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[0.170406] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
[0.170408] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[0.170760] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
[0.173063] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
[0.275017] mmc0: CQHCI version 5.10
[0.277843] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fc8900
[0.278176] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fc8900
[0.279196] j721e-pcie-host 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[0.279209] j721e-pcie-host 2910000.pcie: Parsing ranges property...
[0.279221] j721e-pcie-host 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[0.279235] j721e-pcie-host 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[0.279241] j721e-pcie-host 2910000.pcie: Parsing dma-ranges property...
[0.279247] j721e-pcie-host 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[0.282657] SError Interrupt on CPU0, code 0x00000000bf000000 -- SError
[0.282663] CPU: 0 PID: 50 Comm: kworker/u4:2 Not tainted 6.1.83-rt28-344047-g8e9966230a20-dirty #74
[0.282667] Hardware name: Texas Instruments J7200 EVM (DT)
[0.282670] Workqueue: events_unbound deferred_probe_work_func
[0.282688] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[0.282692] pc : cdns_pcie_detect_quiet_min_delay_set+0x18/0x48
[0.282700] lr : cdns_pcie_host_setup+0x628/0xa30
[0.282703] sp : ffff800009573a50
[0.282705] x29: ffff800009573a50 x28: 0000000000000000 x27: ffff000801ddb980
[0.282710] x26: 0000000000000000 x25: 000000000000ffff x24: ffff00087f814a68
[0.282714] x23: 0000000000000000 x22: ffff0008003bbbc0 x21: ffff000800127010
[0.282718] x20: ffff800008bc4000 x19: ffff000801c7b3c0 x18: 0000000000000000
[0.282722] x17: 0000000070d08223 x16: 00000000d8c4caca x15: 0000000000000001
[0.282726] x14: ffff800008bc4000 x13: 000000000007939d x12: 0101010101010101
[0.282730] x11: ffff800009101000 x10: 0000000018000000 x9 : 0000000000000000
[0.282733] x8 : 006800000000070f x7 : 0040000000000001 x6 : ffff800008ebc590
[0.282737] x5 : ffff00087fffe240 x4 : ffff0008001272d0 x3 : ffff000800c95580
[0.282741] x2 : 0000000000100054 x1 : 0000000000000000 x0 : ffff000801c7b3c0
[0.282746] Kernel panic - not syncing: Asynchronous SError Interrupt
[0.282748] CPU: 0 PID: 50 Comm: kworker/u4:2 Not tainted 6.1.83-rt28-344047-g8e9966230a20-dirty #74

是否PCIE只能从Lane0开始？

TDA4VL-Q1: TDA4VL-Q1 TDA4VL78N5AALZRQ1 TDA4VL21HGAALZRQ1

bxh hdh — Fri, 18 Sep 2026 16:07:04 GMT

Part Number: TDA4VL-Q1

I want to check TDA4VL78N5AALZRQ1 ,then web link to TDA4VL-Q1

but the only option is TDA4VL21HGAALZRQ1

may I know is it same parts?

TMS320F28388D: F28388D上电时序

ha yang — Fri, 18 Sep 2026 01:54:03 GMT

Part Number: TMS320F28388D

F28388D对上电时序有要求吗？如何控制F28388D的上电时序？数据手册和官方demo以及论坛上的回复上的表现不一致。

TAS3251EVM: PPC3中添加该型号进行开发

Wei Xu — Tue, 15 Sep 2026 06:19:27 GMT

Part Number: TAS3251EVM
Other Parts Discussed in Thread: TAS5822M, TAS3251

申请TAS5822M和TAS3251两款芯片在PPC3中开发

J722SXH01EVM: Can AM67A ISP support auto focus?

xingxing gu — Tue, 15 Sep 2026 03:29:45 GMT

Part Number: J722SXH01EVM
Other Parts Discussed in Thread: AM67A

We want to connect two auto focus camera modules to AM67A platform. Any reference ISP setting to support auto focus camera modules?

Thanks

Xingxing

AM5728: AM5728实现IEEE1588协议的一些疑问

chen geng — Fri, 11 Sep 2026 03:03:21 GMT

Part Number: AM5728
Other Parts Discussed in Thread: 66AK2G12, SYSBIOS, AM5729

看了AM5728的手册，EAMC支持IEEE1588协议，但是在TRM上第24.11.4.10章节里，关于CPTS的介绍感觉比较浅，比如下面两个截图，看样子时间戳的时间应该来至定时器TIMER13--16中的一个，但是怎么配置相关的定时器，以及截图二中portimerpwm，是什么样的接口，都没有进一步说明。然后协议层面，时间戳值是如何从选择的定时器加载到数据包里面的，似乎也没有相关介绍。最后，我在网上搜索了下，好像说是AM5728对IEEE1588的支持，只是支持AVB音视频桥接方面，要真正完整支持IEEE1588，是要在PRU-ICSS端去实现的，不知道是不是这样。

AM2754-Q1: AM275x AASRC GROUP Mode Output Channel Phase Rotation — Issue Report

Mingyang Hu — Thu, 10 Sep 2026 07:30:09 GMT

Part Number: AM2754-Q1

Chip / core: AM275x, issue observed and instrumented on the C7x DSP core (C75SS0_0), FreeRTOS.

SDK: freertos_sdk_am275x_12_01_00_28

Hi,

We are seeing the channel interleave phase of an AASRC GROUP output drift over time, and would like to know whether this is expected behaviour or a configuration mistake on our side.

AASRC is configured as a single GROUP channel with 12 channels. The input clock zone is slaved to an external A2B frame sync (McASP2_AFSR); the output clock zone is derived from a local 24.576 MHz reference clock. The two domains are therefore asynchronous, and we measured them to be 7.2 ppm apart — absorbing that offset is exactly why we use AASRC here.

To isolate the problem we inject a mono test tone on A2B media channel 0 and keep the other 11 channels digitally silent, then log which interleave lane carries the signal on each side of AASRC. At the AASRC input buffer the tone stays on lane 0 for the entire run. At the AASRC output buffer it migrates: 0 -> 11 -> 10 -> 9 -> ... -> 1 -> 0, wrapping through all 12 lanes.

The direction is always the same (towards lower lane index, consistent with the output domain being the faster one), but the step size is not constant — most events move the phase by 1 lane, while some events move it by more than one lane at once. Over a 27.7 minute run the phase wrapped through all 12 lanes, at irregular intervals ranging from 50 s to 355 s.

What makes this hard to handle is that nothing in the driver reports it. During that same run the AASRC error callback fired 0 times, the application dropped 0 input blocks, the 4-deep transaction ring never starved (3-4 transactions in flight throughout), and we verified by instrumentation that our transaction-to-buffer mapping never diverged (0 mismatches). The audio itself is clean — no glitches, no dropouts — only the channel positions shift.

Our questions:

In GROUP mode with asynchronous input/output clock zones, is the 12-channel interleave phase of the output DMA stream guaranteed to remain stable indefinitely? If not, is this a known limitation of GROUP mode?
A 12-channel GROUP maps onto 6 stereo SRC pairs sharing one DMA stream. Are the rate-compensation decisions of those 6 pairs shared, or does each pair decide independently? If independent, a divergence of N samples between pairs would rotate the interleave by N positions, which would match both the single-lane and the multi-lane steps we observe. Is that the mechanism?
Is there a register or API to read the current output FIFO level per stereo pair, or the interleave phase of the GROUP? We need a way to detect and re-align the phase that does not depend on audio content — our current probe only works because we can inject a single-channel test tone.
For this use case (resampling 12 A2B media channels from an external clock-slave domain into the local domain), is a single GROUP(12) the recommended configuration, or should we use 6 independent STEREO channels with separate DMA streams so that the pairs cannot drift relative to each other?

Full configuration, reproduction steps, detection method and raw logs are in the sections below.

Thanks,

AASRC_Channel_Phase_Rotation_Report.txt

RM57L843: RM57L843 power on/off sequence

Soni Rao — Wed, 09 Sep 2026 11:30:12 GMT

Part Number: RM57L843
Other Parts Discussed in Thread: TPS65381A-Q1, , TPS62130A-Q1

Hi Ti

My current design use a PS65381A-Q1 PMIC and a TPS62130A-Q1, providing 5V/3.3V and 1.2V respectively. The 3.3V of RM57L843 comes from the TPS65381A-Q1 PMIC, and the 1.2V comes from the TPS62130A-Q1.

In terms of timing, the 1.2V will be powered off 5ms or more later than the 3.3V. Is there any risk with this? Although the RM57 specification states that there is no specific timing for 3.3V/1.2V.

Thanks

TPS54424: 请帮忙提供COD信息

RayVal S — Wed, 09 Sep 2026 01:34:48 GMT

Part Number: TPS54424

TPS54424RNVR
TPS3850H33DRCR
ADS7057IRUGR
SN74HCS264PWR
这四个型号请帮忙确认COD信息，谢谢

AM3352: 升级uboot 从sdk 的2017 到2026，启动同一个fitimage 新的uboot 2026 出现Starting kernel ... 问题

shaohua xiong — Tue, 08 Sep 2026 09:25:50 GMT

Part Number: AM3352

我现在是将板子的uboot 从sdk 的2017 版本，升级到2026 版本，原本旧的uboot 是可以正常启动fitimage 的，且bootargs 配置为 'earlycon=ns16550a,mmio32,0x44e09000 console=ttyO0,115200n8 loglevel=8 root=/dev/ram0 rw'，可以正常看到kernel 启动log, 并正常启动，现在换成uboot 2026 版本后，bootargs 没变，还是 'earlycon=ns16550a,mmio32,0x44e09000 console=ttyO0,115200n8 loglevel=8 root=/dev/ram0 rw'，

=> bootm 0x88000000
## Loading kernel (any) from FIT Image at 88000000 ...
Using 'conf-1' configuration
Verifying Hash Integrity ... OK
Trying 'kernel-1' kernel subimage
Description: Linux Kernel
Created: 2011-04-05 23:00:00 UTC
Type: Kernel Image
Compression: uncompressed
Data Start: 0x880113f0
Data Size: 5902848 Bytes = 5.6 MiB
Architecture: ARM
OS: Linux
Load Address: 0x80300000
Entry Point: 0x80300000
Hash algo: sha256
Hash value: dbc1b7373ca439fe70850915362be5991d21580c810c08f430ae67eaa0a65bea
Verifying Hash Integrity ... sha256+ OK
## Loading ramdisk (any) from FIT Image at 88000000 ...
Using 'conf-1' configuration
Verifying Hash Integrity ... OK
Trying 'ramdisk-1' ramdisk subimage
Description: Ramdisk Image
Created: 2011-04-05 23:00:00 UTC
Type: RAMDisk Image
Compression: uncompressed
Data Start: 0x885b26e8
Data Size: 2108265 Bytes = 2 MiB
Architecture: ARM
OS: Linux
Load Address: 0x83000000
Entry Point: 0x83000000
Hash algo: sha256
Hash value: f2adcb28abc8db029d08a70b44922d17181ef12d965b85a1aaa959d4058625e6
Verifying Hash Integrity ... sha256+ OK
Loading ramdisk from 0x885b26e8 to 0x83000000
## Loading fdt (any) from FIT Image at 88000000 ...
Using 'conf-1' configuration
Verifying Hash Integrity ... OK
Trying 'fdt-1' fdt subimage
Description: Flattened Device Tree blob
Created: 2011-04-05 23:00:00 UTC
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x880000d0
Data Size: 70204 Bytes = 68.6 KiB
Architecture: ARM
Load Address: 0x80200000
Hash algo: sha256
Hash value: 922e664890d89e3e29510ceebcf806157170f2ac0492084f377b4ae4c9d527ac
Verifying Hash Integrity ... sha256+ OK
Loading fdt from 0x880000d0 to 0x80200000
Booting using the fdt blob at 0x80200000
Working FDT set to 80200000
Loading Kernel Image to 80300000
Using Device Tree in place at 80200000, end 8021423b
Working FDT set to 80200000

Starting kernel ...

CCCCCCCC

上面出现Starting kernel ... 后大概等了30s 后出现CCCC, 板子重启，由于kernel 在旧的uboot 可以正常启动，且bootargs 起了作用，我现在怀疑是新的uboot 导致，为什么新的uboot 下bootargs 没起作用，内核也没看到输出，不知道什么原因，大家有遇到过吗，能帮忙一下！

TMS320C6747: TMS320C6747被干扰

ZXL ZXL — Fri, 04 Sep 2026 03:27:47 GMT

Part Number: TMS320C6747

TMS320C6747在1.4G功率辐射下，芯片会死机。
1.辐射天线照射从芯片的引出的线缆、程序烧写口、铝合金结构的缝隙均会出现死机情况；
2.DSP使用有源晶振，在照射的情况下，测试电源纹波(1.2V和3.3v)，看不出来明显的影响，靠近芯片，晶振有微弱的偏移；
3.在1.4-1.5G使用单频点测试均会死机；
4.关闭辐射源的情况下，DSP会辐射出1.4G-1.6G频率，1.4G-1.5G最大辐射量增加（抬升）30dB，1.68G的辐射量最大增加量（抬升）50dB;
5.对晶振部位进行遮挡，会减轻干扰；
需要咨询一下，可以从哪些方面解决这个干扰问题

CCSTUDIO: CCS6 的Full lic 文件

cai mei — Thu, 03 Sep 2026 11:40:27 GMT

Part Number: CCSTUDIO

我使用XDS200仿真器，需要CCS6 的全功能license文件

OMAPL137-HT: DSP端代码格式选择eabi(ELF)和legacy COFF格式遇到的问题

chen geng — Thu, 03 Sep 2026 04:36:24 GMT

Part Number: OMAPL137-HT

CCS版本12.8，C6000CGT版本8.3.12，输出文件格式为eabi(ELF)，进调试模式后，代码全部正常，中断，主函数中的while循环点灯，都没问题；然后通过SPI_FLASH_WRITE.out烧写板载SPI FLASH，CCS中提示烧写完毕，校验也通过，板子断电然后上电，启动失败。然后改为7.4.8的CGT，仍然采用eabi(ELF)，同样调试没有问题，烧入SPI FLAHS启动失败；将7.4.8的CGT输出格式改为COFF格式，进调试模式，仅while循环中的点灯代码运行正常，所有中断均无响应；将COFF格式的out文件烧入SPI FLASH，板子重启后点灯程序能运行，中断无响应。上述情况，我该怎么处理呢

TMS320F28379D: cmd文件的RAM配置

xue yu — Wed, 02 Sep 2026 08:33:21 GMT

Part Number: TMS320F28379D

在例程cmd文件中查到这样的注释

/*
//###########################################################################
// FILE: flash_programming_cpu1_FLASH.cmd
// TITLE: Linker Command File For all F28X7x devices
//###########################################################################
// $TI Release: F2837xD Support Library v200 $
// $Release Date: Tue Jun 21 13:00:02 CDT 2016 $
// $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated -
// http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
// The header linker files are found in <base>\F2837xD_headers\cmd
// For BIOS applications add: F28X7x_Headers_BIOS.cmd
// For nonBIOS applications add: F28X7x_Headers_nonBIOS.cmd
========================================================= */

/* Define the memory block start/length for the F28X7x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections

Notes:
Memory blocks on F28M3Xx are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.

Contiguous SARAM memory blocks or flash sectors can be
be combined if required to create a larger memory block.
*/

在spru513aa文件的8.5.5.2.7 Using the Page Method内看到了另外一种做法，是支持ram段的重叠复用。请问这两种方法的使用界限是什么

TMS320F28035: TMS320F28035的晶振设计指南（晶振的增益裕量参数）

yangbo jiang — Wed, 02 Sep 2026 06:31:10 GMT

Part Number: TMS320F28035

TMS320F28035的晶振设计指南（晶振的增益裕量参数），

66AK2G12: boot启动问题

wood zhou — Wed, 02 Sep 2026 03:10:44 GMT

Part Number: 66AK2G12

根据这个文档 https://software-dl.ti.com/processor-sdk-linux/esd/docs/06_03_00_106/linux/Foundational_Components_U-Boot.html

66ak2g12 只支持sd卡、uart、net、和spi四种启动，但是板上直接启动是不是直接sd卡和spi两种，我现在没有sd卡，spi接的又是nand flash，是不是就没有办法直接板上启动了？

MSP430FR6972: MSP430FR6972运行一年后出现屏幕全新不停复位的现象。

x w — Tue, 01 Sep 2026 09:25:32 GMT

Part Number: MSP430FR6972

现场有100台水表，使用芯片MSP430FR6972，正常运行1年后，出现3台表，液晶一直全显示，然后熄屏，再全显，再熄灭屏幕。其中一台，进行断电上电后，恢复正常运行。另外一台没有断电，将RESET引脚短接GND，也没变化。低功耗模式采用的是LPM2，比较好奇的是，如果是程序跑飞导致的，将RESET引脚短接GND应该能够恢复运行才对，但目前测试，只有通过断电上电的复位方式，才能够恢复运行。在网络上搜索，怀疑是PMM锁死的现象。我对比了我们常规产品程序，只是把主频由4M提高到8M，其他的没有底层驱动的修改。由于设备断电上电后，频繁复位的现象无法复现，想请教下，遇到类似问题，该如何排查。

TDA4VE-Q1: TDA4 eFuse flashing solution Confirm

xie yiwei — Mon, 31 Aug 2026 02:45:25 GMT

Part Number: TDA4VE-Q1

Hello,TI Experts

For TDA4 eFuse flashing solution of mass production ,attach the 1.8V fuse voltage from the outside of the PCBA (external) over test point,whether is ok. could you help to supply your comments? thank you.

TDA4VE-Q1: TDA4 eFuse flashing solution Confirm

xie yiwei — Mon, 31 Aug 2026 02:41:22 GMT

Part Number: TDA4VE-Q1

Hello,TI Experts

For TDA4VE eFuse flashing solution of mass production ,attach the 1.8V fuse voltage from the outside of the PCBA (external) over test point,whether is ok. could you help to supply your comments? thank you