处理器论坛 - 最近的话题

TMS320F28377D: TI的工程师你好，我想咨询一下28377D的高速SPI最快速率能达到多少？

xiongyy — Fri, 09 Oct 2026 08:04:32 GMT

Part Number: TMS320F28377D

如图所示，我看手册上面写只能达到40MHz，但是我记得中文手册说能达到50MHz吗？
然后我还想咨询一下配置高速SPI有没有什么需要注意的地方？是只有图上的GPIO口能配置为高速SPI吗？感谢

RE: TMS320F28377D: TI的工程师你好，我想咨询一下28377D的高速SPI最快速率能达到多少？

xiongyy — Fri, 09 Oct 2026 09:07:03 GMT

还有一个问题，内部环回的话，信号输入输出引脚会有波形吗？因为我是想验证SPI模块的最大速率

RE: TMS320F28377D: TI的工程师你好，我想咨询一下28377D的高速SPI最快速率能达到多少？

FRANK1 — Fri, 09 Oct 2026 08:12:50 GMT

感谢您对TI产品的关注！
关于你的咨询，我们正在确认您的问题，感谢您的耐心等待。

RE: TMS320F28388S: Implementation of EnDat 2.2 Using F28388S

Vivian Gao — Fri, 09 Oct 2026 06:44:17 GMT

Thank you for your attention to TI products. We are verifying your issue, please wait for our reply.

TMS320F28388S: Implementation of EnDat 2.2 Using F28388S

zhan soong — Fri, 09 Oct 2026 06:24:34 GMT

Part Number: TMS320F28388S

I am developing a motor control application using the TMS320F28388S microcontroller. I need to implement an EnDat 2.2 absolute encoder master interface.

I have been trying to use the PM_endat22_lib.lib library that is typically provided for the F2837x series. However, I encountered a fundamental compatibility issue:

My project uses the EABI output format (--abi=eabi), as required for F28388S.

The available PM_endat22_lib.lib is compiled in TI-COFF format.

The linker reports: warning #10373-D: library contains TI-COFF object files which are incompatible with the ELF output file.

As a result, all EnDat22 functions (PM_endat22_setupPeriph, PM_endat22_setFreq, PM_endat22_setupCommand, PM_endat22_startOperation, PM_endat22_receiveData, CheckCRC, etc.) remain unresolved.

I have searched the C2000Ware MotorControl SDK 6.00.00.00 and found only documentation (e.g., TIDUDE3A, SPRU135) and reference designs, but no EABI-compatible library or source code for the EnDat22 protocol stack. I also checked the TI E2E forums and found related discussions, but no definitive solution for F28388S.

My request:

Is there an EABI-compatible version of the PM_endat22_lib.lib library available for the F28388S?

If not, can TI provide the source code of the EnDat22 library so I can recompile it for EABI?

If neither is available, is there any migration guide or recommended approach to port the EnDat22 protocol stack from F2837x to F28388S?

Are there any alternative solutions (e.g., a different library, a reference design with source, or a third-party protocol stack) that TI recommends for EnDat 2.2 on F28388S?

I understand that the F28388S has a CLB (Configurable Logic Block) that can be used to implement custom serial interfaces. I am willing to implement the protocol manually if necessary, but I would greatly appreciate any official library or source code to accelerate development and ensure reliability.

Our project was successfully implemented on the F28379S, but now due to CAN FD requirements we need to switch to the F28388S. However, because I previously developed using the EnDat22 library for the F28379D, and I personally do not know how to configure the CLB for EnDat22, I can only use the lib library. For this reason, I used the same pins as the F28379D example.

RE: DRA821U-Q1: DRA821U-Q1 的PCIE，能否从serdes lane2开始绑定

Takuma Fujiwara — Fri, 25 Sep 2026 15:53:59 GMT

DRA821U-Q1: DRA821U-Q1 的PCIE，能否从serdes lane2开始绑定

?? ? — Wed, 23 Sep 2026 11:58:47 GMT

Part Number: DRA821U-Q1

目前硬件设计

SERDES0 RX0/TX0 |--> to sgmii
SERDES0 RX1/TX1 |--> 浮空
SERDES0 RX2/TX2 |--> to PCIE 1lane
SERDES0 RX3/TX3 |--> to sgmii
设备树启用PCIE并绑定Lane2，linux 内核出现panic
[0.119956] rtc-rx8581 1-0051: setting system clock to 2026-09-23T16:12:04 UTC (1790179924)
[0.120030] omap_i2c 2010000.i2c: bus 1 rev0.12 at 400 kHz
[0.120195] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 137 domain created
[0.120289] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 131 domain created
[0.120380] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 213 domain created
[0.120547] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 209 created
[0.123282] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
[0.123288] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[0.123291] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[0.126753] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211
[0.126761] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[0.126763] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[0.127232] printk: console [ttyS2] disabled
[0.127268] 2800000.serial: ttyS2 at MMIO 0x2800000 (irq = 251, base_baud = 3000000) is a 8250
[0.127411] printk: console [ttyS2] printing thread started
[0.127424] printk: console [ttyS2] enabled
[0.128242] 2810000.serial: ttyS3 at MMIO 0x2810000 (irq = 252, base_baud = 3000000) is a 8250
[0.129724] davinci_mdio c000f00.mdio: Configuring MDIO in manual mode
[0.163822] davinci_mdio c000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[0.170262] davinci_mdio c000f00.mdio: phy[1]: device c000f00.mdio:01, driver Microchip KSZ9131 Gigabit PHY
[0.170267] davinci_mdio c000f00.mdio: phy[2]: device c000f00.mdio:02, driver Microchip KSZ9131 Gigabit PHY
[0.170270] davinci_mdio c000f00.mdio: phy[3]: device c000f00.mdio:03, driver RTL8211F Gigabit Ethernet
[0.170293] am65-cpsw-nuss c000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 5 quirks:00000000
[0.170392] am65-cpsw-nuss c000000.ethernet: Use random MAC address
[0.170406] am65-cpsw-nuss c000000.ethernet: initialized cpsw ale version 1.4
[0.170408] am65-cpsw-nuss c000000.ethernet: ALE Table size 512
[0.170760] am65-cpsw-nuss c000000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
[0.173063] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
[0.275017] mmc0: CQHCI version 5.10
[0.277843] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fc8900
[0.278176] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fc8900
[0.279196] j721e-pcie-host 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[0.279209] j721e-pcie-host 2910000.pcie: Parsing ranges property...
[0.279221] j721e-pcie-host 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[0.279235] j721e-pcie-host 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[0.279241] j721e-pcie-host 2910000.pcie: Parsing dma-ranges property...
[0.279247] j721e-pcie-host 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[0.282657] SError Interrupt on CPU0, code 0x00000000bf000000 -- SError
[0.282663] CPU: 0 PID: 50 Comm: kworker/u4:2 Not tainted 6.1.83-rt28-344047-g8e9966230a20-dirty #74
[0.282667] Hardware name: Texas Instruments J7200 EVM (DT)
[0.282670] Workqueue: events_unbound deferred_probe_work_func
[0.282688] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[0.282692] pc : cdns_pcie_detect_quiet_min_delay_set+0x18/0x48
[0.282700] lr : cdns_pcie_host_setup+0x628/0xa30
[0.282703] sp : ffff800009573a50
[0.282705] x29: ffff800009573a50 x28: 0000000000000000 x27: ffff000801ddb980
[0.282710] x26: 0000000000000000 x25: 000000000000ffff x24: ffff00087f814a68
[0.282714] x23: 0000000000000000 x22: ffff0008003bbbc0 x21: ffff000800127010
[0.282718] x20: ffff800008bc4000 x19: ffff000801c7b3c0 x18: 0000000000000000
[0.282722] x17: 0000000070d08223 x16: 00000000d8c4caca x15: 0000000000000001
[0.282726] x14: ffff800008bc4000 x13: 000000000007939d x12: 0101010101010101
[0.282730] x11: ffff800009101000 x10: 0000000018000000 x9 : 0000000000000000
[0.282733] x8 : 006800000000070f x7 : 0040000000000001 x6 : ffff800008ebc590
[0.282737] x5 : ffff00087fffe240 x4 : ffff0008001272d0 x3 : ffff000800c95580
[0.282741] x2 : 0000000000100054 x1 : 0000000000000000 x0 : ffff000801c7b3c0
[0.282746] Kernel panic - not syncing: Asynchronous SError Interrupt
[0.282748] CPU: 0 PID: 50 Comm: kworker/u4:2 Not tainted 6.1.83-rt28-344047-g8e9966230a20-dirty #74

是否PCIE只能从Lane0开始？

AM5728: AM5728实现IEEE1588协议的一些疑问

chen geng — Fri, 11 Sep 2026 03:03:21 GMT

Part Number: AM5728

看了AM5728的手册，EAMC支持IEEE1588协议，但是在TRM上第24.11.4.10章节里，关于CPTS的介绍感觉比较浅，比如下面两个截图，看样子时间戳的时间应该来至定时器TIMER13--16中的一个，但是怎么配置相关的定时器，以及截图二中portimerpwm，是什么样的接口，都没有进一步说明。然后协议层面，时间戳值是如何从选择的定时器加载到数据包里面的，似乎也没有相关介绍。最后，我在网上搜索了下，好像说是AM5728对IEEE1588的支持，只是支持AVB音视频桥接方面，要真正完整支持IEEE1588，是要在PRU-ICSS端去实现的，不知道是不是这样。

RE: AM5728: AM5728实现IEEE1588协议的一些疑问

chen geng — Fri, 25 Sep 2026 01:07:49 GMT

非常感谢，我好好看看这些文档资料

RE: AM5728: AM5728实现IEEE1588协议的一些疑问

Misael Lopez Cruz — Fri, 25 Sep 2026 00:40:22 GMT

此 SDK 包含 Josue 在其之前的帖子中指出的 GMACSW 驱动程序： https://www.ti.com/tool/download/PROCESSOR-SDK-VISION/03.08.00.00 。

我强烈建议您使用 NSP 驱动程序作为参考。

RE: AM5728: AM5728实现IEEE1588协议的一些疑问

Josue Zamitiz-Ayala — Thu, 24 Sep 2026 17:05:47 GMT

请查阅汽车行业相关版本，并参考 CPTS 文档以获取更详细的指导。本论坛不涉及从零开始编写裸机驱动程序。

https://www.ti.com/tool/PROCESSOR-SDK-TDAX#downloads

查找 /packages/ti/nsp/drv/gmacsw/cpts.c

最好的，

约书亚

RE: AM5728: AM5728实现IEEE1588协议的一些疑问

chen geng — Thu, 24 Sep 2026 01:00:48 GMT

是的，手动令TS_PUSH=1，也不能触发时间戳事件。如果这是因为没有启用CPTS导致的话，那么除了当前已有的初始化代码和令CPTSRegs.CONTROL.bit.CPTS_EN = 1，还需要有其它什么必要的步骤才能真正的启用CPTS？，从TRM上，暂时没有看到有其它寄存器也在控制CPTS的使能或者禁止状态。对于CPTS RCLK，我的代码如下：

目前唯一能让代码进入PTP时间戳事件中断的，就只有如下测试代码：

CPTSRegs.CONTROL.bit.INT_TEST = 1;//开启中断测试
CPTSRegs.INT_STAT_RAW.bit.TS = 1;//手动强制进入中断

RE: DRA821U-Q1: DRA821U-Q1 的PCIE，能否从serdes lane2开始绑定

Eirwen — Wed, 23 Sep 2026 22:59:43 GMT

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: AM5728: AM5728实现IEEE1588协议的一些疑问

Misael Lopez Cruz — Wed, 23 Sep 2026 18:04:27 GMT

CPTS 时间戳事件存储在硬件 FIFO 中，需要从中取出。时间戳事件有多种类型（发送和接收数据包、软件推送、硬件推送），但它们都存储在同一个 FIFO 中。在发送和接收数据包中，当数据包的 EtherType 与您设置的 LTYPE1 值（RX 或 TX）匹配时，硬件将生成一个时间戳事件。

你说它不起作用，是指 FIFO 中没有任何事件吗？

CPTS 支持软件推送事件（通过 TS_PUSH 寄存器），当 TS_PUSH 位写入 1 时，CPTS 将生成一个时间戳事件并将其存储到 CPTS FIFO 中。如果仍然无效，则可能是您未启用 CPTS。

CPTS RCLK 可以来自不同的信号源，通常会有一个多路复用器来选择具体信号源。根据 AM572x 技术参考手册：

> CM_GMAC_GMAC_CLKCTRL[ 27:25 ] CLKSEL_RFT - 选择 CPTS_RFT_CLK 的源

关于您原帖中提到的定时器问题，它们并非 CPTS 时间戳的来源。CPTS 可以捕获通过硬件推送输入传递给它的硬件事件的时间戳。一般来说，它可以是任何硬件事件（在较新的 TI 处理器中就是如此），但在 AM572x 中，它仅限于定时器的 PWM 输出事件。总之，我认为目前硬件推送事件并不重要。

希望这能帮到你。

AM2754-Q1: AM275x AASRC GROUP Mode Output Channel Phase Rotation — Issue Report

Mingyang Hu — Thu, 10 Sep 2026 07:30:09 GMT

Part Number: AM2754-Q1

Chip / core: AM275x, issue observed and instrumented on the C7x DSP core (C75SS0_0), FreeRTOS.

SDK: freertos_sdk_am275x_12_01_00_28

Hi,

We are seeing the channel interleave phase of an AASRC GROUP output drift over time, and would like to know whether this is expected behaviour or a configuration mistake on our side.

AASRC is configured as a single GROUP channel with 12 channels. The input clock zone is slaved to an external A2B frame sync (McASP2_AFSR); the output clock zone is derived from a local 24.576 MHz reference clock. The two domains are therefore asynchronous, and we measured them to be 7.2 ppm apart — absorbing that offset is exactly why we use AASRC here.

To isolate the problem we inject a mono test tone on A2B media channel 0 and keep the other 11 channels digitally silent, then log which interleave lane carries the signal on each side of AASRC. At the AASRC input buffer the tone stays on lane 0 for the entire run. At the AASRC output buffer it migrates: 0 -> 11 -> 10 -> 9 -> ... -> 1 -> 0, wrapping through all 12 lanes.

The direction is always the same (towards lower lane index, consistent with the output domain being the faster one), but the step size is not constant — most events move the phase by 1 lane, while some events move it by more than one lane at once. Over a 27.7 minute run the phase wrapped through all 12 lanes, at irregular intervals ranging from 50 s to 355 s.

What makes this hard to handle is that nothing in the driver reports it. During that same run the AASRC error callback fired 0 times, the application dropped 0 input blocks, the 4-deep transaction ring never starved (3-4 transactions in flight throughout), and we verified by instrumentation that our transaction-to-buffer mapping never diverged (0 mismatches). The audio itself is clean — no glitches, no dropouts — only the channel positions shift.

Our questions:

In GROUP mode with asynchronous input/output clock zones, is the 12-channel interleave phase of the output DMA stream guaranteed to remain stable indefinitely? If not, is this a known limitation of GROUP mode?
A 12-channel GROUP maps onto 6 stereo SRC pairs sharing one DMA stream. Are the rate-compensation decisions of those 6 pairs shared, or does each pair decide independently? If independent, a divergence of N samples between pairs would rotate the interleave by N positions, which would match both the single-lane and the multi-lane steps we observe. Is that the mechanism?
Is there a register or API to read the current output FIFO level per stereo pair, or the interleave phase of the GROUP? We need a way to detect and re-align the phase that does not depend on audio content — our current probe only works because we can inject a single-channel test tone.
For this use case (resampling 12 A2B media channels from an external clock-slave domain into the local domain), is a single GROUP(12) the recommended configuration, or should we use 6 independent STEREO channels with separate DMA streams so that the pairs cannot drift relative to each other?

Full configuration, reproduction steps, detection method and raw logs are in the sections below.

Thanks,

AASRC_Channel_Phase_Rotation_Report.txt

RE: AM2754-Q1: AM275x AASRC GROUP Mode Output Channel Phase Rotation — Issue Report

Ritapravo Sarker — Wed, 23 Sep 2026 14:44:01 GMT

胡，你好

能否在本帖中分享一下你的链接器文件？
还有，你声明 mcasp/aasrc 缓冲区的代码片段。

问候，
里塔普拉沃

RE: AM5728: AM5728实现IEEE1588协议的一些疑问

Josue Zamitiz-Ayala — Wed, 23 Sep 2026 14:13:50 GMT

内部正在核实情况。如果有任何有用的信息，我会及时更新。

-约书亚

RE: AM5728: AM5728实现IEEE1588协议的一些疑问

chen geng — Wed, 23 Sep 2026 00:49:49 GMT

你建议的配置方法，实际上我在发这个帖子之前就都尝试过了的，都没有任何作用，看了你的截图，我又按截图里的参数配置，也没有效果

RE: AM5728: AM5728实现IEEE1588协议的一些疑问

Josue Zamitiz-Ayala — Tue, 22 Sep 2026 15:15:22 GMT

很高兴能帮到你。

我的建议没有起到帮助吗？

请解释一下以下问题：

[quote userid="675191" url="~/support/processors-group/processors---internal/f/processors---internal-forum/1681382/am5728-some-questions-about-am5728-implementing-the-ieee-1588-protocol/6490578"] 但我目前遇到了 CPTS 模块无法识别 PTP 数据包的问题[/quote]

我可以再向我们现有的团队确认一下，看看有没有人能帮忙。

祝你好运！

-约书亚

RE: AM3352: 升级uboot 从sdk 的2017 到2026，启动同一个fitimage 新的uboot 2026 出现Starting kernel ... 问题

Vinuchandran A V — Tue, 22 Sep 2026 10:14:08 GMT

你好，

还有一个测试可以帮助我们缩小问题范围。您能否尝试从标准的 meta-ti / TI 参考构建设置（而不是通过您的 OpenBMC 层）构建并启动内核，然后在您的开发板上使用 U-Boot 2025.01 进行测试？

我们之所以这样问，是因为将您的内核版本字符串与已知可用的参考版本进行比较后，我们发现除了内核版本之外，还有一些其他差异：

1. 内核版本标签：您的内核版本显示为“6.1.46-ti-gbbfe7dc461b4”；参考内核版本显示为“6.1.46-g1d4b5da681”（没有“-ti-”标签），这表明它可能来自不同的配方/层路径。
2. 工具链：您的版本使用 arm-openbmc-linux-gnueabi-gcc (GCC) 15.2.0 构建；参考版本使用 arm-oe-linux-gnueabi-gcc (GCC) 11.4.0 构建——这是一个明显较旧但经过更广泛验证的编译器，适用于此内核版本。

问候，
维努

AM3352: 升级uboot 从sdk 的2017 到2026，启动同一个fitimage 新的uboot 2026 出现Starting kernel ... 问题

shaohua xiong — Tue, 08 Sep 2026 09:25:50 GMT

Part Number: AM3352

我现在是将板子的uboot 从sdk 的2017 版本，升级到2026 版本，原本旧的uboot 是可以正常启动fitimage 的，且bootargs 配置为 'earlycon=ns16550a,mmio32,0x44e09000 console=ttyO0,115200n8 loglevel=8 root=/dev/ram0 rw'，可以正常看到kernel 启动log, 并正常启动，现在换成uboot 2026 版本后，bootargs 没变，还是 'earlycon=ns16550a,mmio32,0x44e09000 console=ttyO0,115200n8 loglevel=8 root=/dev/ram0 rw'，

=> bootm 0x88000000
## Loading kernel (any) from FIT Image at 88000000 ...
Using 'conf-1' configuration
Verifying Hash Integrity ... OK
Trying 'kernel-1' kernel subimage
Description: Linux Kernel
Created: 2011-04-05 23:00:00 UTC
Type: Kernel Image
Compression: uncompressed
Data Start: 0x880113f0
Data Size: 5902848 Bytes = 5.6 MiB
Architecture: ARM
OS: Linux
Load Address: 0x80300000
Entry Point: 0x80300000
Hash algo: sha256
Hash value: dbc1b7373ca439fe70850915362be5991d21580c810c08f430ae67eaa0a65bea
Verifying Hash Integrity ... sha256+ OK
## Loading ramdisk (any) from FIT Image at 88000000 ...
Using 'conf-1' configuration
Verifying Hash Integrity ... OK
Trying 'ramdisk-1' ramdisk subimage
Description: Ramdisk Image
Created: 2011-04-05 23:00:00 UTC
Type: RAMDisk Image
Compression: uncompressed
Data Start: 0x885b26e8
Data Size: 2108265 Bytes = 2 MiB
Architecture: ARM
OS: Linux
Load Address: 0x83000000
Entry Point: 0x83000000
Hash algo: sha256
Hash value: f2adcb28abc8db029d08a70b44922d17181ef12d965b85a1aaa959d4058625e6
Verifying Hash Integrity ... sha256+ OK
Loading ramdisk from 0x885b26e8 to 0x83000000
## Loading fdt (any) from FIT Image at 88000000 ...
Using 'conf-1' configuration
Verifying Hash Integrity ... OK
Trying 'fdt-1' fdt subimage
Description: Flattened Device Tree blob
Created: 2011-04-05 23:00:00 UTC
Type: Flat Device Tree
Compression: uncompressed
Data Start: 0x880000d0
Data Size: 70204 Bytes = 68.6 KiB
Architecture: ARM
Load Address: 0x80200000
Hash algo: sha256
Hash value: 922e664890d89e3e29510ceebcf806157170f2ac0492084f377b4ae4c9d527ac
Verifying Hash Integrity ... sha256+ OK
Loading fdt from 0x880000d0 to 0x80200000
Booting using the fdt blob at 0x80200000
Working FDT set to 80200000
Loading Kernel Image to 80300000
Using Device Tree in place at 80200000, end 8021423b
Working FDT set to 80200000

Starting kernel ...

CCCCCCCC

上面出现Starting kernel ... 后大概等了30s 后出现CCCC, 板子重启，由于kernel 在旧的uboot 可以正常启动，且bootargs 起了作用，我现在怀疑是新的uboot 导致，为什么新的uboot 下bootargs 没起作用，内核也没看到输出，不知道什么原因，大家有遇到过吗，能帮忙一下！

RE: AM5728: AM5728实现IEEE1588协议的一些疑问

chen geng — Tue, 22 Sep 2026 06:08:26 GMT

非常感谢你的帮助。确实我使用AM5728和AM5729的开发方式有点另类，没有使用liunx，也没有使用TI的RTOS，我用的是CCS环境下的纯裸机开发方式，目的是想打造一个以AM5728或者AM5729为核心的算法验证平台，所有代码、片内外设的寄存器全部手动可控。IEEE1588，我是打算用在工业自动化方向上，现在就遇到了这个CPTS模块没有识别到PTP数据包的问题。如果后面证明AM5728在EMAC上的PTP协议支持有问题的话，可能就只有考虑使用完整支持IEEE1588的PHY了，看了下，TI也有几款比较适合。

RE: AM3352: 升级uboot 从sdk 的2017 到2026，启动同一个fitimage 新的uboot 2026 出现Starting kernel ... 问题

shaohua xiong — Tue, 22 Sep 2026 05:55:47 GMT

目前测试看来，错误是随机的，是ddr 问题吗，但是我在uboot 下mtest 是ok 的

RE: AM3352: 升级uboot 从sdk 的2017 到2026，启动同一个fitimage 新的uboot 2026 出现Starting kernel ... 问题

shaohua xiong — Tue, 22 Sep 2026 05:52:30 GMT

另外我今天上午kernel 成功启动了一次，但是重启，又不行了

RE: AM3352: 升级uboot 从sdk 的2017 到2026，启动同一个fitimage 新的uboot 2026 出现Starting kernel ... 问题

shaohua xiong — Tue, 22 Sep 2026 05:51:35 GMT

我上面就是使用的TI-kernel 6.1.46 版本