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TUSB8044A: Assistance on TUSB8044A

David Choi — Wed, 23 Sep 2026 04:30:27 GMT

Part Number: TUSB8044A

I cannot navigate this section properly as the Forum part of Contact Support is in Chinese and I do not understand. Hopefully someone can direct me to the proper support team.

I have a question on the USB Hub controller TUSB8044A. Is a PD controller and EEPROM required to make this work? The output will only be 5V 1.5A each(two ports). Can it work standalone with TUSB8044A and HD3SS3220 per port?

I'm wondering what is the advantage of having I2C and EEPROM support is for my application.

RE: TUSB8044A: Assistance on TUSB8044A

Daniel — Wed, 23 Sep 2026 07:55:05 GMT

您好

When the upstream port is not connected and battery charging support is enabled for a port, the TUSB8044A drives the port power enable active. If AUTOMODE is disabled, then DCP mode is used. If AUTOMODE is enabled and fully automatic mode is disabled (FullAutoEn bit is cleared (Reg_25h Bit 0) or FULLAUTOz pin = 0), then TUSB8044A will start with highest enabled divider current mode (ACPx). The TUSB8044A will remain in highest current mode as long as a pull-up is not detected on DP pin. If an pull-up is detected on DP pin, then TUSB8044A will drive the port power enable inactive and switch to Galaxy mode, if enabled, or to DCP mode if Galaxy mode is disabled. The TUSB8044A will again drive the port power enable active. The TUSB8044A will remain in Galaxy mode as long as no pull-up is detected on DP pin. If an pull-up is detected on DP pin, then TUSB8044A will drive the port power enable inactive and transition to DCP mode. The TUSB8044A will again drive the port power enable active. In DCP mode, the TUSB8044A will look for a pull-up detected on DP pin or RxVdat. If a pull-up or RxVdat is detected on DP, the TUSB8044A will remain in DCP mode. If no pull-up or RxVdat is detected on DP pin after 2 seconds, the TUSB8044A will drive the port power enable inactive and transition back to ACPx mode. This sequence will repeat until upstream port is connected. When Automatic mode is enabled and full automatic mode is enabled (FullAutoEn Reg_25h bit 0 is set or FULLAUTOz pin = 1), TUSB8044A will perform same sequence described in previous paragraph with the addition of attempting all supported ACPx modes before sequencing to Galaxy Mode (if enabled) or DCP mode. The supported battery charging modes when TUSB8044A configured for SMBus or external EEPROM is detailed in Battery Charging Modes with SMBus/EEPROM Table. The supported battery charging modes when TUSB8044A configured for I2C but without an external EEPROM is determined by the sampled state of the pins. These modes are detailed in Battery Charging Modes without EEPROM Table.

请您参考这个部分datasheet说明，不同模式下可以达到不同的结果

RE: TUSB8044A: Assistance on TUSB8044A

Alice — Wed, 23 Sep 2026 06:30:02 GMT

您好，
已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: AFE7950: 60×AFE7950多通道射频直采数采测试系统（8.5–10.5 GHz）时钟同步与校准方案问询

ZHIPENG WANG — Wed, 09 Sep 2026 06:36:14 GMT

请问是否可以提供多芯片同步的参考方案？本项目系真实研发需求，如有回复不胜感谢！

AFE7950: 60×AFE7950多通道射频直采数采测试系统（8.5–10.5 GHz）时钟同步与校准方案问询

ZHIPENG WANG — Tue, 01 Sep 2026 07:43:22 GMT

Part Number: AFE7950

TI团队，您好：

我们正在设计一套多通道射频直采数据采集与测试系统，工作频率8.5–10.5 GHz，希望就全套TI方案的时钟同步与相位校准策略获得建议。

系统概况：

12块电路板，每块板5颗AFE7950（每板20发20收通道）；全系统共60颗AFE7950（240发 / 240收 / 120反馈）
AFE7950使用内部PLL，由全系统共用的单颗100MHz TCXO生成约12GSPS的DAC采样时钟（不做外部12GHz时钟分发）
两级时钟树：1颗根级时钟器件（LMK04828-EP或LMK04832）→ 12颗板级时钟器件，每颗向本板5颗AFE7950＋本地FPGA分发成对的REFCLK＋SYSREF
全部数据链路采用JESD204B/C Subclass 1；12块板的FPGA由中央时序控制器统一协调
所有通道要求相位相干，且上电周期间相位可重复

具体问题：

时钟拓扑： 对于60颗AFE7950在上电周期间要求确定性相位重复的场景，两级时钟树（1根级＋12板级，如LMK04828-EP）是否推荐？是否有更优的替代结构？
SYSREF： 推荐采用什么SYSREF频率和生成方式（我们正评估12.5MHz或6.25MHz；连续脉冲还是N脉冲）？SYSREF应该在根级生成后分发，还是在每块板本地生成？
确定性相位： 每颗AFE7950由共用的100MHz参考经内部PLL生成约12GHz采样时钟，仅靠Subclass 1的SYSREF对齐是否足以保证上电周期间器件间相位可重复？是否还需要额外步骤？
校准： 对于该频段的相位相多多通道采集系统，TI推荐的RX公共Pilot校准和TX反馈通道（FB）校准方法是怎样的（NCO相位/延时表补偿）？如何在温度变化下维持校准精度？
参考噪声预算： 100MHz倍频至约12GHz（倍频比约120，PLL环路带宽内理论相位噪声恶化约41.6dB），TI建议的参考相位噪声/抖动指标是多少？根级是否应采用抖动清洁器（LMK04828 PLL模式）而非纯分配器？

如有多AFE7950同步系统的参考设计、EVM指南或应用笔记，将不胜感激。

此致

RE: AFE7950: 60×AFE7950多通道射频直采数采测试系统（8.5–10.5 GHz）时钟同步与校准方案问询

ZHIPENG WANG — Wed, 09 Sep 2026 06:35:15 GMT

请问是否可以提供多芯片同步的参考方案？本项目系真实研发需求，如有回复不胜感谢！

RE: AFE7950: 60×AFE7950多通道射频直采数采测试系统（8.5–10.5 GHz）时钟同步与校准方案问询

ZHIPENG WANG — Tue, 08 Sep 2026 07:28:13 GMT

您好，盼复，感谢！

RE: AFE7950: 60×AFE7950多通道射频直采数采测试系统（8.5–10.5 GHz）时钟同步与校准方案问询

ZHIPENG WANG — Mon, 07 Sep 2026 01:09:30 GMT

期待您的回复。

RE: AFE7950: 60×AFE7950多通道射频直采数采测试系统（8.5–10.5 GHz）时钟同步与校准方案问询

Alice — Tue, 01 Sep 2026 07:47:54 GMT

您好，已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: AFE7950: AFE7950: ddcFactorRx = 2 with LMFSHdRx = 42220 in 2T2R mode for 1.2 GHz RX BW shows RX DDC-JESD async FIFO status 0x50

user5953526 — Mon, 03 Aug 2026 02:18:44 GMT

As an additional question related to the previous async FIFO discussion:

In our 4T4R hopping configuration, both TX and RX multi-NCO hopping via NCOSEL pins work correctly.

But in our 2T2R configuration:

TX hopping still works
RX hopping does not work

Details:

RX multi-NCO table load succeeds
RX NCOSEL pin values change correctly
Direct RX NCO update also works
However, the actual RX LO does not follow the selected RX multi-NCO slot

So it looks like only RX hopping via multi-NCO + NCOSEL pins fails in 2T2R.

Is this related to the earlier RX async FIFO / DDC-JESD configuration issue? Or is there any extra bringup requirement for RX NCOSEL pin control in 2RX mode?

Thanks.

AFE7950: AFE7950: ddcFactorRx = 2 with LMFSHdRx = 42220 in 2T2R mode for 1.2 GHz RX BW shows RX DDC-JESD async FIFO status 0x50

user5953526 — Fri, 31 Jul 2026 11:10:44 GMT

Part Number: AFE7950

Hi TI team,

I am working on an AFE7950 custom board and would like to confirm whether my use case is officially supported, and how to correctly close the remaining RX async FIFO issue.

Application goal
I need to achieve ~1.2 GHz RX bandwidth on AFE7950, but I am limited by the FPGA GTH maximum lane rate (~16.3 Gbps).

Because of this lane-rate limit, I cannot use a configuration that would require a higher JESD rate. My current target is:

2T2R-style sparse channel usage
only RXA + RXC used
RX bandwidth target = 1.2 GHz
JESD204C / 64b66b
LMFSHdRx = 42220
ddcFactorRx = 2
With this setup, Latte calculates RX lane rate around 12.16512 Gbps, which fits my FPGA GTH limit.
If I use ddcFactorRx = 4, lane rate is only about 6.08256 Gbps, but RX bandwidth is no longer sufficient.

Relevant configuration
My key RX-side settings are approximately:

sysParams.FadcRx = 2949.12
sysParams.rxEnable = [True, False, True, False] # RXA and RXC only
sysParams.ddcFactorRx = [2, 2, 2, 2]
sysParams.RRFMode = 5 # TDD non-shared
sysParams.jesdSystemMode = [3, 3]
sysParams.LMFSHdRx = ["42220"] * 4
sysParams.jesdTxProtocol = [2, 2] # ADC JESD TX = 64b66b
sysParams.fbEnable = [False, False]
TX side is not the main issue here.

What I observe
4RX enabled configurations are much more likely to work
Sparse 2T2R RX usage (RXA + RXC only) is where I see problems
Latte/CAFE link bring-up can complete and the captured RX waveform can look normal
However, checkAsyncFifoStatus() still reports:
ret, raw = setupParams.CAFE.checkAsyncFifoStatus(0)
# ret = 0
# raw = 0x0000000000000050
From the CAFE bit definition, 0x50 means:

bit4 = RXA DDC-JESD Async FIFO
bit6 = RXC DDC-JESD Async FIFO
So the issue appears to be specifically the RXA / RXC DDC-to-JESD async FIFO.

Additional observation
The RX waveform can still appear correct, so this looks more like a startup margin / FIFO boundary issue rather than a complete JESD link failure.

When I manually inspect FIFO pointers after bring-up, the result is not always cleanly centered. For example:

RXC:
(11.0, 11, 5, 12, 8.0)
RXA:
(3, 11, 3, 13, 10.0)
This suggests the FIFO pointer relationship is marginal/unstable, especially on RXA.

My questions
Is ddcFactorRx = 2 with LMFSHdRx = 42220 in this TDD / sparse 2T2R-style RX usage officially supported on AFE7950 for ~1.2 GHz RX bandwidth?

For RXA + RXC only usage, is there any TI-recommended setting for:

RX data mux
TDD mode / override
async FIFO offset
JESD mapper usage
startup sequence
If checkAsyncFifoStatus() returns 0x50 but the RX waveform looks normal, should this be treated as:

only a startup-margin warning, or
a real functional risk that can later affect repeatability / deterministic latency / temperature robustness?
Is there any TI-validated example script for:

AFE7950
ddcFactorRx = 2
LMFSHdRx = 42220
64b66b
preferably 1.2 GHz-class RX bandwidth
If sparse RX usage is not recommended in this mode, is TI’s recommended workaround to:

enable all 4 RX chains internally,
but only use RXA / RXC data in the system?
Why I am asking
My system bottleneck is the FPGA JESD lane rate, so I am trying to find the highest-confidence TI-supported way to achieve 1.2 GHz RX BW without exceeding ~16.3 Gbps lane rate.

Any clarification on whether this is a supported mode, and what TI recommends for the RX async FIFO issue in this exact case, would be greatly appreciated.

Thanks.

RE: AFE7950: AFE7950: ddcFactorRx = 2 with LMFSHdRx = 42220 in 2T2R mode for 1.2 GHz RX BW shows RX DDC-JESD async FIFO status 0x50

Taylor — Sun, 02 Aug 2026 22:48:35 GMT

您好，

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: ADS127L18EVM-PDK: ADS127L18 EVM: Irreducible ~100 fs Floor in Dual-Channel Residual Phase Noise Measurement.

Daniel — Tue, 28 Jul 2026 06:55:59 GMT

您好

https://www.ti.com/lit/an/slyt705/slyt705.pdf?ts=1785217982131

https://www.ti.com/lit/an/slyt237/slyt237.pdf?ts=1785218006488

https://www.ti.com/lit/an/slyt090/slyt090.pdf?ts=1785218013427

以上是相关文档资料请您参考。

ADS127L18EVM-PDK: ADS127L18 EVM: Irreducible ~100 fs Floor in Dual-Channel Residual Phase Noise Measurement.

C.H. Hsueh — Sun, 26 Jul 2026 08:44:13 GMT

Part Number: ADS127L18EVM-PDK

Hi TI team,

We are measuring the residual phase noise / relative timing drift between two channels of ADS127L18 EVM.

Setup: a single tone (frequency) from a source is split into two, fed into two ADC channels independently. After digital IQ demodulation per channel, we compute the phase difference (φ_ch1 − φ_ch2) to reject common-mode noise (source phase noise, clock jitter). The differential phase is converted to delay (τ = φ/2πf) and analyzed via Allan deviation.

Observations that confuse us:

1. Regardless of input frequency or amplitude, the relative delay Allan deviation always converges to a floor of ~100 fs. Higher frequencies converge to this floor faster, but the floor value is the same.

2. Injecting a pilot tone before the splitter does NOT improve the ~100 fs floor. The residual noise appears to be frequency-independent and not removable by common-mode correction.

Since common-mode noise (source, clock) is already rejected by the differential measurement, and pilot tone fails to help, the floor must originate from something inside each ADC channel that is both channel-independent and pilot-insensitive.

What could cause this ~100 fs irreducible floor? Is this a known behavior of ADS127L18 in dual-channel relative timing applications?

We can share Allan deviation plots and raw data if needed. Thank you.

Best regards,
C.H. Hsueh

RE: ADS127L18EVM-PDK: ADS127L18 EVM: Irreducible ~100 fs Floor in Dual-Channel Residual Phase Noise Measurement.

Lydia — Mon, 27 Jul 2026 00:00:56 GMT

Hello, we have received your case and the investigation will take some time. Thank you for your patience.

LMX8410L: 技术咨询

Xu Allen — Wed, 22 Jul 2026 04:34:43 GMT

Part Number: LMX8410L

你好，

在使用LMX8410RGZT是遇到两个问题，请帮忙解答一下，谢谢！

1、官网没有LMX8410LEVM的gerber，请提供一下。

2、参考设计中有三根电源线走线特意绕长，这是出于什么考虑？是否可以不用这么做？

RE: LMX8410L: 技术咨询

Vivian Gao — Wed, 22 Jul 2026 09:46:33 GMT

数据手册第10部分有写layout要求，详见10.1.1 High Frequency Trace Routing和10.1.2 Power Trace Routing。

评估板展示的最佳实践，建议按照评估板去做。

主要目的：

抑制高频噪声耦合
隔离数字噪声对射频电路的影响
降低电源引脚的高频阻抗

TI没有公开gerber文件。

RE: LMX8410L: 技术咨询

Vivian Gao — Wed, 22 Jul 2026 04:46:33 GMT

感谢您对TI产品的关注。
我们正在核实您的问题，请等待我们的答复。

RE: AFE7799: 库存订阅推送 API返回403状态码，麻烦看一下,谢谢。

Eirwen — Tue, 16 Jun 2026 23:35:32 GMT

您好，

E2E技术论坛旨在解决客户在使用TI产品过程中遇到的技术问题。
建议您请按照以下方式联系客户支持部门，会有客服为您提供帮助。
www.ti.com/.../customer-support.html

AFE7799: 库存订阅推送 API返回403状态码，麻烦看一下,谢谢。

huixin an — Tue, 16 Jun 2026 09:49:07 GMT

Part Number: AFE7799

在TI store API 套件中设置了库存订阅推送 API，但是在postman用POST请求的时候，返回403错误，截图如下所示，麻烦看一下，给出一个解决方案，谢谢了。

RE: AFE7799: 库存订阅推送 API返回403状态码，麻烦看一下,谢谢。

Eirwen — Tue, 16 Jun 2026 23:31:16 GMT

已经收到了您的案例，调查需要些时间，感谢您的耐心等待。

RE: AFE7903: Can AFE7903 work for wifi 6E 5G and 6G frequency band? which IC can support wifi 6E frequency band?

Vivian Gao — Fri, 15 May 2026 09:39:22 GMT

感谢您对TI产品的关注！由于 AFE7903 产品属于信息受限制产品，为更加有效地解决您的问题，请您将问题发布在E2E英文技术论坛上（英文论坛对应子论坛链接：https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum），将由资深的英文论坛工程师为您提供帮助。

AFE7903: Can AFE7903 work for wifi 6E 5G and 6G frequency band? which IC can support wifi 6E frequency band?

Xiaodong Yu — Fri, 15 May 2026 08:59:52 GMT

Part Number: AFE7903

Dear Sir/Madam

we want to make a product to work on Wifi 6E frequency band especially the 5G and 6GHz band. We checked AFE7900 adc/dac, we find the maxim ADC rate is 3Gsps. SinceWIFI 6E 5G and 6GHz band are very close we can not seperate them. So the total bandwidth of 5G+6G band is 2GHz, it seams 3Gsps ADC can not work on the 2GHz bandwith. is it correct? How can we solve the issue. any other TI's IC can work on Wifi 6E?

Regards

AWR2188-SAFETY: AWR2188 document download access denied

zhaoyu xiong — Sun, 03 May 2026 14:37:00 GMT

Part Number: AWR2188-SAFETY

AWR2188 technical documentation access denied. Please approve my download request.

RE: AWR2188-SAFETY: AWR2188 document download access denied

Alice — Sun, 03 May 2026 23:54:45 GMT

Hello,

Please try to request using a TI account that is bounded with a company email.

If you have further concern, please contact customer support center to get support.