如题。
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HS_DEBUG1_P/M -》 LVDS_FRCLK
The LVDS_FRCLK is a basically an ADC sample clock . The is one clock cycle for one ADC sample width. If you have 16bit ADC samples this signal will be like a clock for 16bits.
HS_DEBUG2_P/M -》 LVDS_VALID
LVDS_VALID would be high during the complete period of chirp data transfer out.
使用LVDS接口时,HS_DEBUG2_P/M不是必须的。更多信息,请参考下面的论坛讨论。
PS:这4个信号在使用CSI接口时是不需要使用的。