仿真、硬件和系统设计工具论坛 - 最近的话题

LM3481: 需要确认下LM3481的DR引脚输出波形对照原理图是否符合预期

wenbo zhao — Wed, 06 May 2026 03:14:17 GMT

Part Number: LM3481

UCC256404: Simulation issues with UCC256404 and UCC28056

XX W — Tue, 05 May 2026 07:50:31 GMT

Part Number: UCC256404
Other Parts Discussed in Thread: UCC24624, UCC28056

Dear TI Technical Support Team,

Hello! I am currently designing a half-bridge LLC resonant converter using the UCC256404B controller, the UCC28056B PFC controller, and the UCC24624 synchronous rectifier driver. During simulation and design, I have encountered several critical issues and would greatly appreciate your professional guidance.

First, regarding MOSFET current and voltage spikes at startup: In simulation, when using MOSFET models, I observed large current and voltage spikes on the primary-side MOSFETs at the moment of startup. Adding a small amount of parasitic inductance does not eliminate these spikes. After reviewing relevant materials, I suspect the issue is caused by the MOSFETs' initial parasitic capacitance being zero and hard switching. Is there a solution for this?

Second, regarding soft start and output voltage overshoot: I am facing a dilemma with the soft start implementation. Increasing the soft start capacitor value to slow down the voltage ramp‑up causes severe output voltage overshoot. Adjusting the feedback loop parameters to suppress the overshoot then introduces loop stability problems. Is there a way to solve both issues simultaneously?

Third, regarding the UCC28056 startup issue: Sometimes, due to a small voltage difference during startup, the UCC28056 enters CCM mode, which creates an inductor current spike. How can this problem be resolved?

Fourth, regarding integrated simulation of multi‑controller designs: My design uses three separate ICs (UCC256404B, UCC28056B, UCC24624), each with its own simulation model. I would like to simulate the complete system in the same environment to verify end‑to‑end performance. Is it possible to place the three model files into the same project? If so, how should I do it?

Thank you for your time and support. I look forward to your reply.

Best regards,

TINA-TI_SIMP_CHINESE: 我在尝试uaf42的傅里叶变换时出现50hz意外高幅值现象

xh z — Mon, 04 May 2026 13:44:08 GMT

Part Number: TINA-TI

求问各位大佬为什么，图片中能看到中心频率在40hz，但是傅里叶分析产生了多余的50hz分量，这个分量的数值比中心频率40hz的幅值还要大，

542143.TSC

TINA-TI_SIMP_CHINESE: 无法下载该软件

yang liu — Wed, 29 Apr 2026 13:49:28 GMT

Part Number: TINA-TI

无法下载该软件

UCC28070: Why are the output and input voltage values the same in the UCC28070 transient simulation project downloaded from the TI website?

wen maoquan — Sat, 25 Apr 2026 09:18:27 GMT

Part Number: UCC28070

The official simulation circuit does not perform voltage boosting. What's the problem here? I didn't make any changes to the circuit. Does not match the application description. PFC has no drive output.

TPS1689-CALC: PSPICE-FOR-TI: Concurrent device access limit.

user6369895 — Wed, 22 Apr 2026 14:43:28 GMT

Part Number: TPS1689-CALC

I get a "concurrent device access limit" error when I try to install PSpice on my computer at work. please help delink the previous installations. The computers are no longer in service.

C2000WARE-DIGITALPOWER-SDK: 下载SKD遭拒

Roy Yan — Wed, 22 Apr 2026 02:37:48 GMT

Part Number: C2000WARE-DIGITALPOWER-SDK

下载SKD遭拒

TIDA-010270: 设计文件申请

Yuxi Fang — Tue, 21 Apr 2026 06:09:33 GMT

Part Number: TIDA-010270

你好，

我想请问一下，我在TIDA-010270的设计参考中了解到原理图需要从design files中获得，但是我提交申请后被拒了，我想知道被拒的原因，以及是否能够再次申请，这些设计文件对我的实验非常重要，万分感谢！

TIDA-010963: TIDA-010963参考设计的钻孔文件哪里有？

3694043 — Tue, 21 Apr 2026 03:15:00 GMT

Part Number: TIDA-010963

TIDA-010963参考设计中的GERBER文件中钻孔文件哪里有？

TPSM82823A: TPSM82823ASILR 标签DC2548+ ,但实际零件标记59

June KE — Mon, 20 Apr 2026 09:33:52 GMT

Part Number: TPSM82823A

你好，TI团队
我们有一批TPSM82823ASILR 零件（卷轴标签日期代码2548）但实际零件标记59

我们注意到实际设备上标记的日期代码与卷轴标签不同。您能否确认这是否正常，并解释一下差异的原因？

TMS320F28379D: Can the CLB be configured without using SysConfig?

hzs hzs — Fri, 10 Apr 2026 06:23:41 GMT

Part Number: TMS320F28379D
Other Parts Discussed in Thread: SYSCONFIG

I am working with the CLB module on TMS320F28379D. I am trying to implement a simple timer (counter + FSM as T flip-flop) to toggle a GPIO, using only driverlib functions (clb.h, xbar.h) without SysConfig.

However, I am running into issues:

The counter does not seem to generate MATCH1 events (COUNT0_MATCH1 is always 0).
The output LUT's FN field cannot be written with 0xAA (only 0xFF works when writing directly to the register).
The FSM output does not behave as expected.

I have checked:

CLB and EPWM1 clocks are enabled.
GLOBAL_EN is set to 0 during configuration and 1 after configuration.
Direct register writes (HWREG) do not solve the issue.

My question is:
Is SysConfig tool mandatory for configuring the CLB?

(Can the CLB be configured without using SysConfig?)
Can the CLB be fully configured using only driverlib functions, or are there some low-level configurations that must be done through SysConfig-generated code?

If it is possible without SysConfig, could you point me to any working example (without SysConfig) or highlight what might be missing in my configuration?

Thank you for your support.

// ============================================================================
// Project 1: CLB Timer to Toggle LED
// ============================================================================
// Function: Use counter + FSM to implement a T flip-flop for automatic LED toggling
// Output: GPIO25 (OUTPUTXBAR2) - available on LaunchPad
// Period: 1 second @ 100MHz = 100,000,000 (EPWM1 clock)
//
// Signal flow:
//   System clock ──→ Counter 0 (count up) ──→ MATCH1 event ──→ FSM0 (T flip-flop) ──→ Output
//
// Truth tables:
//   1. FSM_LUT_OUT = S0
//      Input order (EXT_IN1, EXT_IN0, S1, S0)
//      16-bit truth table: 0xAAAA
//      (EXT_IN1,EXT_IN0,S1,S0) → output = S0
//      Example: 0000→0, 0001→1, 0010→0, 0011→1, ...
//
//   2. S0_next = S0 ^ EXT_IN0 (T flip-flop)
//      Input order (EXT_IN1, EXT_IN0, S1, S0)
//      16-bit truth table: 0x5A5A
//      Example: 0000→0, 0001→1, 0010→1, 0011→0, ...
//
//   3. Output LUT: OUT = IN0 (pass-through)
//      3-input LUT, 8-bit truth table: 0xAA
//      Input order (IN2, IN1, IN0): 000→0, 001→1, 010→0, 011→1, ...
// ============================================================================
    CLB_disableCLB(CLB1_BASE);  // Force GLOBAL_EN = 0

    // ------------------------------------------------------------------------
    // Step 1: Configure counter input sources
    // ------------------------------------------------------------------------
    // The counter requires MODE_0 and MODE_1 to control counting
    // We want the counter to always count up, so MODE_0=1 (enable), MODE_1=1 (count up)
    //
    // Select values from Table 26-4(from TRM (Technical Reference Manual) ):
    //   0x00 = Always 0
    //   0x08 = Always 1
    //
    // CLB_selectCounterInputs() parameters are 32-bit, format:
    //   bits 4-0   = select value for unit 0
    //   bits 9-5   = select value for unit 1
    //   bits 14-10 = select value for unit 2
    // We only use unit 0; set unit 1/2 to 0

    uint32_t mode0 = (0x08 << 0) | (0x00 << 5) | (0x00 << 10);  // MODE_0 = Always 1
    uint32_t mode1 = (0x08 << 0) | (0x00 << 5) | (0x00 << 10);  // MODE_1 = Always 1
    uint32_t reset = 0x00000000;   // RESET = Always 0 (no reset)
    uint32_t event = (0x03 << 0) | (0x00 << 5) | (0x00 << 10);  // EVENT = MATCH1

    CLB_selectCounterInputs(CLB1_BASE, reset, event, mode0, mode1);

    // ------------------------------------------------------------------------
    // Step 2: Configure counter load and match values
    // ------------------------------------------------------------------------
    // load:   counter starts from 0
    // match1: when counter value equals match1, MATCH1 outputs a high pulse
    // match2: not used
    //
    // CLB clock = 100MHz, 1 second timer = 100,000,000 counts
    CLB_configCounterLoadMatch(CLB1_BASE, CLB_CTR0,
                               0x00000000U,      // load = 0
                               50000000U,              // match1 = 50000000
                               0x00000000U);     // match2 = 0

    // ------------------------------------------------------------------------
    // Step 3: Configure counter mode
    // ------------------------------------------------------------------------
    // COUNT_EVENT_CTRL_0 = 0 (load preset value on EVENT)
    CLB_configMiscCtrlModes(CLB1_BASE, 0x00000000);

    // ------------------------------------------------------------------------
    // Step 4: Configure FSM0 input sources
    // ------------------------------------------------------------------------
    // FSM0's EXT_IN0 receives the counter's MATCH1 signal (to trigger state toggle)
    // Table 26-4: COUNTER_0 MATCH1 = 0x03
    uint32_t fsmExternal0 = (0x03 << 0) | (0x00 << 5) | (0x00 << 10);  // EXT_IN0 = MATCH1
    uint32_t fsmExternal1 = 0x00000000;   // EXT_IN1 = Always 0 (not used)
    uint32_t fsmExtra0 = 0x00000000;      // EXTRA_EXT_IN0 = Always 0 (not used)
    uint32_t fsmExtra1 = 0x00000000;      // EXTRA_EXT_IN1 = Always 0 (not used)

    CLB_selectFSMInputs(CLB1_BASE, fsmExternal0, fsmExternal1, fsmExtra0, fsmExtra1);

    // ------------------------------------------------------------------------
    // Step 5: Configure FSM LUT function (output logic)
    // ------------------------------------------------------------------------
    // FSM_LUT_OUT = S0 (directly output current state)
    // Truth table calculation (input order: EXT_IN1, EXT_IN0, S1, S0):
    //   We only care about S0, with EXT_IN1=0, EXT_IN0=any, S1=0
    //   Output is 0 when S0=0, 1 when S0=1
    //   16-bit truth table = 0xAAAA (1010 1010 1010 1010)
    CLB_configFSMLUTFunction(CLB1_BASE, 0xAAAA, 0x0000);

    // ------------------------------------------------------------------------
    // Step 6: Configure FSM next state (T flip-flop)
    // ------------------------------------------------------------------------
    // S0_next = S0 ^ EXT_IN0 (toggle on each MATCH1 pulse)
    // Truth table (EXT_IN0, S0):
    //   00→0, 01→1, 10→1, 11→0
    //   16-bit truth table = 0x5A5A
    CLB_configFSMNextState(CLB1_BASE, 0x5A5A, 0x0000, 0x0000);

    // ------------------------------------------------------------------------
    // Step 7: Configure output LUT (3-input, for final output)
    // ------------------------------------------------------------------------
    // outputCfg format (32-bit):
    //   bits 4-0:   IN0 select value
    //   bits 9-5:   IN1 select value
    //   bits 14-10: IN2 select value
    //   bits 22-15: FN (8-bit truth table)
    //
    // We use OUT13 (can connect to Output X-BAR)
    // IN0 = FSM_0 LUT output (Table 26-4: 0x06)
    // FN = 0xAA (8-bit: 1010 1010) meaning OUT = IN0
    uint32_t outputCfg = (0x06 << 0) | (0x00 << 5) | (0x00 << 10) | (0xAA << 15);

    // Configure OUT5 (OUTLUT5)
    CLB_configOutputLUT(CLB1_BASE, CLB_OUT5, outputCfg);

    // Enable OUT13 output
    CLB_setOutputMask(CLB1_BASE, CLB_OUTPUT_05, true);
    CLB_setOutputMask(CLB1_BASE, CLB_OUTPUT_13, true);

    // ------------------------------------------------------------------------
    // Step 8: Configure Output X-BAR (route CLB output to GPIO)
    // ------------------------------------------------------------------------
    // Table 9-4: G3 option 2 = CLB1_OUT13
    // Route CLB1_OUT13 to OUTPUTXBAR2 (GPIO25)
    XBAR_setOutputMuxConfig(XBAR_OUTPUT2, XBAR_OUT_MUX03_CLB1_OUT5);
    XBAR_enableOutputMux(XBAR_OUTPUT2, XBAR_MUX03);

    // ------------------------------------------------------------------------
    // Step 9: Start CLB
    // ------------------------------------------------------------------------
    CLB_enableCLB(CLB1_BASE);

26.4.1 Static Switch Block

The Static Switch Block provides the configurable connectivity between the submodules in the CLB tile. The outputs of all the submodules and the eight external inputs are connected to a common internal bus inside the tile. Every input port has a 32-to-1 multiplexer and an associated 5-bit selection value that allows the user to select one of the inputs on the bus. The only restrictions are certain signals (described below) that are tied off in the design to prevent creation of accidental combinatorial loops.

TPS59641: TPS59641 公版layout

Chen Hongqi — Tue, 07 Apr 2026 08:01:09 GMT

Part Number: TPS59641

Hi Sir,

我查看Datasheet，Pin.43 V5DRV 透過電阻連接到 5V 電源層，並使用 ≥1 μF 的陶瓷電容旁路至 GND。

但Datasheet的公版建議線路沒有畫到電阻電容去耦，是只需要在Pin.49旁擺放即可嗎?

請協助提供公版layout的資訊

UCC28750-SIMPLIS: POWERSTAGE-DESIGNER下载被拒绝

FU RUNKANG — Sun, 05 Apr 2026 08:29:51 GMT

Part Number: UCC28750-SIMPLIS

下载一直被拒绝

UCC25600-DESIGN-CALC: Power Stage Designer 我申请这个软件老是被拒绝。我的邮箱注册 runkang.fu@aodicharger.com

FU RUNKANG — Fri, 03 Apr 2026 02:56:38 GMT

Part Number: UCC25600-DESIGN-CALC

你好：

如上所述。

LM5143DESIGN-CALC: LM5143-Q1四相电源设计仿真

? ? — Thu, 02 Apr 2026 01:37:40 GMT

Part Number: LM5143DESIGN-CALC
Other Parts Discussed in Thread: LM5143-Q1

我使用下载的LM5143-Q1仿真模型进行修改，绘制了四相的电源。目前已经也可以run起来了，但是没有输出的波形，各节点电压都为0，只有输入电压有显示，请问要如何解决？附件是我的仿真DNS文件LM5143-Q1_TRANS.zip

UNIFLASH: UNIFLASH: Warning issue when downloading programs with Uniflash

Yuhang Li — Mon, 30 Mar 2026 08:30:30 GMT

Part Number: UNIFLASH

During the development process using the F28P65, the following warning appears when using Uniflash to program, pointing to a memory allocation issue.

However, after comparing with the datasheet, there are no non-compliant areas, and the program runs normally. Additionally, I only used CPU1. I am somewhat confused about this issue, so I hope to get some answers. Below is the text content of my CMD, hoping it can help in getting assistance:

MEMORY
{

BEGIN : origin = 0x080000, length = 0x00003B
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B1, length = 0x00024F
RAMM1 : origin = 0x000400, length = 0x000400

RAMD0 : origin = 0x00C000, length = 0x002000
RAMD1 : origin = 0x00E000, length = 0x002000
RAMD2 : origin = 0x01A000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection
RAMD3 : origin = 0x01C000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection
RAMD4 : origin = 0x01E000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection
RAMD5 : origin = 0x020000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection

RAMLS0 : origin = 0x008000, length = 0x004000
/*
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
*/
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000

// RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
// RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory

RAMGS0 : origin = 0x010000, length = 0x002000
RAMGS1 : origin = 0x012000, length = 0x002000
RAMGS2 : origin = 0x014000, length = 0x002000
RAMGS3 : origin = 0x016000, length = 0x002000
RAMGS4 : origin = 0x018000, length = 0x002000

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 20012000
GROUP { /* GROUP memory ranges for crc/checksum of entire flash */
#endif
#endif
/* BEGIN is used for the "boot to Flash" bootloader mode */

// BEGIN : origin = 0x080000, length = 0x000002 // Update the codestart location as needed
/* Flash Banks (128 sectors each) */
CNT00 : origin = 0x08003B, length = 0x000080 /* on-chip FLASH */
FLASH_BANK0 : origin = 0x0800BB, length = 0x17F44 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection

FLASHFLAG : origin = 0x097FFF, length = 0x00001
FLASH_BANK0_APP : origin = 0x098000, length = 0x08000
FLASH_BANK1 : origin = 0x0A0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK3 : origin = 0x0E0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK4 : origin = 0x100000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection

#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 20012000
} crc(_ccs_flash_checksum, algorithm=C28_CHECKSUM_16)
#endif
#endif

CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000400
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000400

CLATOCPURAM : origin = 0x001480, length = 0x000080
CPUTOCPURAM : origin = 0x001500, length = 0x000080
CLATODMARAM : origin = 0x001680, length = 0x000080
DMATOCLARAM : origin = 0x001700, length = 0x000080

CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
}

SECTIONS
{
codestart : > BEGIN
.text : > FLASH_BANK0, ALIGN(8)
.cinit : > FLASH_BANK0, ALIGN(8)
.switch : > FLASH_BANK0, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */

.stack : > RAMM1
cnt_00 : > CNT00
.flashflag : > FLASHFLAG
#if defined(__TI_EABI__)
.bss : > RAMLS0
.bss:output : > RAMLS0
.init_array : > FLASH_BANK0, ALIGN(8)
.const : > FLASH_BANK0, ALIGN(8)
.data : > RAMLS0
.sysmem : > RAMLS0

#else
.pinit : > FLASH_BANK0, ALIGN(8)
.ebss : > RAMLS0
.econst : > FLASH_BANK0, ALIGN(8)
.esysmem : > RAMLS0
#endif

ramgs0 : > RAMGS0, type=NOINIT
ramgs1 : > RAMGS1, type=NOINIT

#if defined(__TI_EABI__)
.TI.ramfunc : {} LOAD = FLASH_BANK0,
RUN = RAMLS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU1_TO_CPU2_COPY_TO_M1_RAM > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
#else
.TI.ramfunc : {} LOAD = FLASH_BANK0,
RUN = RAMLS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
ALIGN(8)

MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU1_TO_CPU2_COPY_TO_M1_RAM > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT

#endif
/* crc/checksum section configured as COPY section to avoid including in executable */
.TI.memcrc : type = COPY
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

TMS320F28335: RS485发送数据异常问题

w lf — Tue, 24 Mar 2026 09:53:26 GMT

Part Number: TMS320F28335

rs485的RE DE控制引脚连接DSP的GPIO13（已看原理图），但是GPIO13即使不配置，DSP也可以接收到PC发送的数据（且能通过CRC），或配置GPIO13但是设置为发送模式PC按道理发送给DSP数据不会被DSP接受，但是仍然能接收到PC的数据，不论怎么修改数据DSP都发送不到

另外：

1、RS485 A B线没有接反，（尝试反接后收发都无数据）

2、波特率验证无误

UCC25600-DESIGN-CALC: UCC25600, Simulation Design Verification

Abdul Basit — Sat, 14 Mar 2026 21:54:13 GMT

Part Number: UCC25600-DESIGN-CALC
Other Parts Discussed in Thread: UCC25600, UCC27200

I am designing a full-bridge LLC resonant converter using UCC25600 with UCC27200 gate driver to drive the full bridge. For this DC-DC converter, the specifications are Vin=38-42V, Vout=24V, Pout=500W, and I have selected Frequency=100KHz. I have used the document SLUP263 for my understanding and simulated the circuit in PSpice for TI. I want to send my design files, so for that, if an email address is shared, I will then send the files. The simulation is taking a lot of time, and I also want an expert opinion on the design and also all the component values that I have used before making the hardware.

TMS320C5515: 如何获得C55BootImage.exe这个可执行文件，我需要它生成可执行bin文件以从SD卡启动

kai — Wed, 11 Mar 2026 03:03:07 GMT

Part Number: TMS320C5515

我需要C55BootImage.exe 可执行文件

PSPICE-FOR-TI: 如何添加EPC提供的.net文件，来进行仿真

Ke Wang — Tue, 10 Mar 2026 07:05:57 GMT

Part Number: PSPICE-FOR-TI
Other Parts Discussed in Thread: LMG1210

在对lmg1210进行仿真时，希望通过添加真实的GaN开关来进行仿真。但如EPC2204这样的模型官方只提供.net文件。在把文件后缀名改为.lib，然后将.subckt大写结尾.ends 大写并加 EPC2204A后，依然无法读取仿真模型

TPS54-57XX0-CALC: TPS543A22RYSR, TPS543620RPYR,TPS543820RPYR 这三颗芯片的仿真文件

Rita Liang — Mon, 09 Mar 2026 06:28:45 GMT

Part Number: TPS54-57XX0-CALC

有在官网下载了仿真文件，但是用不了，需要如下帮助：

1.看能否帮忙弄个 simplis正式版的安装/license，以解燃眉之急
2.通过贵司正式版软件，直接帮忙export出 SPICE(.sp)文件，大幅提升准确性/实效性

我司用途只是需要电源芯片的准确VRM特性，用于电源完整性仿真（PDN阻抗和AC瞬态）

PSPICE-FOR-TI: PSpice认证失败

Zheng Zheng — Sun, 08 Mar 2026 13:04:05 GMT

Part Number: PSPICE-FOR-TI

成功下载了PSpice for TI, 但在运行setup.exe时，填写email和access key以后出现：unable to access the URL reqired for installation.为什么会这样，怎么解决？

谢谢！

PSPICE-FOR-TI: PSpice认证失败

Zheng Zheng — Sun, 08 Mar 2026 13:02:57 GMT

Part Number: PSPICE-FOR-TI

成功下载了PSpice for TI, 但在允许setup.exe时，填写email和access key以后出现：unable to access the URL reqired for installation.为什么会这样，怎么解决？

谢谢！

TMS320F280039: 咨询PMP41134参考设计的技术资料

Jiatong Zhan — Sat, 07 Mar 2026 03:01:15 GMT

Part Number: TMS320F280039
Other Parts Discussed in Thread: PMP41134

尊敬的TI工程师：

您好！

我是一名研发工程师，正在开发**25kW双向隔离DC/DC**（输入800V，输出150-1000V），对贵司的 **PMP41134参考设计**（SRC-DAB）很感兴趣。

能否提供以下资料：
1. 详细的应用笔记
2. PLECS/Simulink仿真模型
3. 固件源代码等

我的邮箱：1224922140@qq.com

感谢！

此致

TINA-TI_SIMP_CHINESE: TINA-TI下载被出口管制拒绝，需要协助解决下载权限

keyan chen — Fri, 06 Mar 2026 09:13:24 GMT

Part Number: TINA-TI
Other Parts Discussed in Thread: TINA-TI

您好，我是北京航空航天大学的学生，需要下载TINA-TI用于民用学术研究和电路仿真。但在下载时，我的出口审批申请被拒绝了。我的myTI账号信息如下： - 姓名：Chen Keyan - 邮箱：1343552563@qq.com - 单位：Beihang University - 国家：China 我确认该软件将仅用于民用、非军事的教育用途，不会用于任何受限用途。请协助解决此问题，以便我合法下载该软件进行学习和研究。

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