请教一下,规格书上说如果不使用内部DCDC,VDDR接的就是内部LDO。那怎么判断芯片是使用内部DCDC还是内部LDO呢,是芯片自动感应,还是外面人为设置 ?
谢谢!
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请教一下,规格书上说如果不使用内部DCDC,VDDR接的就是内部LDO。那怎么判断芯片是使用内部DCDC还是内部LDO呢,是芯片自动感应,还是外面人为设置 ?
谢谢!
需要通过软件设置,修改CCFG文件
原理图上就是Vddr是NC,我们烧录时把各个Jtag脚都接了,TDI、TDO、nSRESET、TCK、TMC、电源、地,都没反应。每根线是跳线,同样的线烧买来的开发板没问题。
芯片内部的电源使用分布图不知道能否公布一个,我们想了解下电源使用究竟是什么原理
芯片内部的电源使用分布图不知道能否公布一个,我们想了解下电源使用究竟是什么原理
查看6.3节:https://www.ti.com.cn/cn/lit/ug/swcu117i/swcu117i.pdf
另CC2640r2f使用cjtag,不需要连接TDO TDI
如果Vddr是NC,有没有烧录不上的风险
无论是LDO还是DCDC,VDDR都不能悬空
如不愿提供原理图,则参照参考设计https://www.ti.com.cn/tool/cn/LAUNCHXL-CC2640R2#design-files
我还是有个疑问,6.3节上说Vddr要么是从DCDC来,要么是从globle LDO来。从1.3.13.1节中的截图来看,似乎默认还是从globle LDO来的。难道此截图有误,Vddr实际是默认的是从DCDC来的 ?
Maximum efficiency is obtained by using the internal DC/DC converter, and it requires an external inductor
(LDCDC) and capacitor (CDCDC). The components should be placed as close as possible to the
CC13xx/CC26xx device and it is important to have a short current return path for from the CDCDC ground
to the pad on the chip (see Section 4.7). In addition, the bulk capacitor on VDDS should be placed close
to the VDDS_DCDC-pin. The actual value of LDCDC, CDCDC and CBULK vary from device to device.
For the actual values, see the device-specific reference design.
When operating in DC/DC mode, the power system dynamically switches between the Global LDO and
DC/DC converter depending on the required load to achieve maximum efficiency. If VDDS drops below
2.0 V, the DC/DC converter will be less efficient than the LDO and the device will run in global LDO mode.
For systems operating with VDDS less than 2.0 V, consider either global LDO or external regulator mode
to save component cost and board area.
我们拿开发板实测,把L1去除,这样Vddr处于NC,其电压约1.7V。此状态下,能将LDO模式的程序烧录进去,并能正常运行。
但现在有个问题,我们自己做的板子,Vddr同样处于NC却无法识别芯片和无法烧录(如果不接烧录板,自己板子的TCK的电平大约3.3V,而接了烧录板TCK的电平不到2V),不知道原因在哪里
没有有原理图很难判断原因,你只能对照参考设计检查二者不一样的地方
硬件设计审查按照这里的步骤操作:
https://www.ti.com.cn/tool/cn/SIMPLELINK-2-4GHZ-DESIGN-REVIEWS